fpga-lab-2/HDL/sigdel.sv

//top-level module
module sigdel
#(
    PHACC_WIDTH = 27
) (
	//clock and reset
	input logic clk, clr_n,
	//control slave
	input logic [31:0] wr_data,
	input logic wr_n,
	output logic fout
);

	logic [7:0] phinc_val, phase, sine;
	
	//control slave logic
	always_ff @ (posedge clk or negedge clr_n) begin
		if (!clr_n) begin
			phinc_val[7:0] <= 8'd0;
		end else	begin
			if (!wr_n) begin
				phinc_val[7:0] <= wr_data[31:0];
			end
		end
	end

	phacc phacc_inst (.phinc(1'b1), .clk(clk), .reset(clr_n), .phase(phase));
	defparam phacc_inst.WIDTH = PHACC_WIDTH;
	
	sinelut sinelut_inst (
       .address (phase), .clock (clk), .q(sine)
	);
	
	sdmod sdmod_inst (
	    .val(sine), .clk(clk), .reset(clr_n), .daco(fout)
	);
endmodule