22 lines
404 B
Systemverilog
22 lines
404 B
Systemverilog
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//top-level module
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module sigdel
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#(
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PHACC_WIDTH = 14
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) (
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//clock and reset
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input logic clk, clr_n,
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//control slave
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input logic [31:0] wr_data,
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input logic wr_n,
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output logic fout
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);
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phacc phacc_inst (.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
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defparam phacc_inst.WIDTH = PHACC_WIDTH;
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sinelut sinelut_inst (
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.address (phase), .clock (clk), .q(sine)
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);
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endmodule
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