82 lines
1.9 KiB
Systemverilog
82 lines
1.9 KiB
Systemverilog
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`timescale 1 ns/1 ns
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module sigdel_tb();
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// Parameters
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localparam CLK_PRD = 20;
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localparam SAMPLES_PRD = 256;
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localparam OVERSAMPLING = 4;
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localparam PHACC_WIDTH = 14;
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// Wires and variables to connect to UUT (unit under test)
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logic clk, clr_n, wr_n;
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logic [31:0] wr_data;
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logic [31:0] phinc_val;
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logic fout;
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// Instantiate UUT and connect used ports
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sigdel dut(.clk(clk), .clr_n(clr_n), .wr_n(wr_n), .wr_data(wr_data), .fout(fout));
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defparam dut.PHACC_WIDTH = PHACC_WIDTH;
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// Clock definition
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initial begin
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clk = 0;
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forever #(CLK_PRD/2) clk = ~clk;
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end
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// Reset and initial values definition
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initial begin
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clr_n = 0;
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wr_n = 1;
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wr_data = 'bx;
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#(CLK_PRD*5) clr_n = 1;
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end
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// Bus write transaction simulation
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initial begin
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// Wait until system is out of reset
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@(posedge clr_n);
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// Check if phase increment for required accumulator width
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// and oversamlpling ratio will fit in 8 bits
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phinc_val=(2**(PHACC_WIDTH-8))/OVERSAMPLING;
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if ((phinc_val <= 255) && (phinc_val != 0))
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begin
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// Write phase increment several clock cycles after reset
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#(CLK_PRD*3) write_transaction(phinc_val);
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// Wait for one sine period (for 14-bit phase accumulator case)
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#(CLK_PRD*SAMPLES_PRD*OVERSAMPLING)
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#(CLK_PRD*3) write_transaction(phinc_val*5);
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#(CLK_PRD*SAMPLES_PRD*OVERSAMPLING)
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$stop;
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end
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else
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begin
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//Output simulation error
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$display("Error: value of phase increment is out of range! Stopped simulation.");
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//Stop simulation (small delay needed for $display to work)
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#1 $stop;
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end
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end
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//Single write transaction task
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task write_transaction;
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//input signals
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input [31:0] val;
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//transaction implementation
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begin
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@(posedge clk);
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//assert signals for one clock cycle
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wr_n = 0;
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wr_data = val;
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@(posedge clk);
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//deassert signals
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wr_n = 1;
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wr_data = 'bx;
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end
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endtask
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endmodule
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