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pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>datasheet for niosII</title>
<style type="text/css">
body { font-family:arial ;}
a { text-decoration:underline ; color:#003000 ;}
a:hover { text-decoration:underline ; color:0030f0 ;}
td { padding : 5px ;}
table.topTitle { width:100% ;}
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
table.blueBar { width : 100% ; border-spacing : 0px ;}
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
table.blueBar td.l { text-align : left ;}
table.blueBar td.r { text-align : right ;}
table.items { width:100% ; border-collapse:collapse ;}
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
table.grid { border-collapse:collapse ;}
table.grid td { border:1px solid #bbb ; font-size:12px ;}
body { font-family:arial ;}
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
table.x td { border:1px solid #bbb ;}
td.tableTitle { font-weight:bold ; text-align:center ;}
table.grid { border-collapse:collapse ;}
table.grid td { border:1px solid #bbb ;}
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
.flowbox { display:inline-block ;}
.parametersbox table { font-size:10px ;}
td.parametername { font-style:italic ;}
td.parametervalue { font-weight:bold ;}
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
</head>
<body>
<table class="topTitle">
<tr>
<td class="l">niosII</td>
<td class="r">
<br/>
<br/>
</td>
</tr>
</table>
<table class="blueBar">
<tr>
done lr4, programmed hardware
2023-02-07 16:10:37 +03:00
<td class="l">2023.02.07.17:03:00</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<td class="r">Datasheet</td>
</tr>
</table>
<div style="width:100% ; height:10px"> </div>
<div class="label">Overview</div>
<div class="greydiv">
<div style="display:inline-block ; text-align:left">
<table class="connectionboxes">
<tr>
<td class="lefthandwire">&#160;&#160;clk&#160;</td>
<td class="main" rowspan="2">niosII</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
</table>
</div><span style="display:inline-block ; width:28px"> </span>
<div style="display:inline-block ; text-align:left"><span>Processor
<br/>&#160;&#160;
<a href="#module_cpu"><b>cpu</b>
</a> Nios II 18.1
<br/>All Components
<br/>&#160;&#160;
<a href="#module_cpu"><b>cpu</b>
</a> altera_nios2_gen2 18.1
<br/>&#160;&#160;
<a href="#module_jtag_uart"><b>jtag_uart</b>
</a> altera_avalon_jtag_uart 18.1
<br/>&#160;&#160;
<a href="#module_mem"><b>mem</b>
</a> altera_avalon_onchip_memory2 18.1
<br/>&#160;&#160;
wip lab4, nios connected, ready to program
2023-01-27 18:04:01 +03:00
<a href="#module_sigdel_0"><b>sigdel_0</b>
</a> sigdel 1.0
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<br/>&#160;&#160;
<a href="#module_sys_clk_timer"><b>sys_clk_timer</b>
</a> altera_avalon_timer 18.1</span>
</div>
</div>
<div style="width:100% ; height:10px"> </div>
<div class="label">Memory Map</div>
<table class="mmap">
<tr>
<td class="empty" rowspan="2"></td>
<td class="mastermodule" colspan="2">
<a href="#module_cpu"><b>cpu</b>
</a>
</td>
</tr>
<tr>
<td class="masterl">&#160;data_master</td>
<td class="masterr">&#160;instruction_master</td>
</tr>
<tr>
<td class="slavemodule">&#160;
<a href="#module_cpu"><b>cpu</b>
</a>
</td>
<td class="empty"></td>
<td class="empty"></td>
</tr>
<tr>
<td class="slaveb">debug_mem_slave&#160;</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="addr"><span style="color:#989898">0x</span>00008800</td>
<td class="addr"><span style="color:#989898">0x</span>00008800</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="slavemodule">&#160;
<a href="#module_jtag_uart"><b>jtag_uart</b>
</a>
</td>
<td class="empty"></td>
<td class="empty"></td>
</tr>
<tr>
<td class="slaveb">avalon_jtag_slave&#160;</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="addr"><span style="color:#989898">0x</span>00009020</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<td class="empty"></td>
</tr>
<tr>
<td class="slavemodule">&#160;
<a href="#module_mem"><b>mem</b>
</a>
</td>
<td class="empty"></td>
<td class="empty"></td>
</tr>
<tr>
<td class="slavem">s1&#160;</td>
<td class="empty"></td>
<td class="addr"><span style="color:#989898">0x</span>00000000</td>
</tr>
<tr>
<td class="slavem">s2&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00000000</td>
<td class="empty"></td>
</tr>
<tr>
<td class="slavemodule">&#160;
wip lab4, nios connected, ready to program
2023-01-27 18:04:01 +03:00
<a href="#module_sigdel_0"><b>sigdel_0</b>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</a>
</td>
<td class="empty"></td>
<td class="empty"></td>
</tr>
<tr>
wip lab4, nios connected, ready to program
2023-01-27 18:04:01 +03:00
<td class="slaveb">avalon_slave&#160;</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="addr"><span style="color:#989898">0x</span>00009028</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<td class="empty"></td>
</tr>
<tr>
<td class="slavemodule">&#160;
<a href="#module_sys_clk_timer"><b>sys_clk_timer</b>
</a>
</td>
<td class="empty"></td>
<td class="empty"></td>
</tr>
<tr>
<td class="slaveb">s1&#160;</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="addr"><span style="color:#989898">0x</span>00009000</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<td class="empty"></td>
</tr>
</table>
<a name="module_clk"> </a>
<div>
<hr/>
<h2>clk</h2>clock_source v18.1
<br/>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">clockFrequency</td>
<td class="parametervalue">50000000</td>
</tr>
<tr>
<td class="parametername">clockFrequencyKnown</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">inputClockFrequency</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">resetSynchronousEdges</td>
<td class="parametervalue">NONE</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>(none)</td>
</tr>
</table>
</div>
<a name="module_cpu"> </a>
<div>
<hr/>
<h2>cpu</h2>altera_nios2_gen2 v18.1
<br/>
<div class="greydiv">
<table class="connectionboxes">
<tr>
<td class="neighbor" rowspan="4">
<a href="#module_clk">clk</a>
</td>
<td class="from">clk&#160;&#160;</td>
wip lab4, nios connected, ready to program
2023-01-27 18:04:01 +03:00
<td class="main" rowspan="29">cpu</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="to">&#160;&#160;clk</td>
</tr>
<tr>
<td class="from">clk_reset&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;reset</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">data_master&#160;&#160;</td>
<td class="neighbor" rowspan="6">
<a href="#module_jtag_uart">jtag_uart</a>
</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;avalon_jtag_slave</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">irq&#160;&#160;</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;irq</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">debug_reset_request&#160;&#160;</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;reset</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">data_master&#160;&#160;</td>
wip lab4, nios connected, ready to program
2023-01-27 18:04:01 +03:00
<td class="neighbor" rowspan="4">
<a href="#module_sigdel_0">sigdel_0</a>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</td>
</tr>
<tr>
<td></td>
<td></td>
wip lab4, nios connected, ready to program
2023-01-27 18:04:01 +03:00
<td class="to">&#160;&#160;avalon_slave</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td></td>
<td></td>
<td class="from">debug_reset_request&#160;&#160;</td>
</tr>
<tr>
<td></td>
<td></td>
wip lab4, nios connected, ready to program
2023-01-27 18:04:01 +03:00
<td class="to">&#160;&#160;reset_sink</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">data_master&#160;&#160;</td>
<td class="neighbor" rowspan="6">
<a href="#module_sys_clk_timer">sys_clk_timer</a>
</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;s1</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">irq&#160;&#160;</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;irq</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">debug_reset_request&#160;&#160;</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;reset</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">data_master&#160;&#160;</td>
<td class="neighbor" rowspan="6">
<a href="#module_mem">mem</a>
</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;s2</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">instruction_master&#160;&#160;</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;s1</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">debug_reset_request&#160;&#160;</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;reset1</td>
</tr>
</table>
</div>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">tmr_enabled</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_disable_tmr_inj</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_showUnpublishedSettings</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_showInternalSettings</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_preciseIllegalMemAccessException</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_exportPCB</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_exportdebuginfo</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_clearXBitsLDNonBypass</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_bigEndian</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_export_large_RAMs</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_asic_enabled</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">register_file_por</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_asic_synopsys_translate_on_off</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_asic_third_party_synthesis</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_asic_add_scan_mode_input</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_oci_version</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">setting_fast_register_read</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_exportHostDebugPort</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_oci_export_jtag_signals</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_avalonDebugPortPresent</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_alwaysEncrypt</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">io_regionbase</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">io_regionsize</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">setting_support31bitdcachebypass</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_activateTrace</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_allow_break_inst</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_activateTestEndChecker</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_ecc_sim_test_ports</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_disableocitrace</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_activateMonitors</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_HDLSimCachesCleared</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_HBreakTest</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_breakslaveoveride</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">mpu_useLimit</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">mpu_enabled</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">mmu_enabled</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">mmu_autoAssignTlbPtrSz</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">cpuReset</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">resetrequest_enabled</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_removeRAMinit</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_tmr_output_disable</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_shadowRegisterSets</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">mpu_numOfInstRegion</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">mpu_numOfDataRegion</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">mmu_TLBMissExcOffset</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">resetOffset</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">exceptionOffset</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">cpuID</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">breakOffset</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">userDefinedSettings</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">tracefilename</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">resetSlave</td>
<td class="parametervalue">mem.s1</td>
</tr>
<tr>
<td class="parametername">mmu_TLBMissExcSlave</td>
<td class="parametervalue">None</td>
</tr>
<tr>
<td class="parametername">exceptionSlave</td>
<td class="parametervalue">mem.s1</td>
</tr>
<tr>
<td class="parametername">breakSlave</td>
<td class="parametervalue">None</td>
</tr>
<tr>
<td class="parametername">setting_interruptControllerType</td>
<td class="parametervalue">Internal</td>
</tr>
<tr>
<td class="parametername">setting_branchpredictiontype</td>
<td class="parametervalue">Dynamic</td>
</tr>
<tr>
<td class="parametername">setting_bhtPtrSz</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">cpuArchRev</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">stratix_dspblock_shift_mul</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">shifterType</td>
<td class="parametervalue">medium_le_shift</td>
</tr>
<tr>
<td class="parametername">multiplierType</td>
<td class="parametervalue">no_mul</td>
</tr>
<tr>
<td class="parametername">mul_shift_choice</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">mul_32_impl</td>
<td class="parametervalue">2</td>
</tr>
<tr>
<td class="parametername">mul_64_impl</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">shift_rot_impl</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">dividerType</td>
<td class="parametervalue">no_div</td>
</tr>
<tr>
<td class="parametername">mpu_minInstRegionSize</td>
<td class="parametervalue">12</td>
</tr>
<tr>
<td class="parametername">mpu_minDataRegionSize</td>
<td class="parametervalue">12</td>
</tr>
<tr>
<td class="parametername">mmu_uitlbNumEntries</td>
<td class="parametervalue">4</td>
</tr>
<tr>
<td class="parametername">mmu_udtlbNumEntries</td>
<td class="parametervalue">6</td>
</tr>
<tr>
<td class="parametername">mmu_tlbPtrSz</td>
<td class="parametervalue">7</td>
</tr>
<tr>
<td class="parametername">mmu_tlbNumWays</td>
<td class="parametervalue">16</td>
</tr>
<tr>
<td class="parametername">mmu_processIDNumBits</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">impl</td>
<td class="parametervalue">Tiny</td>
</tr>
<tr>
<td class="parametername">icache_size</td>
<td class="parametervalue">4096</td>
</tr>
<tr>
<td class="parametername">fa_cache_line</td>
<td class="parametervalue">2</td>
</tr>
<tr>
<td class="parametername">fa_cache_linesize</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">icache_tagramBlockType</td>
<td class="parametervalue">Automatic</td>
</tr>
<tr>
<td class="parametername">icache_ramBlockType</td>
<td class="parametervalue">Automatic</td>
</tr>
<tr>
<td class="parametername">icache_numTCIM</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">icache_burstType</td>
<td class="parametervalue">None</td>
</tr>
<tr>
<td class="parametername">dcache_bursts</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">dcache_victim_buf_impl</td>
<td class="parametervalue">ram</td>
</tr>
<tr>
<td class="parametername">dcache_size</td>
<td class="parametervalue">2048</td>
</tr>
<tr>
<td class="parametername">dcache_tagramBlockType</td>
<td class="parametervalue">Automatic</td>
</tr>
<tr>
<td class="parametername">dcache_ramBlockType</td>
<td class="parametervalue">Automatic</td>
</tr>
<tr>
<td class="parametername">dcache_numTCDM</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">setting_exportvectors</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_usedesignware</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_ecc_present</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_ic_ecc_present</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_rf_ecc_present</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_mmu_ecc_present</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_dc_ecc_present</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_itcm_ecc_present</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">setting_dtcm_ecc_present</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">regfile_ramBlockType</td>
<td class="parametervalue">Automatic</td>
</tr>
<tr>
<td class="parametername">ocimem_ramBlockType</td>
<td class="parametervalue">Automatic</td>
</tr>
<tr>
<td class="parametername">ocimem_ramInit</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">mmu_ramBlockType</td>
<td class="parametervalue">Automatic</td>
</tr>
<tr>
<td class="parametername">bht_ramBlockType</td>
<td class="parametervalue">Automatic</td>
</tr>
<tr>
<td class="parametername">cdx_enabled</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">mpx_enabled</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">debug_enabled</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">debug_triggerArming</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">debug_debugReqSignals</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">debug_assignJtagInstanceID</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">debug_jtagInstanceID</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">debug_OCIOnchipTrace</td>
<td class="parametervalue">_128</td>
</tr>
<tr>
<td class="parametername">debug_hwbreakpoint</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">debug_datatrigger</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">debug_traceType</td>
<td class="parametervalue">none</td>
</tr>
<tr>
<td class="parametername">debug_traceStorage</td>
<td class="parametervalue">onchip_trace</td>
</tr>
<tr>
<td class="parametername">master_addr_map</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">instruction_master_paddr_base</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">instruction_master_paddr_size</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">flash_instruction_master_paddr_base</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">flash_instruction_master_paddr_size</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">data_master_paddr_base</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">data_master_paddr_size</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_instruction_master_0_paddr_base</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_instruction_master_0_paddr_size</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_instruction_master_1_paddr_base</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_instruction_master_1_paddr_size</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_instruction_master_2_paddr_base</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_instruction_master_2_paddr_size</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_instruction_master_3_paddr_base</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_instruction_master_3_paddr_size</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_data_master_0_paddr_base</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_data_master_0_paddr_size</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_data_master_1_paddr_base</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_data_master_1_paddr_size</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_data_master_2_paddr_base</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_data_master_2_paddr_size</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_data_master_3_paddr_base</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">tightly_coupled_data_master_3_paddr_size</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">instruction_master_high_performance_paddr_base</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">instruction_master_high_performance_paddr_size</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">data_master_high_performance_paddr_base</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">data_master_high_performance_paddr_size</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">resetAbsoluteAddr</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">exceptionAbsoluteAddr</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">breakAbsoluteAddr</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="parametervalue">34848</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="parametername">mmu_TLBMissExcAbsAddr</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">dcache_bursts_derived</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">dcache_size_derived</td>
<td class="parametervalue">2048</td>
</tr>
<tr>
<td class="parametername">breakSlave_derived</td>
<td class="parametervalue">cpu.debug_mem_slave</td>
</tr>
<tr>
<td class="parametername">dcache_lineSize_derived</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">setting_ioregionBypassDCache</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">setting_bit31BypassDCache</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">translate_on</td>
<td class="parametervalue"> "synthesis translate_on" </td>
</tr>
<tr>
<td class="parametername">translate_off</td>
<td class="parametervalue"> "synthesis translate_off" </td>
</tr>
<tr>
<td class="parametername">debug_onchiptrace</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">debug_offchiptrace</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">debug_insttrace</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">debug_datatrace</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">instAddrWidth</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="parametervalue">16</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="parametername">faAddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">dataAddrWidth</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="parametervalue">16</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster0AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster1AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster2AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster3AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster0AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster1AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster2AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster3AddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">dataMasterHighPerformanceAddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">instructionMasterHighPerformanceAddrWidth</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">instSlaveMapParam</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s1' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s1' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;/address-map&gt;</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="parametername">faSlaveMapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">dataSlaveMapParam</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x9000' end='0x9020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x9020' end='0x9028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;slave name='sigdel_0.avalon_slave' start='0x9028' end='0x902C' type='sigdel.avalon_slave' /&gt;&lt;/address-map&gt;</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster1MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster2MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster3MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster0MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster1MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster2MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">tightlyCoupledInstructionMaster3MapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">dataMasterHighPerformanceMapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">instructionMasterHighPerformanceMapParam</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">clockFrequency</td>
<td class="parametervalue">50000000</td>
</tr>
<tr>
<td class="parametername">deviceFamilyName</td>
<td class="parametervalue">CYCLONEIVE</td>
</tr>
<tr>
<td class="parametername">internalIrqMaskSystemInfo</td>
<td class="parametervalue">3</td>
</tr>
<tr>
<td class="parametername">customInstSlavesSystemInfo</td>
<td class="parametervalue">&lt;info/&gt;</td>
</tr>
<tr>
<td class="parametername">customInstSlavesSystemInfo_nios_a</td>
<td class="parametervalue">&lt;info/&gt;</td>
</tr>
<tr>
<td class="parametername">customInstSlavesSystemInfo_nios_b</td>
<td class="parametervalue">&lt;info/&gt;</td>
</tr>
<tr>
<td class="parametername">customInstSlavesSystemInfo_nios_c</td>
<td class="parametervalue">&lt;info/&gt;</td>
</tr>
<tr>
<td class="parametername">deviceFeaturesSystemInfo</td>
<td class="parametervalue">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPOR
</tr>
<tr>
<td class="parametername">AUTO_DEVICE</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="parametervalue">EP4CE15F23C8</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="parametername">AUTO_DEVICE_SPEEDGRADE</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="parametervalue">8</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="parametername">AUTO_CLK_CLOCK_DOMAIN</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">AUTO_CLK_RESET_DOMAIN</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>
<table>
<tr>
<td class="parametername">BIG_ENDIAN</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">BREAK_ADDR</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="parametervalue">0x00008820</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="parametername">CPU_ARCH_NIOS2_R1</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">CPU_FREQ</td>
<td class="parametervalue">50000000u</td>
</tr>
<tr>
<td class="parametername">CPU_ID_SIZE</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">CPU_ID_VALUE</td>
<td class="parametervalue">0x00000000</td>
</tr>
<tr>
<td class="parametername">CPU_IMPLEMENTATION</td>
<td class="parametervalue">"tiny"</td>
</tr>
<tr>
<td class="parametername">DATA_ADDR_WIDTH</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="parametervalue">16</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="parametername">DCACHE_LINE_SIZE</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">DCACHE_LINE_SIZE_LOG2</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">DCACHE_SIZE</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">EXCEPTION_ADDR</td>
<td class="parametervalue">0x00000020</td>
</tr>
<tr>
<td class="parametername">FLASH_ACCELERATOR_LINES</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">FLASH_ACCELERATOR_LINE_SIZE</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">FLUSHDA_SUPPORTED</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">HARDWARE_DIVIDE_PRESENT</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">HARDWARE_MULTIPLY_PRESENT</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">HARDWARE_MULX_PRESENT</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">HAS_DEBUG_CORE</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">HAS_DEBUG_STUB</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">HAS_ILLEGAL_INSTRUCTION_EXCEPTION</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">HAS_JMPI_INSTRUCTION</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">ICACHE_LINE_SIZE</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">ICACHE_LINE_SIZE_LOG2</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">ICACHE_SIZE</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">INST_ADDR_WIDTH</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="parametervalue">16</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="parametername">OCI_VERSION</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">RESET_ADDR</td>
<td class="parametervalue">0x00000000</td>
</tr>
</table>
</td>
</tr>
</table>
</div>
<a name="module_jtag_uart"> </a>
<div>
<hr/>
<h2>jtag_uart</h2>altera_avalon_jtag_uart v18.1
<br/>
<div class="greydiv">
<table class="connectionboxes">
<tr>
<td class="neighbor" rowspan="6">
<a href="#module_cpu">cpu</a>
</td>
<td class="from">data_master&#160;&#160;</td>
<td class="main" rowspan="11">jtag_uart</td>
</tr>
<tr>
<td class="to">&#160;&#160;avalon_jtag_slave</td>
</tr>
<tr>
<td class="from">irq&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;irq</td>
</tr>
<tr>
<td class="from">debug_reset_request&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;reset</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr>
<td class="neighbor" rowspan="4">
<a href="#module_clk">clk</a>
</td>
<td class="from">clk&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;clk</td>
</tr>
<tr>
<td class="from">clk_reset&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;reset</td>
</tr>
</table>
</div>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">allowMultipleConnections</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">hubInstanceID</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">readBufferDepth</td>
<td class="parametervalue">64</td>
</tr>
<tr>
<td class="parametername">readIRQThreshold</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">simInputCharacterStream</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">simInteractiveOptions</td>
<td class="parametervalue">NO_INTERACTIVE_WINDOWS</td>
</tr>
<tr>
<td class="parametername">useRegistersForReadBuffer</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">useRegistersForWriteBuffer</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">useRelativePathForSimFile</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">writeBufferDepth</td>
<td class="parametervalue">64</td>
</tr>
<tr>
<td class="parametername">writeIRQThreshold</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">clkFreq</td>
<td class="parametervalue">50000000</td>
</tr>
<tr>
<td class="parametername">avalonSpec</td>
<td class="parametervalue">2.0</td>
</tr>
<tr>
<td class="parametername">legacySignalAllow</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">enableInteractiveInput</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">enableInteractiveOutput</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>
<table>
<tr>
<td class="parametername">READ_DEPTH</td>
<td class="parametervalue">64</td>
</tr>
<tr>
<td class="parametername">READ_THRESHOLD</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">WRITE_DEPTH</td>
<td class="parametervalue">64</td>
</tr>
<tr>
<td class="parametername">WRITE_THRESHOLD</td>
<td class="parametervalue">8</td>
</tr>
</table>
</td>
</tr>
</table>
</div>
<a name="module_mem"> </a>
<div>
<hr/>
<h2>mem</h2>altera_avalon_onchip_memory2 v18.1
<br/>
<div class="greydiv">
<table class="connectionboxes">
<tr>
<td class="neighbor" rowspan="6">
<a href="#module_cpu">cpu</a>
</td>
<td class="from">data_master&#160;&#160;</td>
<td class="main" rowspan="11">mem</td>
</tr>
<tr>
<td class="to">&#160;&#160;s2</td>
</tr>
<tr>
<td class="from">instruction_master&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;s1</td>
</tr>
<tr>
<td class="from">debug_reset_request&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;reset1</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr>
<td class="neighbor" rowspan="4">
<a href="#module_clk">clk</a>
</td>
<td class="from">clk&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;clk1</td>
</tr>
<tr>
<td class="from">clk_reset&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;reset1</td>
</tr>
</table>
</div>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">allowInSystemMemoryContentEditor</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">blockType</td>
<td class="parametervalue">AUTO</td>
</tr>
<tr>
<td class="parametername">dataWidth</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">dataWidth2</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">dualPort</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">enableDiffWidth</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">derived_enableDiffWidth</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">initMemContent</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">initializationFileName</td>
<td class="parametervalue">onchip_mem.hex</td>
</tr>
<tr>
<td class="parametername">enPRInitMode</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">instanceID</td>
<td class="parametervalue">NONE</td>
</tr>
<tr>
<td class="parametername">memorySize</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="parametervalue">32768</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="parametername">readDuringWriteMode</td>
<td class="parametervalue">DONT_CARE</td>
</tr>
<tr>
<td class="parametername">simAllowMRAMContentsFile</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">simMemInitOnlyFilename</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">singleClockOperation</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">derived_singleClockOperation</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">slave1Latency</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">slave2Latency</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">useNonDefaultInitFile</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">copyInitFile</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">useShallowMemBlocks</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">writable</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">ecc_enabled</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">resetrequest_enabled</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">autoInitializationFileName</td>
<td class="parametervalue">niosII_mem</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">CYCLONEIVE</td>
</tr>
<tr>
<td class="parametername">deviceFeatures</td>
<td class="parametervalue">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPOR
</tr>
<tr>
<td class="parametername">derived_set_addr_width</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="parametervalue">13</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="parametername">derived_set_addr_width2</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="parametervalue">13</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="parametername">derived_set_data_width</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">derived_set_data_width2</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">derived_gui_ram_block_type</td>
<td class="parametervalue">Automatic</td>
</tr>
<tr>
<td class="parametername">derived_is_hardcopy</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">derived_init_file_name</td>
<td class="parametervalue">niosII_mem.hex</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>
<table>
<tr>
<td class="parametername">ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">CONTENTS_INFO</td>
<td class="parametervalue">""</td>
</tr>
<tr>
<td class="parametername">DUAL_PORT</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">GUI_RAM_BLOCK_TYPE</td>
<td class="parametervalue">AUTO</td>
</tr>
<tr>
<td class="parametername">INIT_CONTENTS_FILE</td>
<td class="parametervalue">niosII_mem</td>
</tr>
<tr>
<td class="parametername">INIT_MEM_CONTENT</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">INSTANCE_ID</td>
<td class="parametervalue">NONE</td>
</tr>
<tr>
<td class="parametername">NON_DEFAULT_INIT_FILE_ENABLED</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">RAM_BLOCK_TYPE</td>
<td class="parametervalue">AUTO</td>
</tr>
<tr>
<td class="parametername">READ_DURING_WRITE_MODE</td>
<td class="parametervalue">DONT_CARE</td>
</tr>
<tr>
<td class="parametername">SINGLE_CLOCK_OP</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">SIZE_MULTIPLE</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">SIZE_VALUE</td>
work board parameters
2023-02-07 13:31:34 +03:00
<td class="parametervalue">32768</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="parametername">WRITABLE</td>
<td class="parametervalue">1</td>
</tr>
</table>
</td>
</tr>
</table>
</div>
wip lab4, nios connected, ready to program
2023-01-27 18:04:01 +03:00
<a name="module_sigdel_0"> </a>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<div>
<hr/>
wip lab4, nios connected, ready to program
2023-01-27 18:04:01 +03:00
<h2>sigdel_0</h2>sigdel v1.0
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<br/>
<div class="greydiv">
<table class="connectionboxes">
<tr>
wip lab4, nios connected, ready to program
2023-01-27 18:04:01 +03:00
<td class="neighbor" rowspan="4">
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<a href="#module_cpu">cpu</a>
</td>
<td class="from">data_master&#160;&#160;</td>
wip lab4, nios connected, ready to program
2023-01-27 18:04:01 +03:00
<td class="main" rowspan="9">sigdel_0</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
wip lab4, nios connected, ready to program
2023-01-27 18:04:01 +03:00
<td class="to">&#160;&#160;avalon_slave</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="from">debug_reset_request&#160;&#160;</td>
</tr>
<tr>
wip lab4, nios connected, ready to program
2023-01-27 18:04:01 +03:00
<td class="to">&#160;&#160;reset_sink</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr>
<td class="neighbor" rowspan="4">
<a href="#module_clk">clk</a>
</td>
<td class="from">clk&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;clock</td>
</tr>
<tr>
<td class="from">clk_reset&#160;&#160;</td>
</tr>
<tr>
wip lab4, nios connected, ready to program
2023-01-27 18:04:01 +03:00
<td class="to">&#160;&#160;reset_sink</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
</table>
</div>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
wip lab4, nios connected, ready to program
2023-01-27 18:04:01 +03:00
<td class="parametername">PHACC_WIDTH</td>
done lr4, programmed hardware
2023-02-07 16:10:37 +03:00
<td class="parametervalue">26</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>(none)</td>
</tr>
</table>
</div>
<a name="module_sys_clk_timer"> </a>
<div>
<hr/>
<h2>sys_clk_timer</h2>altera_avalon_timer v18.1
<br/>
<div class="greydiv">
<table class="connectionboxes">
<tr>
<td class="neighbor" rowspan="6">
<a href="#module_cpu">cpu</a>
</td>
<td class="from">data_master&#160;&#160;</td>
<td class="main" rowspan="11">sys_clk_timer</td>
</tr>
<tr>
<td class="to">&#160;&#160;s1</td>
</tr>
<tr>
<td class="from">irq&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;irq</td>
</tr>
<tr>
<td class="from">debug_reset_request&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;reset</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr>
<td class="neighbor" rowspan="4">
<a href="#module_clk">clk</a>
</td>
<td class="from">clk&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;clk</td>
</tr>
<tr>
<td class="from">clk_reset&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;reset</td>
</tr>
</table>
</div>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">alwaysRun</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">counterSize</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">fixedPeriod</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">period</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">periodUnits</td>
<td class="parametervalue">MSEC</td>
</tr>
<tr>
<td class="parametername">resetOutput</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">snapshot</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">timeoutPulseOutput</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">systemFrequency</td>
<td class="parametervalue">50000000</td>
</tr>
<tr>
<td class="parametername">watchdogPulse</td>
<td class="parametervalue">2</td>
</tr>
<tr>
<td class="parametername">timerPreset</td>
<td class="parametervalue">FULL_FEATURED</td>
</tr>
<tr>
<td class="parametername">periodUnitsString</td>
<td class="parametervalue">ms</td>
</tr>
<tr>
<td class="parametername">valueInSecond</td>
<td class="parametervalue">0.001</td>
</tr>
<tr>
<td class="parametername">loadValue</td>
<td class="parametervalue">49999</td>
</tr>
<tr>
<td class="parametername">mult</td>
<td class="parametervalue">0.001</td>
</tr>
<tr>
<td class="parametername">ticksPerSec</td>
<td class="parametervalue">1000.0</td>
</tr>
<tr>
<td class="parametername">slave_address_width</td>
<td class="parametervalue">3</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>
<table>
<tr>
<td class="parametername">ALWAYS_RUN</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">COUNTER_SIZE</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">FIXED_PERIOD</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">FREQ</td>
<td class="parametervalue">50000000</td>
</tr>
<tr>
<td class="parametername">LOAD_VALUE</td>
<td class="parametervalue">49999</td>
</tr>
<tr>
<td class="parametername">MULT</td>
<td class="parametervalue">0.001</td>
</tr>
<tr>
<td class="parametername">PERIOD</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">PERIOD_UNITS</td>
<td class="parametervalue">ms</td>
</tr>
<tr>
<td class="parametername">RESET_OUTPUT</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">SNAPSHOT</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">TICKS_PER_SEC</td>
<td class="parametervalue">1000</td>
</tr>
<tr>
<td class="parametername">TIMEOUT_PULSE_OUTPUT</td>
<td class="parametervalue">0</td>
</tr>
</table>
</td>
</tr>
</table>
</div>
<table class="blueBar">
<tr>
reported lr2 + individual
2023-01-18 16:45:45 +03:00
<td class="l">generation took 0.00 seconds</td>
done lr4, programmed hardware
2023-02-07 16:10:37 +03:00
<td class="r">rendering took 0.03 seconds</td>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</tr>
</table>
</body>
</html>