wip lab4, nios connected, ready to program
This commit is contained in:
parent
22f16bc090
commit
dad79c26fb
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@ -17,7 +17,7 @@ always_ff @(posedge clk, negedge reset) begin
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end
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end
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assign daco = (un >= $signed(8'd0)) ? 1'd1 : 1'd0;
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assign out = (un >= $signed(8'd0)) ? 1'd1 : 1'd0;
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assign eps = (un >= $signed(8'd0)) ? $signed(8'd126) - un : $signed(-8'd126) - un;
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assign daco = out;
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endmodule
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Binary file not shown.
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@ -1,151 +0,0 @@
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# system info niosII_tb on 2022.10.24.18:26:01
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system_info:
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name,value
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DEVICE,EP4CE115F29C7
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DEVICE_FAMILY,Cyclone IV E
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GENERATION_ID,1666621532
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#
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#
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# Files generated for niosII_tb on 2022.10.24.18:26:01
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files:
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filepath,kind,attributes,module,is_top
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niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
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niosII/testbench/niosII_tb/simulation/submodules/niosII.v,VERILOG,,niosII,false
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niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_clock_source,false
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niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv,SYSTEM_VERILOG,,altera_avalon_clock_source,false
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niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_reset_source,false
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niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv,SYSTEM_VERILOG,,altera_avalon_reset_source,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v,VERILOG,,niosII_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false
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niosII/testbench/niosII_tb/simulation/submodules/dec.sv,SYSTEM_VERILOG,,dec,false
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niosII/testbench/niosII_tb/simulation/submodules/periodram.v,VERILOG,,dec,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v,VERILOG,,niosII_sys_clk_timer,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v,VERILOG,,niosII_mm_interconnect_0,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VERILOG,,niosII_irq_mapper,false
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niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
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niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
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niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false
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niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
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niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
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niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false
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niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
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niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
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niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v,VERILOG,,altera_avalon_sc_fifo,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_001,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_002,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_004,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_008,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux_001,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
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niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
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niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_demux,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
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niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
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niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v,VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter,false
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niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0,false
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#
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# Map from instance-path to kind of module
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instances:
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instancePath,module
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niosII_tb.niosII_inst,niosII
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niosII_tb.niosII_inst.cpu,niosII_cpu
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niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu
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niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart
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niosII_tb.niosII_inst.mem,niosII_mem
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niosII_tb.niosII_inst.sem,dec
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niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer
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niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0
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niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_translator,altera_merlin_master_translator
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niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_translator,altera_merlin_master_translator
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niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_translator,altera_merlin_slave_translator
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niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_translator,altera_merlin_slave_translator
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niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_translator,altera_merlin_slave_translator
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niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_translator,altera_merlin_slave_translator
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niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_translator,altera_merlin_slave_translator
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niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_translator,altera_merlin_slave_translator
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niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_translator,altera_merlin_slave_translator
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niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_agent,altera_merlin_master_agent
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niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_agent,altera_merlin_master_agent
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niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent,altera_merlin_slave_agent
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niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent,altera_merlin_slave_agent
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niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent,altera_merlin_slave_agent
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niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent,altera_merlin_slave_agent
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niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent,altera_merlin_slave_agent
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niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent,altera_merlin_slave_agent
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niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent,altera_merlin_slave_agent
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niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent_rsp_fifo,altera_avalon_sc_fifo
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niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent_rsp_fifo,altera_avalon_sc_fifo
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niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent_rsp_fifo,altera_avalon_sc_fifo
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niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent_rsp_fifo,altera_avalon_sc_fifo
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niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent_rsp_fifo,altera_avalon_sc_fifo
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niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent_rsp_fifo,altera_avalon_sc_fifo
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niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent_rsp_fifo,altera_avalon_sc_fifo
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niosII_tb.niosII_inst.mm_interconnect_0.router,niosII_mm_interconnect_0_router
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niosII_tb.niosII_inst.mm_interconnect_0.router_001,niosII_mm_interconnect_0_router_001
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niosII_tb.niosII_inst.mm_interconnect_0.router_002,niosII_mm_interconnect_0_router_002
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niosII_tb.niosII_inst.mm_interconnect_0.router_003,niosII_mm_interconnect_0_router_002
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niosII_tb.niosII_inst.mm_interconnect_0.router_005,niosII_mm_interconnect_0_router_002
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niosII_tb.niosII_inst.mm_interconnect_0.router_006,niosII_mm_interconnect_0_router_002
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niosII_tb.niosII_inst.mm_interconnect_0.router_007,niosII_mm_interconnect_0_router_002
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niosII_tb.niosII_inst.mm_interconnect_0.router_004,niosII_mm_interconnect_0_router_004
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niosII_tb.niosII_inst.mm_interconnect_0.router_008,niosII_mm_interconnect_0_router_008
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niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux,niosII_mm_interconnect_0_cmd_demux
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niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux_001,niosII_mm_interconnect_0_cmd_demux_001
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niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_002,niosII_mm_interconnect_0_cmd_demux_001
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niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux,niosII_mm_interconnect_0_cmd_mux
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niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_001,niosII_mm_interconnect_0_cmd_mux
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niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_003,niosII_mm_interconnect_0_cmd_mux
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niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_004,niosII_mm_interconnect_0_cmd_mux
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niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_005,niosII_mm_interconnect_0_cmd_mux
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niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_006,niosII_mm_interconnect_0_cmd_mux
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niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_002,niosII_mm_interconnect_0_cmd_mux_002
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niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux,niosII_mm_interconnect_0_rsp_demux
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niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_001,niosII_mm_interconnect_0_rsp_demux
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niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_003,niosII_mm_interconnect_0_rsp_demux
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niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_004,niosII_mm_interconnect_0_rsp_demux
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niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_005,niosII_mm_interconnect_0_rsp_demux
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niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_006,niosII_mm_interconnect_0_rsp_demux
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niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux,niosII_mm_interconnect_0_rsp_mux
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niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux_001,niosII_mm_interconnect_0_rsp_mux_001
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niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter,niosII_mm_interconnect_0_avalon_st_adapter
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niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
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niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001,niosII_mm_interconnect_0_avalon_st_adapter
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niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
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niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002,niosII_mm_interconnect_0_avalon_st_adapter
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niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
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niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003,niosII_mm_interconnect_0_avalon_st_adapter
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niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
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niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004,niosII_mm_interconnect_0_avalon_st_adapter
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niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
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niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005,niosII_mm_interconnect_0_avalon_st_adapter
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niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
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niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006,niosII_mm_interconnect_0_avalon_st_adapter
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niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
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niosII_tb.niosII_inst.irq_mapper,niosII_irq_mapper
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niosII_tb.niosII_inst.rst_controller,altera_reset_controller
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niosII_tb.niosII_inst_clk_bfm,altera_avalon_clock_source
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niosII_tb.niosII_inst_reset_bfm,altera_avalon_reset_source
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@ -45,7 +45,7 @@
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{
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datum baseAddress
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{
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value = "135272";
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value = "135200";
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type = "String";
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}
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}
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@ -105,7 +105,7 @@
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type = "String";
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}
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}
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element sem
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element sigdel_0
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{
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datum _sortIndex
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{
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@ -113,19 +113,11 @@
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type = "int";
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}
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}
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element sem.ctl_slave
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element sigdel_0.avalon_slave
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{
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datum baseAddress
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{
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value = "135264";
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type = "String";
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}
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}
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element sem.ram_slave
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{
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datum baseAddress
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{
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value = "135168";
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value = "135208";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -141,7 +133,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "135232";
|
||||
value = "135168";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -167,8 +159,12 @@
|
|||
<parameter name="useTestBenchNamingPattern" value="false" />
|
||||
<instanceScript></instanceScript>
|
||||
<interface name="clk" internal="clk.clk_in" type="clock" dir="end" />
|
||||
<interface
|
||||
name="conduit_end"
|
||||
internal="sigdel_0.conduit_end"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface name="reset" internal="clk.clk_in_reset" type="reset" dir="end" />
|
||||
<interface name="sem_export" internal="sem.sem" type="conduit" dir="end" />
|
||||
<module name="clk" kind="clock_source" version="18.1" enabled="1">
|
||||
<parameter name="clockFrequency" value="50000000" />
|
||||
<parameter name="clockFrequencyKnown" value="true" />
|
||||
|
|
@ -195,7 +191,7 @@
|
|||
<parameter name="dataAddrWidth" value="18" />
|
||||
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
|
||||
<parameter name="dataMasterHighPerformanceMapParam" value="" />
|
||||
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
|
||||
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21020' end='0x21028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sigdel_0.avalon_slave' start='0x21028' end='0x2102C' type='sigdel.avalon_slave' /></address-map>]]></parameter>
|
||||
<parameter name="data_master_high_performance_paddr_base" value="0" />
|
||||
<parameter name="data_master_high_performance_paddr_size" value="0" />
|
||||
<parameter name="data_master_paddr_base" value="0" />
|
||||
|
|
@ -404,8 +400,8 @@
|
|||
<parameter name="useShallowMemBlocks" value="false" />
|
||||
<parameter name="writable" value="true" />
|
||||
</module>
|
||||
<module name="sem" kind="sem" version="1.1" enabled="1">
|
||||
<parameter name="m" value="32" />
|
||||
<module name="sigdel_0" kind="sigdel" version="1.0" enabled="1">
|
||||
<parameter name="PHACC_WIDTH" value="14" />
|
||||
</module>
|
||||
<module
|
||||
name="sys_clk_timer"
|
||||
|
|
@ -429,16 +425,16 @@
|
|||
start="cpu.data_master"
|
||||
end="jtag_uart.avalon_jtag_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00021068" />
|
||||
<parameter name="baseAddress" value="0x00021020" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="18.1"
|
||||
start="cpu.data_master"
|
||||
end="sem.ctl_slave">
|
||||
end="sigdel_0.avalon_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00021060" />
|
||||
<parameter name="baseAddress" value="0x00021028" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -450,22 +446,13 @@
|
|||
<parameter name="baseAddress" value="0x00020800" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="18.1"
|
||||
start="cpu.data_master"
|
||||
end="sem.ram_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00021000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="18.1"
|
||||
start="cpu.data_master"
|
||||
end="sys_clk_timer.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00021040" />
|
||||
<parameter name="baseAddress" value="0x00021000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection kind="avalon" version="18.1" start="cpu.data_master" end="mem.s2">
|
||||
|
|
@ -495,7 +482,7 @@
|
|||
<connection kind="clock" version="18.1" start="clk.clk" end="jtag_uart.clk" />
|
||||
<connection kind="clock" version="18.1" start="clk.clk" end="sys_clk_timer.clk" />
|
||||
<connection kind="clock" version="18.1" start="clk.clk" end="mem.clk1" />
|
||||
<connection kind="clock" version="18.1" start="clk.clk" end="sem.clock" />
|
||||
<connection kind="clock" version="18.1" start="clk.clk" end="sigdel_0.clock" />
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="18.1"
|
||||
|
|
@ -518,7 +505,11 @@
|
|||
start="clk.clk_reset"
|
||||
end="sys_clk_timer.reset" />
|
||||
<connection kind="reset" version="18.1" start="clk.clk_reset" end="mem.reset1" />
|
||||
<connection kind="reset" version="18.1" start="clk.clk_reset" end="sem.reset_n" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="18.1"
|
||||
start="clk.clk_reset"
|
||||
end="sigdel_0.reset_sink" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="18.1"
|
||||
|
|
@ -543,7 +534,7 @@
|
|||
kind="reset"
|
||||
version="18.1"
|
||||
start="cpu.debug_reset_request"
|
||||
end="sem.reset_n" />
|
||||
end="sigdel_0.reset_sink" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
|
||||
|
|
|
|||
File diff suppressed because one or more lines are too long
|
|
@ -1,94 +1,70 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 288 232)
|
||||
(text "niosII" (rect 130 -1 150 11)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 216 20 228)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
|
||||
(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 112 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
|
||||
(text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 112 112)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 152)
|
||||
(input)
|
||||
(text "sem_export_train" (rect 0 0 70 12)(font "Arial" (font_size 8)))
|
||||
(text "sem_export_train" (rect 4 141 100 152)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 152)(pt 112 152)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 168)
|
||||
(output)
|
||||
(text "sem_export_red" (rect 0 0 67 12)(font "Arial" (font_size 8)))
|
||||
(text "sem_export_red" (rect 4 157 88 168)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 168)(pt 112 168)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 184)
|
||||
(output)
|
||||
(text "sem_export_yellow" (rect 0 0 77 12)(font "Arial" (font_size 8)))
|
||||
(text "sem_export_yellow" (rect 4 173 106 184)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 184)(pt 112 184)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 200)
|
||||
(output)
|
||||
(text "sem_export_green" (rect 0 0 76 12)(font "Arial" (font_size 8)))
|
||||
(text "sem_export_green" (rect 4 189 100 200)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 200)(pt 112 200)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(text "clk" (rect 97 43 212 99)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 117 67 252 144)(font "Arial" (color 0 0 0)))
|
||||
(text "reset" (rect 83 83 196 179)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "reset_n" (rect 117 107 276 224)(font "Arial" (color 0 0 0)))
|
||||
(text "sem_export" (rect 44 123 148 259)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "train" (rect 117 147 264 304)(font "Arial" (color 0 0 0)))
|
||||
(text "red" (rect 117 163 252 336)(font "Arial" (color 0 0 0)))
|
||||
(text "yellow" (rect 117 179 270 368)(font "Arial" (color 0 0 0)))
|
||||
(text "green" (rect 117 195 264 400)(font "Arial" (color 0 0 0)))
|
||||
(text " niosII " (rect 262 216 572 442)(font "Arial" ))
|
||||
(line (pt 112 32)(pt 176 32)(line_width 1))
|
||||
(line (pt 176 32)(pt 176 216)(line_width 1))
|
||||
(line (pt 112 216)(pt 176 216)(line_width 1))
|
||||
(line (pt 112 32)(pt 112 216)(line_width 1))
|
||||
(line (pt 113 52)(pt 113 76)(line_width 1))
|
||||
(line (pt 114 52)(pt 114 76)(line_width 1))
|
||||
(line (pt 113 92)(pt 113 116)(line_width 1))
|
||||
(line (pt 114 92)(pt 114 116)(line_width 1))
|
||||
(line (pt 113 132)(pt 113 204)(line_width 1))
|
||||
(line (pt 114 132)(pt 114 204)(line_width 1))
|
||||
(line (pt 0 0)(pt 288 0)(line_width 1))
|
||||
(line (pt 288 0)(pt 288 232)(line_width 1))
|
||||
(line (pt 0 232)(pt 288 232)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 232)(line_width 1))
|
||||
)
|
||||
)
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 496 184)
|
||||
(text "niosII" (rect 234 -1 254 11)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 168 20 180)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
|
||||
(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 192 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 152)
|
||||
(input)
|
||||
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
|
||||
(text "reset_reset_n" (rect 4 141 82 152)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 152)(pt 192 152)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(output)
|
||||
(text "conduit_end_writeresponsevalid_n" (rect 0 0 135 12)(font "Arial" (font_size 8)))
|
||||
(text "conduit_end_writeresponsevalid_n" (rect 4 101 196 112)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 192 112)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(text "clk" (rect 177 43 372 99)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 197 67 412 144)(font "Arial" (color 0 0 0)))
|
||||
(text "conduit_end" (rect 123 83 312 179)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "writeresponsevalid_n" (rect 197 107 514 224)(font "Arial" (color 0 0 0)))
|
||||
(text "reset" (rect 163 123 356 259)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "reset_n" (rect 197 147 436 304)(font "Arial" (color 0 0 0)))
|
||||
(text " niosII " (rect 470 168 988 346)(font "Arial" ))
|
||||
(line (pt 192 32)(pt 304 32)(line_width 1))
|
||||
(line (pt 304 32)(pt 304 168)(line_width 1))
|
||||
(line (pt 192 168)(pt 304 168)(line_width 1))
|
||||
(line (pt 192 32)(pt 192 168)(line_width 1))
|
||||
(line (pt 193 52)(pt 193 76)(line_width 1))
|
||||
(line (pt 194 52)(pt 194 76)(line_width 1))
|
||||
(line (pt 193 92)(pt 193 116)(line_width 1))
|
||||
(line (pt 194 92)(pt 194 116)(line_width 1))
|
||||
(line (pt 193 132)(pt 193 156)(line_width 1))
|
||||
(line (pt 194 132)(pt 194 156)(line_width 1))
|
||||
(line (pt 0 0)(pt 496 0)(line_width 1))
|
||||
(line (pt 496 0)(pt 496 184)(line_width 1))
|
||||
(line (pt 0 184)(pt 496 184)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 184)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,11 +1,8 @@
|
|||
component niosII is
|
||||
component niosII is
|
||||
port (
|
||||
clk_clk : in std_logic := 'X'; -- clk
|
||||
reset_reset_n : in std_logic := 'X'; -- reset_n
|
||||
sem_export_train : in std_logic := 'X'; -- train
|
||||
sem_export_red : out std_logic; -- red
|
||||
sem_export_yellow : out std_logic; -- yellow
|
||||
sem_export_green : out std_logic -- green
|
||||
clk_clk : in std_logic := 'X'; -- clk
|
||||
conduit_end_writeresponsevalid_n : out std_logic; -- writeresponsevalid_n
|
||||
reset_reset_n : in std_logic := 'X' -- reset_n
|
||||
);
|
||||
end component niosII;
|
||||
|
||||
end component niosII;
|
||||
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2023.01.17.19:00:54</td>
|
||||
<td class="l">2023.01.27.18:49:31</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
|
|
@ -100,8 +100,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<a href="#module_mem"><b>mem</b>
|
||||
</a> altera_avalon_onchip_memory2 18.1
|
||||
<br/>  
|
||||
<a href="#module_sem"><b>sem</b>
|
||||
</a> sem 1.1
|
||||
<a href="#module_sigdel_0"><b>sigdel_0</b>
|
||||
</a> sigdel 1.0
|
||||
<br/>  
|
||||
<a href="#module_sys_clk_timer"><b>sys_clk_timer</b>
|
||||
</a> altera_avalon_timer 18.1</span>
|
||||
|
|
@ -144,7 +144,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="slaveb">avalon_jtag_slave </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021068</td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021020</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
|
|
@ -167,20 +167,15 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="slavemodule"> 
|
||||
<a href="#module_sem"><b>sem</b>
|
||||
<a href="#module_sigdel_0"><b>sigdel_0</b>
|
||||
</a>
|
||||
</td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">ctl_slave </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021060</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">ram_slave </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
|
||||
<td class="slaveb">avalon_slave </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021028</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
|
|
@ -193,7 +188,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="slaveb">s1 </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021040</td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
</table>
|
||||
|
|
@ -256,7 +251,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<a href="#module_clk">clk</a>
|
||||
</td>
|
||||
<td class="from">clk  </td>
|
||||
<td class="main" rowspan="31">cpu</td>
|
||||
<td class="main" rowspan="29">cpu</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  clk</td>
|
||||
|
|
@ -307,24 +302,14 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<td></td>
|
||||
<td></td>
|
||||
<td class="from">data_master  </td>
|
||||
<td class="neighbor" rowspan="6">
|
||||
<a href="#module_sem">sem</a>
|
||||
<td class="neighbor" rowspan="4">
|
||||
<a href="#module_sigdel_0">sigdel_0</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  ctl_slave</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="from">data_master  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  ram_slave</td>
|
||||
<td class="to">  avalon_slave</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
|
|
@ -334,7 +319,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  reset_n</td>
|
||||
<td class="to">  reset_sink</td>
|
||||
</tr>
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
|
|
@ -1107,7 +1092,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">dataSlaveMapParam</td>
|
||||
<td class="parametervalue"><address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map></td>
|
||||
<td class="parametervalue"><address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21020' end='0x21028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sigdel_0.avalon_slave' start='0x21028' end='0x2102C' type='sigdel.avalon_slave' /></address-map></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
|
||||
|
|
@ -1763,34 +1748,28 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_sem"> </a>
|
||||
<a name="module_sigdel_0"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>sem</h2>sem v1.1
|
||||
<h2>sigdel_0</h2>sigdel v1.0
|
||||
<br/>
|
||||
<div class="greydiv">
|
||||
<table class="connectionboxes">
|
||||
<tr>
|
||||
<td class="neighbor" rowspan="6">
|
||||
<td class="neighbor" rowspan="4">
|
||||
<a href="#module_cpu">cpu</a>
|
||||
</td>
|
||||
<td class="from">data_master  </td>
|
||||
<td class="main" rowspan="11">sem</td>
|
||||
<td class="main" rowspan="9">sigdel_0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  ctl_slave</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="from">data_master  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  ram_slave</td>
|
||||
<td class="to">  avalon_slave</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="from">debug_reset_request  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  reset_n</td>
|
||||
<td class="to">  reset_sink</td>
|
||||
</tr>
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
|
|
@ -1808,7 +1787,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<td class="from">clk_reset  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  reset_n</td>
|
||||
<td class="to">  reset_sink</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
|
|
@ -1820,8 +1799,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">m</td>
|
||||
<td class="parametervalue">32</td>
|
||||
<td class="parametername">PHACC_WIDTH</td>
|
||||
<td class="parametervalue">14</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
|
|
|
|||
File diff suppressed because one or more lines are too long
|
|
@ -1,16 +1,10 @@
|
|||
|
||||
module niosII (
|
||||
clk_clk,
|
||||
reset_reset_n,
|
||||
sem_export_train,
|
||||
sem_export_red,
|
||||
sem_export_yellow,
|
||||
sem_export_green);
|
||||
conduit_end_writeresponsevalid_n,
|
||||
reset_reset_n);
|
||||
|
||||
input clk_clk;
|
||||
output conduit_end_writeresponsevalid_n;
|
||||
input reset_reset_n;
|
||||
input sem_export_train;
|
||||
output sem_export_red;
|
||||
output sem_export_yellow;
|
||||
output sem_export_green;
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1,9 +1,6 @@
|
|||
niosII u0 (
|
||||
.clk_clk (<connected-to-clk_clk>), // clk.clk
|
||||
.reset_reset_n (<connected-to-reset_reset_n>), // reset.reset_n
|
||||
.sem_export_train (<connected-to-sem_export_train>), // sem_export.train
|
||||
.sem_export_red (<connected-to-sem_export_red>), // .red
|
||||
.sem_export_yellow (<connected-to-sem_export_yellow>), // .yellow
|
||||
.sem_export_green (<connected-to-sem_export_green>) // .green
|
||||
);
|
||||
|
||||
.clk_clk (<connected-to-clk_clk>), // clk.clk
|
||||
.conduit_end_writeresponsevalid_n (<connected-to-conduit_end_writeresponsevalid_n>), // conduit_end.writeresponsevalid_n
|
||||
.reset_reset_n (<connected-to-reset_reset_n>) // reset.reset_n
|
||||
);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,21 +1,15 @@
|
|||
component niosII is
|
||||
component niosII is
|
||||
port (
|
||||
clk_clk : in std_logic := 'X'; -- clk
|
||||
reset_reset_n : in std_logic := 'X'; -- reset_n
|
||||
sem_export_train : in std_logic := 'X'; -- train
|
||||
sem_export_red : out std_logic; -- red
|
||||
sem_export_yellow : out std_logic; -- yellow
|
||||
sem_export_green : out std_logic -- green
|
||||
clk_clk : in std_logic := 'X'; -- clk
|
||||
conduit_end_writeresponsevalid_n : out std_logic; -- writeresponsevalid_n
|
||||
reset_reset_n : in std_logic := 'X' -- reset_n
|
||||
);
|
||||
end component niosII;
|
||||
|
||||
u0 : component niosII
|
||||
end component niosII;
|
||||
|
||||
u0 : component niosII
|
||||
port map (
|
||||
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
|
||||
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
|
||||
sem_export_train => CONNECTED_TO_sem_export_train, -- sem_export.train
|
||||
sem_export_red => CONNECTED_TO_sem_export_red, -- .red
|
||||
sem_export_yellow => CONNECTED_TO_sem_export_yellow, -- .yellow
|
||||
sem_export_green => CONNECTED_TO_sem_export_green -- .green
|
||||
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
|
||||
conduit_end_writeresponsevalid_n => CONNECTED_TO_conduit_end_writeresponsevalid_n, -- conduit_end.writeresponsevalid_n
|
||||
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
|
||||
);
|
||||
|
||||
|
||||
|
|
|
|||
File diff suppressed because one or more lines are too long
|
|
@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy
|
|||
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"]
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1673967654"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1674830971"
|
||||
set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"]
|
||||
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"]
|
||||
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"]
|
||||
|
|
@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP
|
|||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3Mzk2NzY1NA==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3NDgzMDk3MQ==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U="
|
||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
|
||||
|
|
@ -128,7 +128,7 @@ set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "n
|
|||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Ng==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::Mg==::TnVtYmVyIG9mIG11eCBpbnB1dHM="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MA==::UGlwZWxpbmVkIGFyYml0cmF0aW9u"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u"
|
||||
|
|
@ -144,13 +144,13 @@ set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosI
|
|||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::Ng==::TnVtYmVyIG9mIG11eCBpbnB1dHM="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Ng==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::NQ==::TnVtYmVyIG9mIG11eCBpbnB1dHM="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MA==::UGlwZWxpbmVkIGFyYml0cmF0aW9u"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::NTg=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0NIRU1F::bm8tYXJi::QXJiaXRyYXRpb24gc2NoZW1l"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MSwxLDEsMSwxLDE=::QXJiaXRyYXRpb24gc2hhcmVz"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MSwxLDEsMSwx::QXJiaXRyYXRpb24gc2hhcmVz"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21tX2ludGVyY29ubmVjdF8wX3JzcF9kZW11eA=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBEZW11bHRpcGxleGVy"
|
||||
|
|
@ -160,7 +160,7 @@ set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "nio
|
|||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::UGFja2V0IGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Ng==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::MQ==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MQ==::VmFsaWQgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_rsp_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
|
||||
|
|
@ -174,7 +174,7 @@ set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "n
|
|||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Ng==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::Mg==::TnVtYmVyIG9mIG11eCBpbnB1dHM="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MQ==::UGlwZWxpbmVkIGFyYml0cmF0aW9u"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux_002" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u"
|
||||
|
|
@ -190,7 +190,7 @@ set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosI
|
|||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Ng==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::MQ==::TnVtYmVyIG9mIG11eCBpbnB1dHM="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MQ==::UGlwZWxpbmVkIGFyYml0cmF0aW9u"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_mux" -library "niosII" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u"
|
||||
|
|
@ -206,7 +206,7 @@ set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library
|
|||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::UGFja2V0IGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Ng==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::Mg==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MQ==::VmFsaWQgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
|
||||
|
|
@ -220,45 +220,45 @@ set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "nio
|
|||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::UGFja2V0IGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::Ng==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Ng==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::NQ==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MQ==::VmFsaWQgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::NTAwMDAwMDA=::QXV0byBDTE9DS19SQVRF"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21tX2ludGVyY29ubmVjdF8wX3JvdXRlcl8wMDg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MQ==::RGVzdGluYXRpb24gSUQ="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MQ==::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::cmVhZA==::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgw::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgw::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MQ==::Tm9uLXNlY3VyZWQgdGFncw=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MA==::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MA==::U2VjdXJlZCByYW5nZSBwYWlycw=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NTM=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::ODQ=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::ODI=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODA=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::Nzg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NTY=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MToxOjB4MDoweDA6cmVhZDoxOjA6MDox::U0xBVkVTX0lORk8="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::MQ==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21tX2ludGVyY29ubmVjdF8wX3JvdXRlcl8wMDc="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MQ==::RGVzdGluYXRpb24gSUQ="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MQ==::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::cmVhZA==::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgw::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgw::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MQ==::Tm9uLXNlY3VyZWQgdGFncw=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MA==::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MA==::U2VjdXJlZCByYW5nZSBwYWlycw=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NTM=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::ODQ=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::ODI=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODA=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::Nzg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NTY=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Ng==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MToxOjB4MDoweDA6cmVhZDoxOjA6MDox::U0xBVkVTX0lORk8="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::MQ==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoOTM6OTEpIHJlc3BvbnNlX3N0YXR1cyg5MDo4OSkgY2FjaGUoODg6ODUpIHByb3RlY3Rpb24oODQ6ODIpIHRocmVhZF9pZCg4MSkgZGVzdF9pZCg4MDo3OCkgc3JjX2lkKDc3Ojc1KSBxb3MoNzQpIGJlZ2luX2J1cnN0KDczKSBkYXRhX3NpZGViYW5kKDcyKSBhZGRyX3NpZGViYW5kKDcxKSBidXJzdF90eXBlKDcwOjY5KSBidXJzdF9zaXplKDY4OjY2KSBidXJzdHdyYXAoNjU6NjMpIGJ5dGVfY250KDYyOjYwKSB0cmFuc19leGNsdXNpdmUoNTkpIHRyYW5zX2xvY2soNTgpIHRyYW5zX3JlYWQoNTcpIHRyYW5zX3dyaXRlKDU2KSB0cmFuc19wb3N0ZWQoNTUpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg1NCkgYWRkcig1MzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21tX2ludGVyY29ubmVjdF8wX3JvdXRlcl8wMDQ="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
|
|
@ -283,7 +283,7 @@ set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "ni
|
|||
set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NTY=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Ng==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MDowMToweDA6MHgwOmJvdGg6MTowOjA6MSwxOjEwOjB4MDoweDA6cmVhZDoxOjA6MDox::U0xBVkVTX0lORk8="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs"
|
||||
|
|
@ -316,7 +316,7 @@ set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "ni
|
|||
set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NTY=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Ng==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MDoxOjB4MDoweDA6Ym90aDoxOjA6MDox::U0xBVkVTX0lORk8="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_002" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs"
|
||||
|
|
@ -349,7 +349,7 @@ set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "ni
|
|||
set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NTY=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Ng==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MjoxMDoweDA6MHgyMDAwMDpib3RoOjE6MDowOjEsMDowMToweDIwODAwOjB4MjEwMDA6Ym90aDoxOjA6MDox::U0xBVkVTX0lORk8="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MA==::RGVjb2RlciB0eXBl"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_001" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MQ==::RGVmYXVsdCBjaGFubmVs"
|
||||
|
|
@ -365,14 +365,14 @@ set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII
|
|||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MywwLDUsNiw0LDE=::RGVzdGluYXRpb24gSUQ="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MTAwMDAwLDAwMDEwMCwwMDEwMDAsMDEwMDAwLDAwMDAxMCwwMDAwMDE=::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxib3RoLHdyaXRlLGJvdGgsYm90aCxib3Ro::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgwLDB4MjA4MDAsMHgyMTAwMCwweDIxMDQwLDB4MjEwNjAsMHgyMTA2OA==::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgyMDAwMCwweDIxMDAwLDB4MjEwNDAsMHgyMTA2MCwweDIxMDY4LDB4MjEwNzA=::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwxLDEsMSwxLDE=::Tm9uLXNlY3VyZWQgdGFncw=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCwwLDAsMCwwLDA=::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCwwLDAsMCwwLDA=::U2VjdXJlZCByYW5nZSBwYWlycw=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MywwLDUsMSw0::RGVzdGluYXRpb24gSUQ="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MTAwMDAsMDAxMDAsMDEwMDAsMDAwMDEsMDAwMTA=::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxib3RoLGJvdGgsYm90aCx3cml0ZQ==::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgwLDB4MjA4MDAsMHgyMTAwMCwweDIxMDIwLDB4MjEwMjg=::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgyMDAwMCwweDIxMDAwLDB4MjEwMjAsMHgyMTAyOCwweDIxMDJj::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwxLDEsMSwx::Tm9uLXNlY3VyZWQgdGFncw=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCwwLDAsMCww::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCwwLDAsMCww::U2VjdXJlZCByYW5nZSBwYWlycw=="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::NTM=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::ODQ=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA=="
|
||||
|
|
@ -382,10 +382,10 @@ set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII
|
|||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NTY=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MzoxMDAwMDA6MHgwOjB4MjAwMDA6Ym90aDoxOjA6MDoxLDA6MDAwMTAwOjB4MjA4MDA6MHgyMTAwMDpib3RoOjE6MDowOjEsNTowMDEwMDA6MHgyMTAwMDoweDIxMDQwOndyaXRlOjE6MDowOjEsNjowMTAwMDA6MHgyMTA0MDoweDIxMDYwOmJvdGg6MTowOjA6MSw0OjAwMDAxMDoweDIxMDYwOjB4MjEwNjg6Ym90aDoxOjA6MDoxLDE6MDAwMDAxOjB4MjEwNjg6MHgyMTA3MDpib3RoOjE6MDowOjE=::U0xBVkVTX0lORk8="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Ng==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MzoxMDAwMDoweDA6MHgyMDAwMDpib3RoOjE6MDowOjEsMDowMDEwMDoweDIwODAwOjB4MjEwMDA6Ym90aDoxOjA6MDoxLDU6MDEwMDA6MHgyMTAwMDoweDIxMDIwOmJvdGg6MTowOjA6MSwxOjAwMDAxOjB4MjEwMjA6MHgyMTAyODpib3RoOjE6MDowOjEsNDowMDAxMDoweDIxMDI4OjB4MjEwMmM6d3JpdGU6MTowOjA6MQ==::U0xBVkVTX0lORk8="
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MA==::RGVjb2RlciB0eXBl"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::NQ==::RGVmYXVsdCBjaGFubmVs"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::NA==::RGVmYXVsdCBjaGFubmVs"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::Mw==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA=="
|
||||
|
|
@ -447,7 +447,7 @@ set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -nam
|
|||
set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODA=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::Nzg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1NZTUJPTF9X::OA==::UGFja2V0IHN5bWJvbCB3aWR0aA=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Ng==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "QVZTX0JVUlNUQ09VTlRfU1lNQk9MUw==::MA==::YnVyc3Rjb3VudFN5bWJvbHM="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "QVZTX0JVUlNUQ09VTlRfVw==::Mw==::YnVyc3Rjb3VudCB3aWR0aA=="
|
||||
|
|
@ -510,7 +510,7 @@ set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -na
|
|||
set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::ODA=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::Nzg=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Ng==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9X::Mw==::QXZhbG9uLU1NIGJ1cnN0Y291bnQgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "QVZfTElORVdSQVBCVVJTVFM=::MA==::bGluZXdyYXBCdXJzdHM="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "niosII" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RCT1VOREFSSUVT::MQ==::YnVyc3RPbkJ1cnN0Qm91bmRhcmllc09ubHk="
|
||||
|
|
@ -662,12 +662,12 @@ set_global_assignment -entity "niosII_sys_clk_timer" -library "niosII" -name IP_
|
|||
set_global_assignment -entity "niosII_sys_clk_timer" -library "niosII" -name IP_COMPONENT_PARAMETER "bXVsdA==::MC4wMDE=::bXVsdA=="
|
||||
set_global_assignment -entity "niosII_sys_clk_timer" -library "niosII" -name IP_COMPONENT_PARAMETER "dGlja3NQZXJTZWM=::MTAwMC4w::dGlja3NQZXJTZWM="
|
||||
set_global_assignment -entity "niosII_sys_clk_timer" -library "niosII" -name IP_COMPONENT_PARAMETER "c2xhdmVfYWRkcmVzc193aWR0aA==::Mw==::c2xhdmVfYWRkcmVzc193aWR0aA=="
|
||||
set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_NAME "ZGVj"
|
||||
set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "U2VtYWZvcg=="
|
||||
set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_VERSION "MS4x"
|
||||
set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_PARAMETER "bQ==::MzI=::bQ=="
|
||||
set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_NAME "c2lnZGVs"
|
||||
set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "U2lnbWEtRGVsdGEgTW9kdWxhdG9y"
|
||||
set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
|
||||
set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_PARAMETER "UEhBQ0NfV0lEVEg=::MTQ=::UEhBQ0NfV0lEVEg="
|
||||
set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21lbQ=="
|
||||
set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "T24tQ2hpcCBNZW1vcnkgKFJBTSBvciBST00pIEludGVsIEZQR0EgSVA="
|
||||
set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
|
|
@ -859,7 +859,7 @@ set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_
|
|||
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
|
||||
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
|
||||
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0="
|
||||
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDQwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTA0MCcgZW5kPScweDIxMDYwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTA2MCcgZW5kPScweDIxMDY4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDY4JyBlbmQ9JzB4MjEwNzAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0="
|
||||
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDIwJyBlbmQ9JzB4MjEwMjgnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzaWdkZWxfMC5hdmFsb25fc2xhdmUnIHN0YXJ0PScweDIxMDI4JyBlbmQ9JzB4MjEwMkMnIHR5cGU9J3NpZ2RlbC5hdmFsb25fc2xhdmUnIC8+PC9hZGRyZXNzLW1hcD4=::ZGF0YVNsYXZlTWFwUGFyYW0="
|
||||
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ=="
|
||||
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="
|
||||
|
|
@ -1042,7 +1042,7 @@ set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPON
|
|||
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
|
||||
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
|
||||
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0="
|
||||
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDQwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTA0MCcgZW5kPScweDIxMDYwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTA2MCcgZW5kPScweDIxMDY4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDY4JyBlbmQ9JzB4MjEwNzAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0="
|
||||
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDIwJyBlbmQ9JzB4MjEwMjgnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzaWdkZWxfMC5hdmFsb25fc2xhdmUnIHN0YXJ0PScweDIxMDI4JyBlbmQ9JzB4MjEwMkMnIHR5cGU9J3NpZ2RlbC5hdmFsb25fc2xhdmUnIC8+PC9hZGRyZXNzLW1hcD4=::ZGF0YVNsYXZlTWFwUGFyYW0="
|
||||
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ=="
|
||||
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="
|
||||
|
|
@ -1065,7 +1065,7 @@ set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::q
|
|||
set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_cmd_mux.sv"]
|
||||
set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_cmd_demux_001.sv"]
|
||||
set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_cmd_demux.sv"]
|
||||
set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_router_008.sv"]
|
||||
set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_router_007.sv"]
|
||||
set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_router_004.sv"]
|
||||
set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_router_002.sv"]
|
||||
set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mm_interconnect_0_router_001.sv"]
|
||||
|
|
@ -1077,8 +1077,11 @@ set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::q
|
|||
set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_translator.sv"]
|
||||
set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_translator.sv"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_sys_clk_timer.v"]
|
||||
set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/dec.sv"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/periodram.v"]
|
||||
set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/phacc.sv"]
|
||||
set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/sdmod.sv"]
|
||||
set_global_assignment -library "niosII" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/sigdel.sv"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/sinelut.v"]
|
||||
set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/sine256.mif"]
|
||||
set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_mem.hex"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mem.v"]
|
||||
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_jtag_uart.v"]
|
||||
|
|
@ -1129,9 +1132,9 @@ set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux_001" -library
|
|||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_cmd_demux" -library "niosII" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_TOOL_NAME "altera_merlin_router"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_008" -library "niosII" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_TOOL_NAME "altera_merlin_router"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_007" -library "niosII" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_TOOL_NAME "altera_merlin_router"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -entity "niosII_mm_interconnect_0_router_004" -library "niosII" -name IP_TOOL_ENV "Qsys"
|
||||
|
|
|
|||
|
|
@ -4,12 +4,9 @@
|
|||
|
||||
`timescale 1 ps / 1 ps
|
||||
module niosII (
|
||||
input wire clk_clk, // clk.clk
|
||||
input wire reset_reset_n, // reset.reset_n
|
||||
input wire sem_export_train, // sem_export.train
|
||||
output wire sem_export_red, // .red
|
||||
output wire sem_export_yellow, // .yellow
|
||||
output wire sem_export_green // .green
|
||||
input wire clk_clk, // clk.clk
|
||||
output wire conduit_end_writeresponsevalid_n, // conduit_end.writeresponsevalid_n
|
||||
input wire reset_reset_n // reset.reset_n
|
||||
);
|
||||
|
||||
wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata
|
||||
|
|
@ -31,11 +28,8 @@ module niosII (
|
|||
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
|
||||
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
|
||||
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
|
||||
wire [31:0] mm_interconnect_0_sem_ctl_slave_readdata; // sem:ctl_rddata -> mm_interconnect_0:sem_ctl_slave_readdata
|
||||
wire [0:0] mm_interconnect_0_sem_ctl_slave_address; // mm_interconnect_0:sem_ctl_slave_address -> sem:ctl_addr
|
||||
wire mm_interconnect_0_sem_ctl_slave_read; // mm_interconnect_0:sem_ctl_slave_read -> sem:ctl_rd
|
||||
wire mm_interconnect_0_sem_ctl_slave_write; // mm_interconnect_0:sem_ctl_slave_write -> sem:ctl_wr
|
||||
wire [31:0] mm_interconnect_0_sem_ctl_slave_writedata; // mm_interconnect_0:sem_ctl_slave_writedata -> sem:ctl_wrdata
|
||||
wire mm_interconnect_0_sigdel_0_avalon_slave_write; // mm_interconnect_0:sigdel_0_avalon_slave_write -> sigdel_0:wr_n
|
||||
wire [31:0] mm_interconnect_0_sigdel_0_avalon_slave_writedata; // mm_interconnect_0:sigdel_0_avalon_slave_writedata -> sigdel_0:wr_data
|
||||
wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_readdata; // cpu:debug_mem_slave_readdata -> mm_interconnect_0:cpu_debug_mem_slave_readdata
|
||||
wire mm_interconnect_0_cpu_debug_mem_slave_waitrequest; // cpu:debug_mem_slave_waitrequest -> mm_interconnect_0:cpu_debug_mem_slave_waitrequest
|
||||
wire mm_interconnect_0_cpu_debug_mem_slave_debugaccess; // mm_interconnect_0:cpu_debug_mem_slave_debugaccess -> cpu:debug_mem_slave_debugaccess
|
||||
|
|
@ -44,9 +38,6 @@ module niosII (
|
|||
wire [3:0] mm_interconnect_0_cpu_debug_mem_slave_byteenable; // mm_interconnect_0:cpu_debug_mem_slave_byteenable -> cpu:debug_mem_slave_byteenable
|
||||
wire mm_interconnect_0_cpu_debug_mem_slave_write; // mm_interconnect_0:cpu_debug_mem_slave_write -> cpu:debug_mem_slave_write
|
||||
wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_writedata; // mm_interconnect_0:cpu_debug_mem_slave_writedata -> cpu:debug_mem_slave_writedata
|
||||
wire [3:0] mm_interconnect_0_sem_ram_slave_address; // mm_interconnect_0:sem_ram_slave_address -> sem:ram_addr
|
||||
wire mm_interconnect_0_sem_ram_slave_write; // mm_interconnect_0:sem_ram_slave_write -> sem:ram_wr
|
||||
wire [31:0] mm_interconnect_0_sem_ram_slave_writedata; // mm_interconnect_0:sem_ram_slave_writedata -> sem:ram_wrdata
|
||||
wire mm_interconnect_0_sys_clk_timer_s1_chipselect; // mm_interconnect_0:sys_clk_timer_s1_chipselect -> sys_clk_timer:chipselect
|
||||
wire [15:0] mm_interconnect_0_sys_clk_timer_s1_readdata; // sys_clk_timer:readdata -> mm_interconnect_0:sys_clk_timer_s1_readdata
|
||||
wire [2:0] mm_interconnect_0_sys_clk_timer_s1_address; // mm_interconnect_0:sys_clk_timer_s1_address -> sys_clk_timer:address
|
||||
|
|
@ -69,7 +60,7 @@ module niosII (
|
|||
wire irq_mapper_receiver0_irq; // sys_clk_timer:irq -> irq_mapper:receiver0_irq
|
||||
wire irq_mapper_receiver1_irq; // jtag_uart:av_irq -> irq_mapper:receiver1_irq
|
||||
wire [31:0] cpu_irq_irq; // irq_mapper:sender_irq -> cpu:irq
|
||||
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [cpu:reset_n, irq_mapper:reset, jtag_uart:rst_n, mem:reset, mm_interconnect_0:cpu_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sem:clrn, sys_clk_timer:reset_n]
|
||||
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [cpu:reset_n, irq_mapper:reset, jtag_uart:rst_n, mem:reset, mm_interconnect_0:cpu_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sigdel_0:clr_n, sys_clk_timer:reset_n]
|
||||
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [cpu:reset_req, mem:reset_req, rst_translator:reset_req_in]
|
||||
wire cpu_debug_reset_request_reset; // cpu:debug_reset_request -> rst_controller:reset_in1
|
||||
|
||||
|
|
@ -136,23 +127,14 @@ module niosII (
|
|||
.freeze (1'b0) // (terminated)
|
||||
);
|
||||
|
||||
dec #(
|
||||
.m (32)
|
||||
) sem (
|
||||
.clk (clk_clk), // clock.clk
|
||||
.ctl_wr (mm_interconnect_0_sem_ctl_slave_write), // ctl_slave.write
|
||||
.ctl_rd (mm_interconnect_0_sem_ctl_slave_read), // .read
|
||||
.ctl_addr (mm_interconnect_0_sem_ctl_slave_address), // .address
|
||||
.ctl_wrdata (mm_interconnect_0_sem_ctl_slave_writedata), // .writedata
|
||||
.ctl_rddata (mm_interconnect_0_sem_ctl_slave_readdata), // .readdata
|
||||
.clrn (~rst_controller_reset_out_reset), // reset_n.reset_n
|
||||
.ram_wr (mm_interconnect_0_sem_ram_slave_write), // ram_slave.write
|
||||
.ram_addr (mm_interconnect_0_sem_ram_slave_address), // .address
|
||||
.ram_wrdata (mm_interconnect_0_sem_ram_slave_writedata), // .writedata
|
||||
.train (sem_export_train), // sem.train
|
||||
.red (sem_export_red), // .red
|
||||
.yellow (sem_export_yellow), // .yellow
|
||||
.green (sem_export_green) // .green
|
||||
sigdel #(
|
||||
.PHACC_WIDTH (14)
|
||||
) sigdel_0 (
|
||||
.clk (clk_clk), // clock.clk
|
||||
.clr_n (~rst_controller_reset_out_reset), // reset_sink.reset_n
|
||||
.fout (conduit_end_writeresponsevalid_n), // conduit_end.writeresponsevalid_n
|
||||
.wr_n (~mm_interconnect_0_sigdel_0_avalon_slave_write), // avalon_slave.write_n
|
||||
.wr_data (mm_interconnect_0_sigdel_0_avalon_slave_writedata) // .writedata
|
||||
);
|
||||
|
||||
niosII_sys_clk_timer sys_clk_timer (
|
||||
|
|
@ -210,14 +192,8 @@ module niosII (
|
|||
.mem_s2_byteenable (mm_interconnect_0_mem_s2_byteenable), // .byteenable
|
||||
.mem_s2_chipselect (mm_interconnect_0_mem_s2_chipselect), // .chipselect
|
||||
.mem_s2_clken (mm_interconnect_0_mem_s2_clken), // .clken
|
||||
.sem_ctl_slave_address (mm_interconnect_0_sem_ctl_slave_address), // sem_ctl_slave.address
|
||||
.sem_ctl_slave_write (mm_interconnect_0_sem_ctl_slave_write), // .write
|
||||
.sem_ctl_slave_read (mm_interconnect_0_sem_ctl_slave_read), // .read
|
||||
.sem_ctl_slave_readdata (mm_interconnect_0_sem_ctl_slave_readdata), // .readdata
|
||||
.sem_ctl_slave_writedata (mm_interconnect_0_sem_ctl_slave_writedata), // .writedata
|
||||
.sem_ram_slave_address (mm_interconnect_0_sem_ram_slave_address), // sem_ram_slave.address
|
||||
.sem_ram_slave_write (mm_interconnect_0_sem_ram_slave_write), // .write
|
||||
.sem_ram_slave_writedata (mm_interconnect_0_sem_ram_slave_writedata), // .writedata
|
||||
.sigdel_0_avalon_slave_write (mm_interconnect_0_sigdel_0_avalon_slave_write), // sigdel_0_avalon_slave.write
|
||||
.sigdel_0_avalon_slave_writedata (mm_interconnect_0_sigdel_0_avalon_slave_writedata), // .writedata
|
||||
.sys_clk_timer_s1_address (mm_interconnect_0_sys_clk_timer_s1_address), // sys_clk_timer_s1.address
|
||||
.sys_clk_timer_s1_write (mm_interconnect_0_sys_clk_timer_s1_write), // .write
|
||||
.sys_clk_timer_s1_readdata (mm_interconnect_0_sys_clk_timer_s1_readdata), // .readdata
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -11,262 +11,262 @@
|
|||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2010 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $
|
||||
// $Revision: #3 $
|
||||
// $Date: 2010/07/07 $
|
||||
// $Author: jyeap $
|
||||
|
||||
/* -----------------------------------------------------------------------
|
||||
Round-robin/fixed arbitration implementation.
|
||||
|
||||
Q: how do you find the least-significant set-bit in an n-bit binary number, X?
|
||||
|
||||
A: M = X & (~X + 1)
|
||||
|
||||
Example: X = 101000100
|
||||
101000100 &
|
||||
010111011 + 1 =
|
||||
|
||||
101000100 &
|
||||
010111100 =
|
||||
-----------
|
||||
000000100
|
||||
|
||||
The method can be generalized to find the first set-bit
|
||||
at a bit index no lower than bit-index N, simply by adding
|
||||
2**N rather than 1.
|
||||
|
||||
|
||||
Q: how does this relate to round-robin arbitration?
|
||||
A:
|
||||
Let X be the concatenation of all request signals.
|
||||
Let the number to be added to X (hereafter called the
|
||||
top_priority) initialize to 1, and be assigned from the
|
||||
concatenation of the previous saved-grant, left-rotated
|
||||
by one position, each time arbitration occurs. The
|
||||
concatenation of grants is then M.
|
||||
|
||||
Problem: consider this case:
|
||||
|
||||
top_priority = 010000
|
||||
request = 001001
|
||||
~request + top_priority = 000110
|
||||
next_grant = 000000 <- no one is granted!
|
||||
|
||||
There was no "set bit at a bit index no lower than bit-index 4", so
|
||||
the result was 0.
|
||||
|
||||
We need to propagate the carry out from (~request + top_priority) to the LSB, so
|
||||
that the sum becomes 000111, and next_grant is 000001. This operation could be
|
||||
called a "circular add".
|
||||
|
||||
A bit of experimentation on the circular add reveals a significant amount of
|
||||
delay in exiting and re-entering the carry chain - this will vary with device
|
||||
family. Quartus also reports a combinational loop warning. Finally,
|
||||
Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But
|
||||
Modelsim _doesn't_ report a combinational loop!)
|
||||
|
||||
An alternate solution: concatenate the request vector with itself, and OR
|
||||
corresponding bits from the top and bottom halves to determine next_grant.
|
||||
|
||||
Example:
|
||||
|
||||
top_priority = 010000
|
||||
{request, request} = 001001 001001
|
||||
{~request, ~request} + top_priority = 110111 000110
|
||||
result of & operation = 000001 000000
|
||||
next_grant = 000001
|
||||
|
||||
Notice that if request = 0, the sum operation will overflow, but we can ignore
|
||||
this; the next_grant result is 0 (no one granted), as you might expect.
|
||||
In the implementation, the last-granted value must be maintained as
|
||||
a non-zero value - best probably simply not to update it when no requests
|
||||
occur.
|
||||
|
||||
----------------------------------------------------------------------- */
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_arbitrator
|
||||
#(
|
||||
parameter NUM_REQUESTERS = 8,
|
||||
// --------------------------------------
|
||||
// Implemented schemes
|
||||
// "round-robin"
|
||||
// "fixed-priority"
|
||||
// "no-arb"
|
||||
// --------------------------------------
|
||||
parameter SCHEME = "round-robin",
|
||||
parameter PIPELINE = 0
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// --------------------------------------
|
||||
// Requests
|
||||
// --------------------------------------
|
||||
input [NUM_REQUESTERS-1:0] request,
|
||||
|
||||
// --------------------------------------
|
||||
// Grants
|
||||
// --------------------------------------
|
||||
output [NUM_REQUESTERS-1:0] grant,
|
||||
|
||||
// --------------------------------------
|
||||
// Control Signals
|
||||
// --------------------------------------
|
||||
input increment_top_priority,
|
||||
input save_top_priority
|
||||
);
|
||||
|
||||
// --------------------------------------
|
||||
// Signals
|
||||
// --------------------------------------
|
||||
wire [NUM_REQUESTERS-1:0] top_priority;
|
||||
reg [NUM_REQUESTERS-1:0] top_priority_reg;
|
||||
reg [NUM_REQUESTERS-1:0] last_grant;
|
||||
wire [2*NUM_REQUESTERS-1:0] result;
|
||||
|
||||
// --------------------------------------
|
||||
// Scheme Selection
|
||||
// --------------------------------------
|
||||
generate
|
||||
if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
|
||||
assign top_priority = top_priority_reg;
|
||||
end
|
||||
else begin
|
||||
// Fixed arbitration (or single-requester corner case)
|
||||
assign top_priority = 1'b1;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------
|
||||
// Decision Logic
|
||||
// --------------------------------------
|
||||
altera_merlin_arb_adder
|
||||
#(
|
||||
.WIDTH (2 * NUM_REQUESTERS)
|
||||
)
|
||||
adder
|
||||
(
|
||||
.a ({ ~request, ~request }),
|
||||
.b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
|
||||
.sum (result)
|
||||
);
|
||||
|
||||
|
||||
generate if (SCHEME == "no-arb") begin
|
||||
|
||||
// --------------------------------------
|
||||
// No arbitration: just wire request directly to grant
|
||||
// --------------------------------------
|
||||
assign grant = request;
|
||||
|
||||
end else begin
|
||||
// Do the math in double-vector domain
|
||||
wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
|
||||
assign grant_double_vector = {request, request} & result;
|
||||
|
||||
// --------------------------------------
|
||||
// Extract grant from the top and bottom halves
|
||||
// of the double vector.
|
||||
// --------------------------------------
|
||||
assign grant =
|
||||
grant_double_vector[NUM_REQUESTERS - 1 : 0] |
|
||||
grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------
|
||||
// Left-rotate the last grant vector to create top_priority.
|
||||
// --------------------------------------
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
top_priority_reg <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if (PIPELINE) begin
|
||||
if (increment_top_priority) begin
|
||||
top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
|
||||
grant[NUM_REQUESTERS-1]} : top_priority_reg;
|
||||
end
|
||||
end else begin
|
||||
if (increment_top_priority) begin
|
||||
if (|request)
|
||||
top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
|
||||
grant[NUM_REQUESTERS-1] };
|
||||
else
|
||||
top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
|
||||
end
|
||||
else if (save_top_priority) begin
|
||||
top_priority_reg <= grant;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ----------------------------------------------
|
||||
// Adder for the standard arbitrator
|
||||
// ----------------------------------------------
|
||||
module altera_merlin_arb_adder
|
||||
#(
|
||||
parameter WIDTH = 8
|
||||
)
|
||||
(
|
||||
input [WIDTH-1:0] a,
|
||||
input [WIDTH-1:0] b,
|
||||
|
||||
output [WIDTH-1:0] sum
|
||||
);
|
||||
|
||||
wire [WIDTH:0] sum_lint;
|
||||
// ----------------------------------------------
|
||||
// Benchmarks indicate that for small widths, the full
|
||||
// adder has higher fmax because synthesis can merge
|
||||
// it with the mux, allowing partial decisions to be
|
||||
// made early.
|
||||
//
|
||||
// The magic number is 4 requesters, which means an
|
||||
// 8 bit adder.
|
||||
// ----------------------------------------------
|
||||
genvar i;
|
||||
generate if (WIDTH <= 8) begin : full_adder
|
||||
|
||||
wire cout[WIDTH-1:0];
|
||||
|
||||
assign sum[0] = (a[0] ^ b[0]);
|
||||
assign cout[0] = (a[0] & b[0]);
|
||||
|
||||
for (i = 1; i < WIDTH; i = i+1) begin : arb
|
||||
|
||||
assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
|
||||
assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
|
||||
|
||||
end
|
||||
|
||||
end else begin : carry_chain
|
||||
|
||||
assign sum_lint = a + b;
|
||||
assign sum = sum_lint[WIDTH-1:0];
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
// (C) 2001-2010 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $
|
||||
// $Revision: #3 $
|
||||
// $Date: 2010/07/07 $
|
||||
// $Author: jyeap $
|
||||
|
||||
/* -----------------------------------------------------------------------
|
||||
Round-robin/fixed arbitration implementation.
|
||||
|
||||
Q: how do you find the least-significant set-bit in an n-bit binary number, X?
|
||||
|
||||
A: M = X & (~X + 1)
|
||||
|
||||
Example: X = 101000100
|
||||
101000100 &
|
||||
010111011 + 1 =
|
||||
|
||||
101000100 &
|
||||
010111100 =
|
||||
-----------
|
||||
000000100
|
||||
|
||||
The method can be generalized to find the first set-bit
|
||||
at a bit index no lower than bit-index N, simply by adding
|
||||
2**N rather than 1.
|
||||
|
||||
|
||||
Q: how does this relate to round-robin arbitration?
|
||||
A:
|
||||
Let X be the concatenation of all request signals.
|
||||
Let the number to be added to X (hereafter called the
|
||||
top_priority) initialize to 1, and be assigned from the
|
||||
concatenation of the previous saved-grant, left-rotated
|
||||
by one position, each time arbitration occurs. The
|
||||
concatenation of grants is then M.
|
||||
|
||||
Problem: consider this case:
|
||||
|
||||
top_priority = 010000
|
||||
request = 001001
|
||||
~request + top_priority = 000110
|
||||
next_grant = 000000 <- no one is granted!
|
||||
|
||||
There was no "set bit at a bit index no lower than bit-index 4", so
|
||||
the result was 0.
|
||||
|
||||
We need to propagate the carry out from (~request + top_priority) to the LSB, so
|
||||
that the sum becomes 000111, and next_grant is 000001. This operation could be
|
||||
called a "circular add".
|
||||
|
||||
A bit of experimentation on the circular add reveals a significant amount of
|
||||
delay in exiting and re-entering the carry chain - this will vary with device
|
||||
family. Quartus also reports a combinational loop warning. Finally,
|
||||
Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But
|
||||
Modelsim _doesn't_ report a combinational loop!)
|
||||
|
||||
An alternate solution: concatenate the request vector with itself, and OR
|
||||
corresponding bits from the top and bottom halves to determine next_grant.
|
||||
|
||||
Example:
|
||||
|
||||
top_priority = 010000
|
||||
{request, request} = 001001 001001
|
||||
{~request, ~request} + top_priority = 110111 000110
|
||||
result of & operation = 000001 000000
|
||||
next_grant = 000001
|
||||
|
||||
Notice that if request = 0, the sum operation will overflow, but we can ignore
|
||||
this; the next_grant result is 0 (no one granted), as you might expect.
|
||||
In the implementation, the last-granted value must be maintained as
|
||||
a non-zero value - best probably simply not to update it when no requests
|
||||
occur.
|
||||
|
||||
----------------------------------------------------------------------- */
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_arbitrator
|
||||
#(
|
||||
parameter NUM_REQUESTERS = 8,
|
||||
// --------------------------------------
|
||||
// Implemented schemes
|
||||
// "round-robin"
|
||||
// "fixed-priority"
|
||||
// "no-arb"
|
||||
// --------------------------------------
|
||||
parameter SCHEME = "round-robin",
|
||||
parameter PIPELINE = 0
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// --------------------------------------
|
||||
// Requests
|
||||
// --------------------------------------
|
||||
input [NUM_REQUESTERS-1:0] request,
|
||||
|
||||
// --------------------------------------
|
||||
// Grants
|
||||
// --------------------------------------
|
||||
output [NUM_REQUESTERS-1:0] grant,
|
||||
|
||||
// --------------------------------------
|
||||
// Control Signals
|
||||
// --------------------------------------
|
||||
input increment_top_priority,
|
||||
input save_top_priority
|
||||
);
|
||||
|
||||
// --------------------------------------
|
||||
// Signals
|
||||
// --------------------------------------
|
||||
wire [NUM_REQUESTERS-1:0] top_priority;
|
||||
reg [NUM_REQUESTERS-1:0] top_priority_reg;
|
||||
reg [NUM_REQUESTERS-1:0] last_grant;
|
||||
wire [2*NUM_REQUESTERS-1:0] result;
|
||||
|
||||
// --------------------------------------
|
||||
// Scheme Selection
|
||||
// --------------------------------------
|
||||
generate
|
||||
if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
|
||||
assign top_priority = top_priority_reg;
|
||||
end
|
||||
else begin
|
||||
// Fixed arbitration (or single-requester corner case)
|
||||
assign top_priority = 1'b1;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------
|
||||
// Decision Logic
|
||||
// --------------------------------------
|
||||
altera_merlin_arb_adder
|
||||
#(
|
||||
.WIDTH (2 * NUM_REQUESTERS)
|
||||
)
|
||||
adder
|
||||
(
|
||||
.a ({ ~request, ~request }),
|
||||
.b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
|
||||
.sum (result)
|
||||
);
|
||||
|
||||
|
||||
generate if (SCHEME == "no-arb") begin
|
||||
|
||||
// --------------------------------------
|
||||
// No arbitration: just wire request directly to grant
|
||||
// --------------------------------------
|
||||
assign grant = request;
|
||||
|
||||
end else begin
|
||||
// Do the math in double-vector domain
|
||||
wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
|
||||
assign grant_double_vector = {request, request} & result;
|
||||
|
||||
// --------------------------------------
|
||||
// Extract grant from the top and bottom halves
|
||||
// of the double vector.
|
||||
// --------------------------------------
|
||||
assign grant =
|
||||
grant_double_vector[NUM_REQUESTERS - 1 : 0] |
|
||||
grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------
|
||||
// Left-rotate the last grant vector to create top_priority.
|
||||
// --------------------------------------
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
top_priority_reg <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if (PIPELINE) begin
|
||||
if (increment_top_priority) begin
|
||||
top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
|
||||
grant[NUM_REQUESTERS-1]} : top_priority_reg;
|
||||
end
|
||||
end else begin
|
||||
if (increment_top_priority) begin
|
||||
if (|request)
|
||||
top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
|
||||
grant[NUM_REQUESTERS-1] };
|
||||
else
|
||||
top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
|
||||
end
|
||||
else if (save_top_priority) begin
|
||||
top_priority_reg <= grant;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ----------------------------------------------
|
||||
// Adder for the standard arbitrator
|
||||
// ----------------------------------------------
|
||||
module altera_merlin_arb_adder
|
||||
#(
|
||||
parameter WIDTH = 8
|
||||
)
|
||||
(
|
||||
input [WIDTH-1:0] a,
|
||||
input [WIDTH-1:0] b,
|
||||
|
||||
output [WIDTH-1:0] sum
|
||||
);
|
||||
|
||||
wire [WIDTH:0] sum_lint;
|
||||
// ----------------------------------------------
|
||||
// Benchmarks indicate that for small widths, the full
|
||||
// adder has higher fmax because synthesis can merge
|
||||
// it with the mux, allowing partial decisions to be
|
||||
// made early.
|
||||
//
|
||||
// The magic number is 4 requesters, which means an
|
||||
// 8 bit adder.
|
||||
// ----------------------------------------------
|
||||
genvar i;
|
||||
generate if (WIDTH <= 8) begin : full_adder
|
||||
|
||||
wire cout[WIDTH-1:0];
|
||||
|
||||
assign sum[0] = (a[0] ^ b[0]);
|
||||
assign cout[0] = (a[0] & b[0]);
|
||||
|
||||
for (i = 1; i < WIDTH; i = i+1) begin : arb
|
||||
|
||||
assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
|
||||
assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
|
||||
|
||||
end
|
||||
|
||||
end else begin : carry_chain
|
||||
|
||||
assign sum_lint = a + b;
|
||||
assign sum = sum_lint[WIDTH-1:0];
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -11,286 +11,286 @@
|
|||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2012 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2018/07/18 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// ------------------------------------------
|
||||
// Merlin Burst Uncompressor
|
||||
//
|
||||
// Compressed read bursts -> uncompressed
|
||||
// ------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_burst_uncompressor
|
||||
#(
|
||||
parameter ADDR_W = 16,
|
||||
parameter BURSTWRAP_W = 3,
|
||||
parameter BYTE_CNT_W = 4,
|
||||
parameter PKT_SYMBOLS = 4,
|
||||
parameter BURST_SIZE_W = 3
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// sink ST signals
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
input sink_valid,
|
||||
output sink_ready,
|
||||
|
||||
// sink ST "data"
|
||||
input [ADDR_W - 1: 0] sink_addr,
|
||||
input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
|
||||
input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
|
||||
input sink_is_compressed,
|
||||
input [BURST_SIZE_W-1 : 0] sink_burstsize,
|
||||
|
||||
// source ST signals
|
||||
output source_startofpacket,
|
||||
output source_endofpacket,
|
||||
output source_valid,
|
||||
input source_ready,
|
||||
|
||||
// source ST "data"
|
||||
output [ADDR_W - 1: 0] source_addr,
|
||||
output [BURSTWRAP_W - 1 : 0] source_burstwrap,
|
||||
output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
|
||||
|
||||
// Note: in the slave agent, the output should always be uncompressed. In
|
||||
// other applications, it may be required to leave-compressed or not. How to
|
||||
// control? Seems like a simple mux - pass-through if no uncompression is
|
||||
// required.
|
||||
output source_is_compressed,
|
||||
output [BURST_SIZE_W-1 : 0] source_burstsize
|
||||
);
|
||||
|
||||
//----------------------------------------------------
|
||||
// AXSIZE decoding
|
||||
//
|
||||
// Turns the axsize value into the actual number of bytes
|
||||
// being transferred.
|
||||
// ---------------------------------------------------
|
||||
function reg[63:0] bytes_in_transfer;
|
||||
input [BURST_SIZE_W-1:0] axsize;
|
||||
case (axsize)
|
||||
4'b0000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
|
||||
4'b0001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010;
|
||||
4'b0010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100;
|
||||
4'b0011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000;
|
||||
4'b0100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000;
|
||||
4'b0101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000;
|
||||
4'b0110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000;
|
||||
4'b0111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000;
|
||||
4'b1000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000100000000;
|
||||
4'b1001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000001000000000;
|
||||
default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
|
||||
endcase
|
||||
|
||||
endfunction
|
||||
|
||||
// num_symbols is PKT_SYMBOLS, appropriately sized.
|
||||
wire [31:0] int_num_symbols = PKT_SYMBOLS;
|
||||
wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
|
||||
|
||||
// def: Burst Compression. In a merlin network, a compressed burst is one
|
||||
// which is transmitted in a single beat. Example: read burst. In
|
||||
// constrast, an uncompressed burst (example: write burst) is transmitted in
|
||||
// one beat per writedata item.
|
||||
//
|
||||
// For compressed bursts which require response packets, burst
|
||||
// uncompression is required. Concrete example: a read burst of size 8
|
||||
// occupies one response-fifo position. When that fifo position reaches the
|
||||
// front of the FIFO, the slave starts providing the required 8 readdatavalid
|
||||
// pulses. The 8 return response beats must be provided in a single packet,
|
||||
// with incrementing address and decrementing byte_cnt fields. Upon receipt
|
||||
// of the final readdata item of the burst, the response FIFO item is
|
||||
// retired.
|
||||
// Burst uncompression logic provides:
|
||||
// a) 2-state FSM (idle, busy)
|
||||
// reset to idle state
|
||||
// transition to busy state for 2nd and subsequent rdv pulses
|
||||
// - a single-cycle burst (aka non-burst read) causes no transition to
|
||||
// busy state.
|
||||
// b) response startofpacket/endofpacket logic. The response FIFO item
|
||||
// will have sop asserted, and may have eop asserted. (In the case of
|
||||
// multiple read bursts transmit in the command fabric in a single packet,
|
||||
// the eop assertion will come in a later FIFO item.) To support packet
|
||||
// conservation, and emit a well-formed packet on the response fabric,
|
||||
// i) response fabric startofpacket is asserted only for the first resp.
|
||||
// beat;
|
||||
// ii) response fabric endofpacket is asserted only for the last resp.
|
||||
// beat.
|
||||
// c) response address field. The response address field contains an
|
||||
// incrementing sequence, such that each readdata item is associated with
|
||||
// its slave-map location. N.b. a) computing the address correctly requires
|
||||
// knowledge of burstwrap behavior b) there may be no clients of the address
|
||||
// field, which makes this field a good target for optimization. See
|
||||
// burst_uncompress_address_counter below.
|
||||
// d) response byte_cnt field. The response byte_cnt field contains a
|
||||
// decrementing sequence, such that each beat of the response contains the
|
||||
// count of bytes to follow. In the case of sub-bursts in a single packet,
|
||||
// the byte_cnt field may decrement down to num_symbols, then back up to
|
||||
// some value, multiple times in the packet.
|
||||
|
||||
reg burst_uncompress_busy;
|
||||
reg [BYTE_CNT_W:0] burst_uncompress_byte_counter;
|
||||
wire [BYTE_CNT_W-1:0] burst_uncompress_byte_counter_lint;
|
||||
wire first_packet_beat;
|
||||
wire last_packet_beat;
|
||||
|
||||
assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
|
||||
assign burst_uncompress_byte_counter_lint = burst_uncompress_byte_counter[BYTE_CNT_W-1:0];
|
||||
|
||||
// First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to
|
||||
// the output.
|
||||
assign source_byte_cnt =
|
||||
first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter_lint;
|
||||
assign source_valid = sink_valid;
|
||||
|
||||
// Last packet beat is set throughout receipt of an uncompressed read burst
|
||||
// from the response FIFO - this forces all the burst uncompression machinery
|
||||
// idle.
|
||||
assign last_packet_beat = ~sink_is_compressed |
|
||||
(
|
||||
burst_uncompress_busy ?
|
||||
(sink_valid & (burst_uncompress_byte_counter_lint == num_symbols)) :
|
||||
sink_valid & (sink_byte_cnt == num_symbols)
|
||||
);
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
burst_uncompress_busy <= '0;
|
||||
burst_uncompress_byte_counter <= '0;
|
||||
end
|
||||
else begin
|
||||
if (source_valid & source_ready & sink_valid) begin
|
||||
// No matter what the current state, last_packet_beat leads to
|
||||
// idle.
|
||||
if (last_packet_beat) begin
|
||||
burst_uncompress_busy <= '0;
|
||||
burst_uncompress_byte_counter <= '0;
|
||||
end
|
||||
else begin
|
||||
if (burst_uncompress_busy) begin
|
||||
burst_uncompress_byte_counter <= (burst_uncompress_byte_counter > 0) ?
|
||||
(burst_uncompress_byte_counter_lint - num_symbols) :
|
||||
(sink_byte_cnt - num_symbols);
|
||||
end
|
||||
else begin // not busy, at least one more beat to go
|
||||
burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols;
|
||||
// To do: should busy go true for numsymbols-size compressed
|
||||
// bursts?
|
||||
burst_uncompress_busy <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
|
||||
reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
|
||||
|
||||
wire [63:0] decoded_burstsize_wire;
|
||||
wire [ADDR_W-1:0] decoded_burstsize;
|
||||
|
||||
|
||||
localparam ADD_BURSTWRAP_W = (ADDR_W > BURSTWRAP_W) ? ADDR_W : BURSTWRAP_W;
|
||||
wire [ADD_BURSTWRAP_W-1:0] addr_width_burstwrap;
|
||||
// The input burstwrap value can be used as a mask against address values,
|
||||
// but with one caveat: the address width may be (probably is) wider than
|
||||
// the burstwrap width. The spec says: extend the msb of the burstwrap
|
||||
// value out over the entire address width (but only if the address width
|
||||
// actually is wider than the burstwrap width; otherwise it's a 0-width or
|
||||
// negative range and concatenation multiplier).
|
||||
generate
|
||||
if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
|
||||
// Sign-extend, just wires:
|
||||
assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
|
||||
{(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
|
||||
assign addr_width_burstwrap[BURSTWRAP_W-1:0] = sink_burstwrap [BURSTWRAP_W-1:0];
|
||||
end
|
||||
else begin
|
||||
assign addr_width_burstwrap[BURSTWRAP_W-1 : 0] = sink_burstwrap;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
burst_uncompress_address_base <= '0;
|
||||
end
|
||||
else if (first_packet_beat & source_ready) begin
|
||||
burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
|
||||
end
|
||||
end
|
||||
|
||||
assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits
|
||||
assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed
|
||||
|
||||
wire [ADDR_W : 0] p1_burst_uncompress_address_offset =
|
||||
(
|
||||
(first_packet_beat ?
|
||||
sink_addr :
|
||||
burst_uncompress_address_offset) + decoded_burstsize
|
||||
) &
|
||||
addr_width_burstwrap[ADDR_W-1:0];
|
||||
wire [ADDR_W-1:0] p1_burst_uncompress_address_offset_lint = p1_burst_uncompress_address_offset [ADDR_W-1:0];
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
burst_uncompress_address_offset <= '0;
|
||||
end
|
||||
else begin
|
||||
if (source_ready & source_valid) begin
|
||||
burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
|
||||
// if (first_packet_beat) begin
|
||||
// burst_uncompress_address_offset <=
|
||||
// (sink_addr + num_symbols) & addr_width_burstwrap;
|
||||
// end
|
||||
// else begin
|
||||
// burst_uncompress_address_offset <=
|
||||
// (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap;
|
||||
// end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// On the first packet beat, send the input address out unchanged,
|
||||
// while values are computed/registered for 2nd and subsequent beats.
|
||||
assign source_addr = first_packet_beat ? sink_addr :
|
||||
burst_uncompress_address_base | burst_uncompress_address_offset;
|
||||
assign source_burstwrap = sink_burstwrap;
|
||||
assign source_burstsize = sink_burstsize;
|
||||
|
||||
//-------------------------------------------------------------------
|
||||
// A single (compressed) read burst will have sop/eop in the same beat.
|
||||
// A sequence of read sub-bursts emitted by a burst adapter in response to a
|
||||
// single read burst will have sop on the first sub-burst, eop on the last.
|
||||
// Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve
|
||||
// packet conservation.
|
||||
assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
|
||||
assign source_endofpacket = sink_endofpacket & last_packet_beat;
|
||||
assign sink_ready = source_valid & source_ready & last_packet_beat;
|
||||
|
||||
// This is correct for the slave agent usage, but won't always be true in the
|
||||
// width adapter. To do: add an "please uncompress" input, and use it to
|
||||
// pass-through or modify, and set source_is_compressed accordingly.
|
||||
assign source_is_compressed = 1'b0;
|
||||
endmodule
|
||||
|
||||
// (C) 2001-2012 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2018/07/18 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// ------------------------------------------
|
||||
// Merlin Burst Uncompressor
|
||||
//
|
||||
// Compressed read bursts -> uncompressed
|
||||
// ------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_burst_uncompressor
|
||||
#(
|
||||
parameter ADDR_W = 16,
|
||||
parameter BURSTWRAP_W = 3,
|
||||
parameter BYTE_CNT_W = 4,
|
||||
parameter PKT_SYMBOLS = 4,
|
||||
parameter BURST_SIZE_W = 3
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// sink ST signals
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
input sink_valid,
|
||||
output sink_ready,
|
||||
|
||||
// sink ST "data"
|
||||
input [ADDR_W - 1: 0] sink_addr,
|
||||
input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
|
||||
input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
|
||||
input sink_is_compressed,
|
||||
input [BURST_SIZE_W-1 : 0] sink_burstsize,
|
||||
|
||||
// source ST signals
|
||||
output source_startofpacket,
|
||||
output source_endofpacket,
|
||||
output source_valid,
|
||||
input source_ready,
|
||||
|
||||
// source ST "data"
|
||||
output [ADDR_W - 1: 0] source_addr,
|
||||
output [BURSTWRAP_W - 1 : 0] source_burstwrap,
|
||||
output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
|
||||
|
||||
// Note: in the slave agent, the output should always be uncompressed. In
|
||||
// other applications, it may be required to leave-compressed or not. How to
|
||||
// control? Seems like a simple mux - pass-through if no uncompression is
|
||||
// required.
|
||||
output source_is_compressed,
|
||||
output [BURST_SIZE_W-1 : 0] source_burstsize
|
||||
);
|
||||
|
||||
//----------------------------------------------------
|
||||
// AXSIZE decoding
|
||||
//
|
||||
// Turns the axsize value into the actual number of bytes
|
||||
// being transferred.
|
||||
// ---------------------------------------------------
|
||||
function reg[63:0] bytes_in_transfer;
|
||||
input [BURST_SIZE_W-1:0] axsize;
|
||||
case (axsize)
|
||||
4'b0000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
|
||||
4'b0001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010;
|
||||
4'b0010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100;
|
||||
4'b0011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000;
|
||||
4'b0100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000;
|
||||
4'b0101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000;
|
||||
4'b0110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000;
|
||||
4'b0111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000;
|
||||
4'b1000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000100000000;
|
||||
4'b1001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000001000000000;
|
||||
default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
|
||||
endcase
|
||||
|
||||
endfunction
|
||||
|
||||
// num_symbols is PKT_SYMBOLS, appropriately sized.
|
||||
wire [31:0] int_num_symbols = PKT_SYMBOLS;
|
||||
wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
|
||||
|
||||
// def: Burst Compression. In a merlin network, a compressed burst is one
|
||||
// which is transmitted in a single beat. Example: read burst. In
|
||||
// constrast, an uncompressed burst (example: write burst) is transmitted in
|
||||
// one beat per writedata item.
|
||||
//
|
||||
// For compressed bursts which require response packets, burst
|
||||
// uncompression is required. Concrete example: a read burst of size 8
|
||||
// occupies one response-fifo position. When that fifo position reaches the
|
||||
// front of the FIFO, the slave starts providing the required 8 readdatavalid
|
||||
// pulses. The 8 return response beats must be provided in a single packet,
|
||||
// with incrementing address and decrementing byte_cnt fields. Upon receipt
|
||||
// of the final readdata item of the burst, the response FIFO item is
|
||||
// retired.
|
||||
// Burst uncompression logic provides:
|
||||
// a) 2-state FSM (idle, busy)
|
||||
// reset to idle state
|
||||
// transition to busy state for 2nd and subsequent rdv pulses
|
||||
// - a single-cycle burst (aka non-burst read) causes no transition to
|
||||
// busy state.
|
||||
// b) response startofpacket/endofpacket logic. The response FIFO item
|
||||
// will have sop asserted, and may have eop asserted. (In the case of
|
||||
// multiple read bursts transmit in the command fabric in a single packet,
|
||||
// the eop assertion will come in a later FIFO item.) To support packet
|
||||
// conservation, and emit a well-formed packet on the response fabric,
|
||||
// i) response fabric startofpacket is asserted only for the first resp.
|
||||
// beat;
|
||||
// ii) response fabric endofpacket is asserted only for the last resp.
|
||||
// beat.
|
||||
// c) response address field. The response address field contains an
|
||||
// incrementing sequence, such that each readdata item is associated with
|
||||
// its slave-map location. N.b. a) computing the address correctly requires
|
||||
// knowledge of burstwrap behavior b) there may be no clients of the address
|
||||
// field, which makes this field a good target for optimization. See
|
||||
// burst_uncompress_address_counter below.
|
||||
// d) response byte_cnt field. The response byte_cnt field contains a
|
||||
// decrementing sequence, such that each beat of the response contains the
|
||||
// count of bytes to follow. In the case of sub-bursts in a single packet,
|
||||
// the byte_cnt field may decrement down to num_symbols, then back up to
|
||||
// some value, multiple times in the packet.
|
||||
|
||||
reg burst_uncompress_busy;
|
||||
reg [BYTE_CNT_W:0] burst_uncompress_byte_counter;
|
||||
wire [BYTE_CNT_W-1:0] burst_uncompress_byte_counter_lint;
|
||||
wire first_packet_beat;
|
||||
wire last_packet_beat;
|
||||
|
||||
assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
|
||||
assign burst_uncompress_byte_counter_lint = burst_uncompress_byte_counter[BYTE_CNT_W-1:0];
|
||||
|
||||
// First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to
|
||||
// the output.
|
||||
assign source_byte_cnt =
|
||||
first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter_lint;
|
||||
assign source_valid = sink_valid;
|
||||
|
||||
// Last packet beat is set throughout receipt of an uncompressed read burst
|
||||
// from the response FIFO - this forces all the burst uncompression machinery
|
||||
// idle.
|
||||
assign last_packet_beat = ~sink_is_compressed |
|
||||
(
|
||||
burst_uncompress_busy ?
|
||||
(sink_valid & (burst_uncompress_byte_counter_lint == num_symbols)) :
|
||||
sink_valid & (sink_byte_cnt == num_symbols)
|
||||
);
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
burst_uncompress_busy <= '0;
|
||||
burst_uncompress_byte_counter <= '0;
|
||||
end
|
||||
else begin
|
||||
if (source_valid & source_ready & sink_valid) begin
|
||||
// No matter what the current state, last_packet_beat leads to
|
||||
// idle.
|
||||
if (last_packet_beat) begin
|
||||
burst_uncompress_busy <= '0;
|
||||
burst_uncompress_byte_counter <= '0;
|
||||
end
|
||||
else begin
|
||||
if (burst_uncompress_busy) begin
|
||||
burst_uncompress_byte_counter <= (burst_uncompress_byte_counter > 0) ?
|
||||
(burst_uncompress_byte_counter_lint - num_symbols) :
|
||||
(sink_byte_cnt - num_symbols);
|
||||
end
|
||||
else begin // not busy, at least one more beat to go
|
||||
burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols;
|
||||
// To do: should busy go true for numsymbols-size compressed
|
||||
// bursts?
|
||||
burst_uncompress_busy <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
|
||||
reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
|
||||
|
||||
wire [63:0] decoded_burstsize_wire;
|
||||
wire [ADDR_W-1:0] decoded_burstsize;
|
||||
|
||||
|
||||
localparam ADD_BURSTWRAP_W = (ADDR_W > BURSTWRAP_W) ? ADDR_W : BURSTWRAP_W;
|
||||
wire [ADD_BURSTWRAP_W-1:0] addr_width_burstwrap;
|
||||
// The input burstwrap value can be used as a mask against address values,
|
||||
// but with one caveat: the address width may be (probably is) wider than
|
||||
// the burstwrap width. The spec says: extend the msb of the burstwrap
|
||||
// value out over the entire address width (but only if the address width
|
||||
// actually is wider than the burstwrap width; otherwise it's a 0-width or
|
||||
// negative range and concatenation multiplier).
|
||||
generate
|
||||
if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
|
||||
// Sign-extend, just wires:
|
||||
assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
|
||||
{(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
|
||||
assign addr_width_burstwrap[BURSTWRAP_W-1:0] = sink_burstwrap [BURSTWRAP_W-1:0];
|
||||
end
|
||||
else begin
|
||||
assign addr_width_burstwrap[BURSTWRAP_W-1 : 0] = sink_burstwrap;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
burst_uncompress_address_base <= '0;
|
||||
end
|
||||
else if (first_packet_beat & source_ready) begin
|
||||
burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
|
||||
end
|
||||
end
|
||||
|
||||
assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits
|
||||
assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed
|
||||
|
||||
wire [ADDR_W : 0] p1_burst_uncompress_address_offset =
|
||||
(
|
||||
(first_packet_beat ?
|
||||
sink_addr :
|
||||
burst_uncompress_address_offset) + decoded_burstsize
|
||||
) &
|
||||
addr_width_burstwrap[ADDR_W-1:0];
|
||||
wire [ADDR_W-1:0] p1_burst_uncompress_address_offset_lint = p1_burst_uncompress_address_offset [ADDR_W-1:0];
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
burst_uncompress_address_offset <= '0;
|
||||
end
|
||||
else begin
|
||||
if (source_ready & source_valid) begin
|
||||
burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
|
||||
// if (first_packet_beat) begin
|
||||
// burst_uncompress_address_offset <=
|
||||
// (sink_addr + num_symbols) & addr_width_burstwrap;
|
||||
// end
|
||||
// else begin
|
||||
// burst_uncompress_address_offset <=
|
||||
// (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap;
|
||||
// end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// On the first packet beat, send the input address out unchanged,
|
||||
// while values are computed/registered for 2nd and subsequent beats.
|
||||
assign source_addr = first_packet_beat ? sink_addr :
|
||||
burst_uncompress_address_base | burst_uncompress_address_offset;
|
||||
assign source_burstwrap = sink_burstwrap;
|
||||
assign source_burstsize = sink_burstsize;
|
||||
|
||||
//-------------------------------------------------------------------
|
||||
// A single (compressed) read burst will have sop/eop in the same beat.
|
||||
// A sequence of read sub-bursts emitted by a burst adapter in response to a
|
||||
// single read burst will have sop on the first sub-burst, eop on the last.
|
||||
// Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve
|
||||
// packet conservation.
|
||||
assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
|
||||
assign source_endofpacket = sink_endofpacket & last_packet_beat;
|
||||
assign sink_ready = source_valid & source_ready & last_packet_beat;
|
||||
|
||||
// This is correct for the slave agent usage, but won't always be true in the
|
||||
// width adapter. To do: add an "please uncompress" input, and use it to
|
||||
// pass-through or modify, and set source_is_compressed accordingly.
|
||||
assign source_is_compressed = 1'b0;
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -11,293 +11,293 @@
|
|||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2018/07/18 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// --------------------------------------
|
||||
// Merlin Master Agent
|
||||
//
|
||||
// Converts Avalon-MM transactions into
|
||||
// Merlin network packets.
|
||||
// --------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_master_agent
|
||||
#(
|
||||
// -------------------
|
||||
// Packet Format Parameters
|
||||
// -------------------
|
||||
parameter
|
||||
PKT_QOS_H = 109,
|
||||
PKT_QOS_L = 106,
|
||||
PKT_DATA_SIDEBAND_H = 105,
|
||||
PKT_DATA_SIDEBAND_L = 98,
|
||||
PKT_ADDR_SIDEBAND_H = 97,
|
||||
PKT_ADDR_SIDEBAND_L = 93,
|
||||
PKT_CACHE_H = 92,
|
||||
PKT_CACHE_L = 89,
|
||||
PKT_THREAD_ID_H = 88,
|
||||
PKT_THREAD_ID_L = 87,
|
||||
PKT_BEGIN_BURST = 81,
|
||||
PKT_PROTECTION_H = 80,
|
||||
PKT_PROTECTION_L = 80,
|
||||
PKT_BURSTWRAP_H = 79,
|
||||
PKT_BURSTWRAP_L = 77,
|
||||
PKT_BYTE_CNT_H = 76,
|
||||
PKT_BYTE_CNT_L = 74,
|
||||
PKT_ADDR_H = 73,
|
||||
PKT_ADDR_L = 42,
|
||||
PKT_BURST_SIZE_H = 86,
|
||||
PKT_BURST_SIZE_L = 84,
|
||||
PKT_BURST_TYPE_H = 94,
|
||||
PKT_BURST_TYPE_L = 93,
|
||||
PKT_TRANS_EXCLUSIVE = 83,
|
||||
PKT_TRANS_LOCK = 82,
|
||||
PKT_TRANS_COMPRESSED_READ = 41,
|
||||
PKT_TRANS_POSTED = 40,
|
||||
PKT_TRANS_WRITE = 39,
|
||||
PKT_TRANS_READ = 38,
|
||||
PKT_DATA_H = 37,
|
||||
PKT_DATA_L = 6,
|
||||
PKT_BYTEEN_H = 5,
|
||||
PKT_BYTEEN_L = 2,
|
||||
PKT_SRC_ID_H = 1,
|
||||
PKT_SRC_ID_L = 1,
|
||||
PKT_DEST_ID_H = 0,
|
||||
PKT_DEST_ID_L = 0,
|
||||
PKT_RESPONSE_STATUS_L = 110,
|
||||
PKT_RESPONSE_STATUS_H = 111,
|
||||
PKT_ORI_BURST_SIZE_L = 112,
|
||||
PKT_ORI_BURST_SIZE_H = 114,
|
||||
ST_DATA_W = 115,
|
||||
ST_CHANNEL_W = 1,
|
||||
|
||||
// -------------------
|
||||
// Agent Parameters
|
||||
// -------------------
|
||||
AV_BURSTCOUNT_W = 3,
|
||||
ID = 1,
|
||||
SUPPRESS_0_BYTEEN_RSP = 1,
|
||||
BURSTWRAP_VALUE = 4,
|
||||
CACHE_VALUE = 0,
|
||||
SECURE_ACCESS_BIT = 1,
|
||||
USE_READRESPONSE = 0,
|
||||
USE_WRITERESPONSE = 0,
|
||||
|
||||
// -------------------
|
||||
// Derived Parameters
|
||||
// -------------------
|
||||
PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
|
||||
PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
|
||||
PKT_PROTECTION_W = PKT_PROTECTION_H - PKT_PROTECTION_L + 1,
|
||||
PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1,
|
||||
PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1,
|
||||
PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
|
||||
PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1,
|
||||
PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1,
|
||||
PKT_BURST_SIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1
|
||||
) (
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// -------------------
|
||||
// Avalon-MM Anti-Master
|
||||
// -------------------
|
||||
input [PKT_ADDR_W-1 : 0] av_address,
|
||||
input av_write,
|
||||
input av_read,
|
||||
input [PKT_DATA_W-1 : 0] av_writedata,
|
||||
output reg [PKT_DATA_W-1 : 0] av_readdata,
|
||||
output reg av_waitrequest,
|
||||
output reg av_readdatavalid,
|
||||
input [PKT_BYTEEN_W-1 : 0] av_byteenable,
|
||||
input [AV_BURSTCOUNT_W-1 : 0] av_burstcount,
|
||||
input av_debugaccess,
|
||||
input av_lock,
|
||||
output reg [1 : 0] av_response,
|
||||
output reg av_writeresponsevalid,
|
||||
|
||||
// -------------------
|
||||
// Command Source
|
||||
// -------------------
|
||||
output reg cp_valid,
|
||||
output reg [ST_DATA_W-1 : 0] cp_data,
|
||||
output wire cp_startofpacket,
|
||||
output wire cp_endofpacket,
|
||||
input cp_ready,
|
||||
|
||||
// -------------------
|
||||
// Response Sink
|
||||
// -------------------
|
||||
input rp_valid,
|
||||
input [ST_DATA_W-1 : 0] rp_data,
|
||||
input [ST_CHANNEL_W-1 : 0] rp_channel,
|
||||
input rp_startofpacket,
|
||||
input rp_endofpacket,
|
||||
output reg rp_ready
|
||||
);
|
||||
// ------------------------------------------------------------
|
||||
// Utility Functions
|
||||
// ------------------------------------------------------------
|
||||
function integer clogb2;
|
||||
input [31 : 0] value;
|
||||
begin
|
||||
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
|
||||
value = value >> 1;
|
||||
clogb2 = clogb2 - 1;
|
||||
end
|
||||
endfunction // clogb2
|
||||
|
||||
localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1);
|
||||
localparam NUMSYMBOLS = PKT_BYTEEN_W;
|
||||
localparam BURSTING = (MAX_BURST > NUMSYMBOLS);
|
||||
localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS);
|
||||
localparam BURST_SIZE = clogb2(NUMSYMBOLS);
|
||||
|
||||
typedef enum bit [1 : 0]
|
||||
{
|
||||
FIXED = 2'b00,
|
||||
INCR = 2'b01,
|
||||
WRAP = 2'b10,
|
||||
OTHER_WRAP = 2'b11
|
||||
} MerlinBurstType;
|
||||
|
||||
// --------------------------------------
|
||||
// Potential optimization: compare in words to save bits?
|
||||
// --------------------------------------
|
||||
wire is_burst;
|
||||
assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS);
|
||||
|
||||
wire [31 : 0] burstwrap_value_int = BURSTWRAP_VALUE;
|
||||
wire [31 : 0] id_int = ID;
|
||||
wire [PKT_BURST_SIZE_W-1 : 0] burstsize_sig = BURST_SIZE[PKT_BURST_SIZE_W-1 : 0];
|
||||
wire [1 : 0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP;
|
||||
|
||||
// --------------------------------------
|
||||
// Address alignment
|
||||
//
|
||||
// The packet format requires that addresses be aligned to
|
||||
// the transaction size.
|
||||
// --------------------------------------
|
||||
wire [PKT_ADDR_W-1 : 0] av_address_aligned;
|
||||
generate
|
||||
if (NUMSYMBOLS > 1) begin
|
||||
assign av_address_aligned =
|
||||
{av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}};
|
||||
end
|
||||
else begin
|
||||
assign av_address_aligned = av_address;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------
|
||||
// Command & Response Construction
|
||||
// --------------------------------------
|
||||
always_comb begin
|
||||
cp_data = '0;
|
||||
|
||||
cp_data[PKT_PROTECTION_L] = av_debugaccess;
|
||||
cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // secure cache bit
|
||||
cp_data[PKT_PROTECTION_L+2] = 1'b0; // instruction/data cache bit
|
||||
cp_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L] = burstwrap_value_int[PKT_BURSTWRAP_W-1 : 0];
|
||||
cp_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = av_burstcount;
|
||||
cp_data[PKT_ADDR_H : PKT_ADDR_L] = av_address_aligned;
|
||||
cp_data[PKT_TRANS_EXCLUSIVE] = 1'b0;
|
||||
cp_data[PKT_TRANS_LOCK] = av_lock;
|
||||
cp_data[PKT_TRANS_COMPRESSED_READ] = av_read & is_burst;
|
||||
cp_data[PKT_TRANS_READ] = av_read;
|
||||
cp_data[PKT_TRANS_WRITE] = av_write;
|
||||
cp_data[PKT_TRANS_POSTED] = av_write & !USE_WRITERESPONSE;
|
||||
cp_data[PKT_DATA_H : PKT_DATA_L] = av_writedata;
|
||||
cp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] = av_byteenable;
|
||||
cp_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L] = burstsize_sig;
|
||||
cp_data[PKT_ORI_BURST_SIZE_H : PKT_ORI_BURST_SIZE_L] = burstsize_sig;
|
||||
cp_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L] = bursttype_value;
|
||||
cp_data[PKT_SRC_ID_H : PKT_SRC_ID_L] = id_int[PKT_SRC_ID_W-1 : 0];
|
||||
cp_data[PKT_THREAD_ID_H : PKT_THREAD_ID_L] = '0;
|
||||
cp_data[PKT_CACHE_H : PKT_CACHE_L] = CACHE_VALUE[3 : 0];
|
||||
cp_data[PKT_QOS_H : PKT_QOS_L] = '0;
|
||||
cp_data[PKT_ADDR_SIDEBAND_H : PKT_ADDR_SIDEBAND_L] = '0;
|
||||
cp_data[PKT_DATA_SIDEBAND_H : PKT_DATA_SIDEBAND_L] = '0;
|
||||
|
||||
av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L];
|
||||
if (USE_WRITERESPONSE || USE_READRESPONSE)
|
||||
av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L];
|
||||
else
|
||||
av_response = '0;
|
||||
end
|
||||
|
||||
// --------------------------------------
|
||||
// Command Control
|
||||
// --------------------------------------
|
||||
reg hold_waitrequest;
|
||||
|
||||
always @ (posedge clk, posedge reset) begin
|
||||
if (reset)
|
||||
hold_waitrequest <= 1'b1;
|
||||
else
|
||||
hold_waitrequest <= 1'b0;
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
cp_valid = 0;
|
||||
|
||||
if ((av_write || av_read) && ~hold_waitrequest)
|
||||
cp_valid = 1;
|
||||
end
|
||||
|
||||
generate if (BURSTING) begin
|
||||
reg sop_enable;
|
||||
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
sop_enable <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if (cp_valid && cp_ready) begin
|
||||
sop_enable <= 1'b0;
|
||||
if (cp_endofpacket)
|
||||
sop_enable <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign cp_startofpacket = sop_enable;
|
||||
assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS);
|
||||
|
||||
end
|
||||
else begin
|
||||
|
||||
assign cp_startofpacket = 1'b1;
|
||||
assign cp_endofpacket = 1'b1;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------
|
||||
// Backpressure & Readdatavalid
|
||||
// --------------------------------------
|
||||
always_comb begin
|
||||
rp_ready = 1;
|
||||
av_readdatavalid = 0;
|
||||
av_writeresponsevalid = 0;
|
||||
av_waitrequest = hold_waitrequest | !cp_ready;
|
||||
|
||||
if (USE_WRITERESPONSE && (rp_data[PKT_TRANS_WRITE] == 1))
|
||||
av_writeresponsevalid = rp_valid;
|
||||
else
|
||||
av_readdatavalid = rp_valid;
|
||||
|
||||
if (SUPPRESS_0_BYTEEN_RSP) begin
|
||||
if (rp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] == 0)
|
||||
av_readdatavalid = 0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2018/07/18 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// --------------------------------------
|
||||
// Merlin Master Agent
|
||||
//
|
||||
// Converts Avalon-MM transactions into
|
||||
// Merlin network packets.
|
||||
// --------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_master_agent
|
||||
#(
|
||||
// -------------------
|
||||
// Packet Format Parameters
|
||||
// -------------------
|
||||
parameter
|
||||
PKT_QOS_H = 109,
|
||||
PKT_QOS_L = 106,
|
||||
PKT_DATA_SIDEBAND_H = 105,
|
||||
PKT_DATA_SIDEBAND_L = 98,
|
||||
PKT_ADDR_SIDEBAND_H = 97,
|
||||
PKT_ADDR_SIDEBAND_L = 93,
|
||||
PKT_CACHE_H = 92,
|
||||
PKT_CACHE_L = 89,
|
||||
PKT_THREAD_ID_H = 88,
|
||||
PKT_THREAD_ID_L = 87,
|
||||
PKT_BEGIN_BURST = 81,
|
||||
PKT_PROTECTION_H = 80,
|
||||
PKT_PROTECTION_L = 80,
|
||||
PKT_BURSTWRAP_H = 79,
|
||||
PKT_BURSTWRAP_L = 77,
|
||||
PKT_BYTE_CNT_H = 76,
|
||||
PKT_BYTE_CNT_L = 74,
|
||||
PKT_ADDR_H = 73,
|
||||
PKT_ADDR_L = 42,
|
||||
PKT_BURST_SIZE_H = 86,
|
||||
PKT_BURST_SIZE_L = 84,
|
||||
PKT_BURST_TYPE_H = 94,
|
||||
PKT_BURST_TYPE_L = 93,
|
||||
PKT_TRANS_EXCLUSIVE = 83,
|
||||
PKT_TRANS_LOCK = 82,
|
||||
PKT_TRANS_COMPRESSED_READ = 41,
|
||||
PKT_TRANS_POSTED = 40,
|
||||
PKT_TRANS_WRITE = 39,
|
||||
PKT_TRANS_READ = 38,
|
||||
PKT_DATA_H = 37,
|
||||
PKT_DATA_L = 6,
|
||||
PKT_BYTEEN_H = 5,
|
||||
PKT_BYTEEN_L = 2,
|
||||
PKT_SRC_ID_H = 1,
|
||||
PKT_SRC_ID_L = 1,
|
||||
PKT_DEST_ID_H = 0,
|
||||
PKT_DEST_ID_L = 0,
|
||||
PKT_RESPONSE_STATUS_L = 110,
|
||||
PKT_RESPONSE_STATUS_H = 111,
|
||||
PKT_ORI_BURST_SIZE_L = 112,
|
||||
PKT_ORI_BURST_SIZE_H = 114,
|
||||
ST_DATA_W = 115,
|
||||
ST_CHANNEL_W = 1,
|
||||
|
||||
// -------------------
|
||||
// Agent Parameters
|
||||
// -------------------
|
||||
AV_BURSTCOUNT_W = 3,
|
||||
ID = 1,
|
||||
SUPPRESS_0_BYTEEN_RSP = 1,
|
||||
BURSTWRAP_VALUE = 4,
|
||||
CACHE_VALUE = 0,
|
||||
SECURE_ACCESS_BIT = 1,
|
||||
USE_READRESPONSE = 0,
|
||||
USE_WRITERESPONSE = 0,
|
||||
|
||||
// -------------------
|
||||
// Derived Parameters
|
||||
// -------------------
|
||||
PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
|
||||
PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
|
||||
PKT_PROTECTION_W = PKT_PROTECTION_H - PKT_PROTECTION_L + 1,
|
||||
PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1,
|
||||
PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1,
|
||||
PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
|
||||
PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1,
|
||||
PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1,
|
||||
PKT_BURST_SIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1
|
||||
) (
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// -------------------
|
||||
// Avalon-MM Anti-Master
|
||||
// -------------------
|
||||
input [PKT_ADDR_W-1 : 0] av_address,
|
||||
input av_write,
|
||||
input av_read,
|
||||
input [PKT_DATA_W-1 : 0] av_writedata,
|
||||
output reg [PKT_DATA_W-1 : 0] av_readdata,
|
||||
output reg av_waitrequest,
|
||||
output reg av_readdatavalid,
|
||||
input [PKT_BYTEEN_W-1 : 0] av_byteenable,
|
||||
input [AV_BURSTCOUNT_W-1 : 0] av_burstcount,
|
||||
input av_debugaccess,
|
||||
input av_lock,
|
||||
output reg [1 : 0] av_response,
|
||||
output reg av_writeresponsevalid,
|
||||
|
||||
// -------------------
|
||||
// Command Source
|
||||
// -------------------
|
||||
output reg cp_valid,
|
||||
output reg [ST_DATA_W-1 : 0] cp_data,
|
||||
output wire cp_startofpacket,
|
||||
output wire cp_endofpacket,
|
||||
input cp_ready,
|
||||
|
||||
// -------------------
|
||||
// Response Sink
|
||||
// -------------------
|
||||
input rp_valid,
|
||||
input [ST_DATA_W-1 : 0] rp_data,
|
||||
input [ST_CHANNEL_W-1 : 0] rp_channel,
|
||||
input rp_startofpacket,
|
||||
input rp_endofpacket,
|
||||
output reg rp_ready
|
||||
);
|
||||
// ------------------------------------------------------------
|
||||
// Utility Functions
|
||||
// ------------------------------------------------------------
|
||||
function integer clogb2;
|
||||
input [31 : 0] value;
|
||||
begin
|
||||
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
|
||||
value = value >> 1;
|
||||
clogb2 = clogb2 - 1;
|
||||
end
|
||||
endfunction // clogb2
|
||||
|
||||
localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1);
|
||||
localparam NUMSYMBOLS = PKT_BYTEEN_W;
|
||||
localparam BURSTING = (MAX_BURST > NUMSYMBOLS);
|
||||
localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS);
|
||||
localparam BURST_SIZE = clogb2(NUMSYMBOLS);
|
||||
|
||||
typedef enum bit [1 : 0]
|
||||
{
|
||||
FIXED = 2'b00,
|
||||
INCR = 2'b01,
|
||||
WRAP = 2'b10,
|
||||
OTHER_WRAP = 2'b11
|
||||
} MerlinBurstType;
|
||||
|
||||
// --------------------------------------
|
||||
// Potential optimization: compare in words to save bits?
|
||||
// --------------------------------------
|
||||
wire is_burst;
|
||||
assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS);
|
||||
|
||||
wire [31 : 0] burstwrap_value_int = BURSTWRAP_VALUE;
|
||||
wire [31 : 0] id_int = ID;
|
||||
wire [PKT_BURST_SIZE_W-1 : 0] burstsize_sig = BURST_SIZE[PKT_BURST_SIZE_W-1 : 0];
|
||||
wire [1 : 0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP;
|
||||
|
||||
// --------------------------------------
|
||||
// Address alignment
|
||||
//
|
||||
// The packet format requires that addresses be aligned to
|
||||
// the transaction size.
|
||||
// --------------------------------------
|
||||
wire [PKT_ADDR_W-1 : 0] av_address_aligned;
|
||||
generate
|
||||
if (NUMSYMBOLS > 1) begin
|
||||
assign av_address_aligned =
|
||||
{av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}};
|
||||
end
|
||||
else begin
|
||||
assign av_address_aligned = av_address;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------
|
||||
// Command & Response Construction
|
||||
// --------------------------------------
|
||||
always_comb begin
|
||||
cp_data = '0;
|
||||
|
||||
cp_data[PKT_PROTECTION_L] = av_debugaccess;
|
||||
cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // secure cache bit
|
||||
cp_data[PKT_PROTECTION_L+2] = 1'b0; // instruction/data cache bit
|
||||
cp_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L] = burstwrap_value_int[PKT_BURSTWRAP_W-1 : 0];
|
||||
cp_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = av_burstcount;
|
||||
cp_data[PKT_ADDR_H : PKT_ADDR_L] = av_address_aligned;
|
||||
cp_data[PKT_TRANS_EXCLUSIVE] = 1'b0;
|
||||
cp_data[PKT_TRANS_LOCK] = av_lock;
|
||||
cp_data[PKT_TRANS_COMPRESSED_READ] = av_read & is_burst;
|
||||
cp_data[PKT_TRANS_READ] = av_read;
|
||||
cp_data[PKT_TRANS_WRITE] = av_write;
|
||||
cp_data[PKT_TRANS_POSTED] = av_write & !USE_WRITERESPONSE;
|
||||
cp_data[PKT_DATA_H : PKT_DATA_L] = av_writedata;
|
||||
cp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] = av_byteenable;
|
||||
cp_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L] = burstsize_sig;
|
||||
cp_data[PKT_ORI_BURST_SIZE_H : PKT_ORI_BURST_SIZE_L] = burstsize_sig;
|
||||
cp_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L] = bursttype_value;
|
||||
cp_data[PKT_SRC_ID_H : PKT_SRC_ID_L] = id_int[PKT_SRC_ID_W-1 : 0];
|
||||
cp_data[PKT_THREAD_ID_H : PKT_THREAD_ID_L] = '0;
|
||||
cp_data[PKT_CACHE_H : PKT_CACHE_L] = CACHE_VALUE[3 : 0];
|
||||
cp_data[PKT_QOS_H : PKT_QOS_L] = '0;
|
||||
cp_data[PKT_ADDR_SIDEBAND_H : PKT_ADDR_SIDEBAND_L] = '0;
|
||||
cp_data[PKT_DATA_SIDEBAND_H : PKT_DATA_SIDEBAND_L] = '0;
|
||||
|
||||
av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L];
|
||||
if (USE_WRITERESPONSE || USE_READRESPONSE)
|
||||
av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L];
|
||||
else
|
||||
av_response = '0;
|
||||
end
|
||||
|
||||
// --------------------------------------
|
||||
// Command Control
|
||||
// --------------------------------------
|
||||
reg hold_waitrequest;
|
||||
|
||||
always @ (posedge clk, posedge reset) begin
|
||||
if (reset)
|
||||
hold_waitrequest <= 1'b1;
|
||||
else
|
||||
hold_waitrequest <= 1'b0;
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
cp_valid = 0;
|
||||
|
||||
if ((av_write || av_read) && ~hold_waitrequest)
|
||||
cp_valid = 1;
|
||||
end
|
||||
|
||||
generate if (BURSTING) begin
|
||||
reg sop_enable;
|
||||
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
sop_enable <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if (cp_valid && cp_ready) begin
|
||||
sop_enable <= 1'b0;
|
||||
if (cp_endofpacket)
|
||||
sop_enable <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign cp_startofpacket = sop_enable;
|
||||
assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS);
|
||||
|
||||
end
|
||||
else begin
|
||||
|
||||
assign cp_startofpacket = 1'b1;
|
||||
assign cp_endofpacket = 1'b1;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------
|
||||
// Backpressure & Readdatavalid
|
||||
// --------------------------------------
|
||||
always_comb begin
|
||||
rp_ready = 1;
|
||||
av_readdatavalid = 0;
|
||||
av_writeresponsevalid = 0;
|
||||
av_waitrequest = hold_waitrequest | !cp_ready;
|
||||
|
||||
if (USE_WRITERESPONSE && (rp_data[PKT_TRANS_WRITE] == 1))
|
||||
av_writeresponsevalid = rp_valid;
|
||||
else
|
||||
av_readdatavalid = rp_valid;
|
||||
|
||||
if (SUPPRESS_0_BYTEEN_RSP) begin
|
||||
if (rp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] == 0)
|
||||
av_readdatavalid = 0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -11,472 +11,472 @@
|
|||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2018/07/18 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// -------------------------------------
|
||||
// Merlin Slave Translator
|
||||
//
|
||||
// Translates Universal Avalon MM Slave
|
||||
// to any Avalon MM Slave
|
||||
// -------------------------------------
|
||||
//
|
||||
//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
|
||||
//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
|
||||
//The key feature here is that no same cycle turnaround data is processed through the fabric.
|
||||
|
||||
//import avalon_utilities_pkg::*;
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_slave_translator #(
|
||||
parameter
|
||||
//Widths
|
||||
AV_ADDRESS_W = 32,
|
||||
AV_DATA_W = 32,
|
||||
AV_BURSTCOUNT_W = 4,
|
||||
AV_BYTEENABLE_W = 4,
|
||||
UAV_BYTEENABLE_W = 4,
|
||||
|
||||
//Read Latency
|
||||
AV_READLATENCY = 1,
|
||||
|
||||
//Timing
|
||||
AV_READ_WAIT_CYCLES = 0,
|
||||
AV_WRITE_WAIT_CYCLES = 0,
|
||||
AV_SETUP_WAIT_CYCLES = 0,
|
||||
AV_DATA_HOLD_CYCLES = 0,
|
||||
|
||||
//Optional Port Declarations
|
||||
USE_READDATAVALID = 1,
|
||||
USE_WAITREQUEST = 1,
|
||||
USE_READRESPONSE = 0,
|
||||
USE_WRITERESPONSE = 0,
|
||||
|
||||
//Variable Addressing
|
||||
AV_SYMBOLS_PER_WORD = 4,
|
||||
AV_ADDRESS_SYMBOLS = 0,
|
||||
AV_BURSTCOUNT_SYMBOLS = 0,
|
||||
BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1),
|
||||
UAV_ADDRESS_W = 38,
|
||||
UAV_BURSTCOUNT_W = 10,
|
||||
UAV_DATA_W = 32,
|
||||
|
||||
AV_CONSTANT_BURST_BEHAVIOR = 0,
|
||||
UAV_CONSTANT_BURST_BEHAVIOR = 0,
|
||||
CHIPSELECT_THROUGH_READLATENCY = 0,
|
||||
|
||||
// Tightly-Coupled Options
|
||||
USE_UAV_CLKEN = 0,
|
||||
AV_REQUIRE_UNALIGNED_ADDRESSES = 0
|
||||
) (
|
||||
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
// -------------------
|
||||
// Universal Avalon Slave
|
||||
// -------------------
|
||||
|
||||
input wire [UAV_ADDRESS_W - 1 : 0] uav_address,
|
||||
input wire [UAV_DATA_W - 1 : 0] uav_writedata,
|
||||
input wire uav_write,
|
||||
input wire uav_read,
|
||||
input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount,
|
||||
input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable,
|
||||
input wire uav_lock,
|
||||
input wire uav_debugaccess,
|
||||
input wire uav_clken,
|
||||
|
||||
output logic uav_readdatavalid,
|
||||
output logic uav_waitrequest,
|
||||
output logic [UAV_DATA_W - 1 : 0] uav_readdata,
|
||||
output logic [1:0] uav_response,
|
||||
// input wire uav_writeresponserequest,
|
||||
output logic uav_writeresponsevalid,
|
||||
|
||||
// -------------------
|
||||
// Customizable Avalon Master
|
||||
// -------------------
|
||||
output logic [AV_ADDRESS_W - 1 : 0] av_address,
|
||||
output logic [AV_DATA_W - 1 : 0] av_writedata,
|
||||
output logic av_write,
|
||||
output logic av_read,
|
||||
output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
|
||||
output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable,
|
||||
output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
|
||||
output logic av_begintransfer,
|
||||
output wire av_chipselect,
|
||||
output logic av_beginbursttransfer,
|
||||
output logic av_lock,
|
||||
output wire av_clken,
|
||||
output wire av_debugaccess,
|
||||
output wire av_outputenable,
|
||||
|
||||
input logic [AV_DATA_W - 1 : 0] av_readdata,
|
||||
input logic av_readdatavalid,
|
||||
input logic av_waitrequest,
|
||||
|
||||
input logic [1:0] av_response,
|
||||
// output logic av_writeresponserequest,
|
||||
input wire av_writeresponsevalid
|
||||
|
||||
);
|
||||
|
||||
function integer clog2_plusone;
|
||||
input [31:0] Depth;
|
||||
integer i;
|
||||
begin
|
||||
i = Depth;
|
||||
for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1)
|
||||
i = i >> 1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer max;
|
||||
//returns the larger of two passed arguments
|
||||
input [31:0] one;
|
||||
input [31:0] two;
|
||||
if(one > two)
|
||||
max=one;
|
||||
else
|
||||
max=two;
|
||||
endfunction // int
|
||||
|
||||
localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
|
||||
localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
|
||||
localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
|
||||
localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1));
|
||||
localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
|
||||
localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
|
||||
localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
|
||||
AV_ADDRESS_W :
|
||||
UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
|
||||
localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
|
||||
AV_BURSTCOUNT_W :
|
||||
UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
|
||||
localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1;
|
||||
|
||||
|
||||
// Calculate the symbols per word as the power of 2 extended symbols per word
|
||||
wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
|
||||
wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0];
|
||||
|
||||
// +--------------------------------
|
||||
// |Backwards Compatibility Signals
|
||||
// +--------------------------------
|
||||
assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
|
||||
assign av_debugaccess = uav_debugaccess;
|
||||
|
||||
// +-------------------
|
||||
// |Passthru Signals
|
||||
// +-------------------
|
||||
|
||||
reg [1 : 0] av_response_delayed;
|
||||
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
av_response_delayed <= 2'b0;
|
||||
end else begin
|
||||
av_response_delayed <= av_response;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb
|
||||
begin
|
||||
if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin
|
||||
uav_response = '0;
|
||||
end else begin
|
||||
if (AV_READLATENCY != 0 || USE_READDATAVALID) begin
|
||||
uav_response = av_response;
|
||||
end else begin
|
||||
uav_response = av_response_delayed;
|
||||
end
|
||||
end
|
||||
end
|
||||
// assign av_writeresponserequest = uav_writeresponserequest;
|
||||
assign uav_writeresponsevalid = av_writeresponsevalid;
|
||||
|
||||
//-------------------------
|
||||
//Writedata and Byteenable
|
||||
//-------------------------
|
||||
|
||||
always@* begin
|
||||
av_byteenable = '0;
|
||||
av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
|
||||
end
|
||||
|
||||
always@* begin
|
||||
av_writedata = '0;
|
||||
av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
|
||||
end
|
||||
|
||||
// +-------------------
|
||||
// |Calculated Signals
|
||||
// +-------------------
|
||||
|
||||
logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
|
||||
|
||||
function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
|
||||
input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
|
||||
|
||||
for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
|
||||
if(byteenable[i] == 1) begin
|
||||
return i;
|
||||
end
|
||||
end
|
||||
|
||||
return '0;
|
||||
|
||||
endfunction
|
||||
|
||||
reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
|
||||
reg [AV_ADDRESS_W - 1 : 0] address_reg;
|
||||
always@(posedge clk, posedge reset) begin
|
||||
if(reset) begin
|
||||
burstcount_reg <= '0;
|
||||
address_reg <= '0;
|
||||
end else begin
|
||||
burstcount_reg <= burstcount_reg;
|
||||
address_reg <= address_reg;
|
||||
if(av_beginbursttransfer) begin
|
||||
burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
|
||||
address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
|
||||
|
||||
always@* begin
|
||||
if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
|
||||
temp_wire = decode_byteenable(uav_byteenable);
|
||||
real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
|
||||
end else begin
|
||||
real_uav_address = uav_address;
|
||||
end
|
||||
|
||||
av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
|
||||
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
|
||||
av_address = address_reg;
|
||||
end
|
||||
|
||||
always@* begin
|
||||
av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
|
||||
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
|
||||
av_burstcount = burstcount_reg;
|
||||
end
|
||||
|
||||
always@* begin
|
||||
av_lock = uav_lock;
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Writebyteenable Assignment
|
||||
// -------------------
|
||||
always@* begin
|
||||
av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Waitrequest Assignment
|
||||
// -------------------
|
||||
|
||||
reg av_waitrequest_generated;
|
||||
reg av_waitrequest_generated_read;
|
||||
reg av_waitrequest_generated_write;
|
||||
reg waitrequest_reset_override;
|
||||
reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
|
||||
|
||||
always@(posedge reset, posedge clk) begin
|
||||
if(reset) begin
|
||||
wait_latency_counter <= '0;
|
||||
waitrequest_reset_override <= 1'h1;
|
||||
end else begin
|
||||
waitrequest_reset_override <= 1'h0;
|
||||
wait_latency_counter <= '0;
|
||||
if( ~uav_waitrequest | waitrequest_reset_override )
|
||||
wait_latency_counter <= '0;
|
||||
else if( uav_read | uav_write )
|
||||
wait_latency_counter <= wait_latency_counter + 1'h1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @* begin
|
||||
|
||||
av_read = uav_read;
|
||||
av_write = uav_write;
|
||||
av_waitrequest_generated = 1'h1;
|
||||
av_waitrequest_generated_read = 1'h1;
|
||||
av_waitrequest_generated_write = 1'h1;
|
||||
|
||||
if(LOG2_OF_LATENCY_SUM == 1)
|
||||
av_waitrequest_generated = 0;
|
||||
|
||||
if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
|
||||
av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
|
||||
av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
|
||||
av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
|
||||
av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
|
||||
|
||||
if(uav_write)
|
||||
av_waitrequest_generated = av_waitrequest_generated_write;
|
||||
else
|
||||
av_waitrequest_generated = av_waitrequest_generated_read;
|
||||
|
||||
end
|
||||
|
||||
if(USE_WAITREQUEST) begin
|
||||
uav_waitrequest = av_waitrequest;
|
||||
end else begin
|
||||
uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// --------------
|
||||
// Readdata Assignment
|
||||
// --------------
|
||||
|
||||
reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
|
||||
|
||||
always@(posedge clk, posedge reset) begin
|
||||
if(reset)
|
||||
av_readdata_pre <= 'b0;
|
||||
else
|
||||
av_readdata_pre <= av_readdata;
|
||||
end
|
||||
|
||||
always@* begin
|
||||
uav_readdata = {UAV_DATA_W{1'b0}};
|
||||
if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin
|
||||
uav_readdata[AV_DATA_W-1:0] = av_readdata;
|
||||
end else begin
|
||||
uav_readdata[AV_DATA_W-1:0] = av_readdata_pre;
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Readdatavalid Assigment
|
||||
// -------------------
|
||||
reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
|
||||
reg top_read_latency_shift_reg;
|
||||
|
||||
always@* begin
|
||||
uav_readdatavalid=top_read_latency_shift_reg;
|
||||
if(USE_READDATAVALID) begin
|
||||
uav_readdatavalid = av_readdatavalid;
|
||||
end
|
||||
end
|
||||
|
||||
always@* begin
|
||||
top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
|
||||
if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
|
||||
top_read_latency_shift_reg=read_latency_shift_reg;
|
||||
end
|
||||
if (AV_READLATENCY > 1) begin
|
||||
top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge reset, posedge clk) begin
|
||||
if (reset) begin
|
||||
read_latency_shift_reg <= '0;
|
||||
end else if (av_clken) begin
|
||||
read_latency_shift_reg[0] <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override;
|
||||
for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
|
||||
read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ------------
|
||||
// Chipselect and OutputEnable
|
||||
// ------------
|
||||
reg av_chipselect_pre;
|
||||
wire cs_extension;
|
||||
reg av_outputenable_pre;
|
||||
|
||||
assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
|
||||
assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
|
||||
assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
|
||||
|
||||
always@(posedge reset, posedge clk) begin
|
||||
if(reset)
|
||||
av_outputenable_pre <= 1'b0;
|
||||
else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 )
|
||||
av_outputenable_pre <= 0;
|
||||
else
|
||||
av_outputenable_pre <= cs_extension | uav_read;
|
||||
end
|
||||
|
||||
always@(posedge reset, posedge clk) begin
|
||||
if(reset) begin
|
||||
av_chipselect_pre <= 1'b0;
|
||||
end else begin
|
||||
av_chipselect_pre <= 1'b0;
|
||||
if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
|
||||
//The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
|
||||
//There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
|
||||
if(uav_read) begin
|
||||
av_chipselect_pre <= 1'b1;
|
||||
end else if(cs_extension == 1) begin
|
||||
av_chipselect_pre <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Begintransfer Assigment
|
||||
// -------------------
|
||||
reg end_begintransfer;
|
||||
|
||||
always@* begin
|
||||
av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
|
||||
end
|
||||
|
||||
always@ ( posedge clk or posedge reset ) begin
|
||||
if(reset) begin
|
||||
end_begintransfer <= 1'b0;
|
||||
end else begin
|
||||
if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
|
||||
end_begintransfer <= 1'b1;
|
||||
else if(uav_waitrequest)
|
||||
end_begintransfer <= end_begintransfer;
|
||||
else
|
||||
end_begintransfer <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Beginbursttransfer Assigment
|
||||
// -------------------
|
||||
reg end_beginbursttransfer;
|
||||
reg in_transfer;
|
||||
|
||||
always@* begin
|
||||
av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
|
||||
end
|
||||
|
||||
always@ ( posedge clk or posedge reset ) begin
|
||||
if(reset) begin
|
||||
end_beginbursttransfer <= 1'b0;
|
||||
in_transfer <= 1'b0;
|
||||
end else begin
|
||||
end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
|
||||
if(uav_write && uav_burstcount == symbols_per_word)
|
||||
in_transfer <=1'b0;
|
||||
else if(uav_write)
|
||||
in_transfer <=1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2018/07/18 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// -------------------------------------
|
||||
// Merlin Slave Translator
|
||||
//
|
||||
// Translates Universal Avalon MM Slave
|
||||
// to any Avalon MM Slave
|
||||
// -------------------------------------
|
||||
//
|
||||
//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
|
||||
//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
|
||||
//The key feature here is that no same cycle turnaround data is processed through the fabric.
|
||||
|
||||
//import avalon_utilities_pkg::*;
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_slave_translator #(
|
||||
parameter
|
||||
//Widths
|
||||
AV_ADDRESS_W = 32,
|
||||
AV_DATA_W = 32,
|
||||
AV_BURSTCOUNT_W = 4,
|
||||
AV_BYTEENABLE_W = 4,
|
||||
UAV_BYTEENABLE_W = 4,
|
||||
|
||||
//Read Latency
|
||||
AV_READLATENCY = 1,
|
||||
|
||||
//Timing
|
||||
AV_READ_WAIT_CYCLES = 0,
|
||||
AV_WRITE_WAIT_CYCLES = 0,
|
||||
AV_SETUP_WAIT_CYCLES = 0,
|
||||
AV_DATA_HOLD_CYCLES = 0,
|
||||
|
||||
//Optional Port Declarations
|
||||
USE_READDATAVALID = 1,
|
||||
USE_WAITREQUEST = 1,
|
||||
USE_READRESPONSE = 0,
|
||||
USE_WRITERESPONSE = 0,
|
||||
|
||||
//Variable Addressing
|
||||
AV_SYMBOLS_PER_WORD = 4,
|
||||
AV_ADDRESS_SYMBOLS = 0,
|
||||
AV_BURSTCOUNT_SYMBOLS = 0,
|
||||
BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1),
|
||||
UAV_ADDRESS_W = 38,
|
||||
UAV_BURSTCOUNT_W = 10,
|
||||
UAV_DATA_W = 32,
|
||||
|
||||
AV_CONSTANT_BURST_BEHAVIOR = 0,
|
||||
UAV_CONSTANT_BURST_BEHAVIOR = 0,
|
||||
CHIPSELECT_THROUGH_READLATENCY = 0,
|
||||
|
||||
// Tightly-Coupled Options
|
||||
USE_UAV_CLKEN = 0,
|
||||
AV_REQUIRE_UNALIGNED_ADDRESSES = 0
|
||||
) (
|
||||
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
// -------------------
|
||||
// Universal Avalon Slave
|
||||
// -------------------
|
||||
|
||||
input wire [UAV_ADDRESS_W - 1 : 0] uav_address,
|
||||
input wire [UAV_DATA_W - 1 : 0] uav_writedata,
|
||||
input wire uav_write,
|
||||
input wire uav_read,
|
||||
input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount,
|
||||
input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable,
|
||||
input wire uav_lock,
|
||||
input wire uav_debugaccess,
|
||||
input wire uav_clken,
|
||||
|
||||
output logic uav_readdatavalid,
|
||||
output logic uav_waitrequest,
|
||||
output logic [UAV_DATA_W - 1 : 0] uav_readdata,
|
||||
output logic [1:0] uav_response,
|
||||
// input wire uav_writeresponserequest,
|
||||
output logic uav_writeresponsevalid,
|
||||
|
||||
// -------------------
|
||||
// Customizable Avalon Master
|
||||
// -------------------
|
||||
output logic [AV_ADDRESS_W - 1 : 0] av_address,
|
||||
output logic [AV_DATA_W - 1 : 0] av_writedata,
|
||||
output logic av_write,
|
||||
output logic av_read,
|
||||
output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
|
||||
output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable,
|
||||
output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
|
||||
output logic av_begintransfer,
|
||||
output wire av_chipselect,
|
||||
output logic av_beginbursttransfer,
|
||||
output logic av_lock,
|
||||
output wire av_clken,
|
||||
output wire av_debugaccess,
|
||||
output wire av_outputenable,
|
||||
|
||||
input logic [AV_DATA_W - 1 : 0] av_readdata,
|
||||
input logic av_readdatavalid,
|
||||
input logic av_waitrequest,
|
||||
|
||||
input logic [1:0] av_response,
|
||||
// output logic av_writeresponserequest,
|
||||
input wire av_writeresponsevalid
|
||||
|
||||
);
|
||||
|
||||
function integer clog2_plusone;
|
||||
input [31:0] Depth;
|
||||
integer i;
|
||||
begin
|
||||
i = Depth;
|
||||
for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1)
|
||||
i = i >> 1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer max;
|
||||
//returns the larger of two passed arguments
|
||||
input [31:0] one;
|
||||
input [31:0] two;
|
||||
if(one > two)
|
||||
max=one;
|
||||
else
|
||||
max=two;
|
||||
endfunction // int
|
||||
|
||||
localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
|
||||
localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
|
||||
localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
|
||||
localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1));
|
||||
localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
|
||||
localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
|
||||
localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
|
||||
AV_ADDRESS_W :
|
||||
UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
|
||||
localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
|
||||
AV_BURSTCOUNT_W :
|
||||
UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
|
||||
localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1;
|
||||
|
||||
|
||||
// Calculate the symbols per word as the power of 2 extended symbols per word
|
||||
wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
|
||||
wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0];
|
||||
|
||||
// +--------------------------------
|
||||
// |Backwards Compatibility Signals
|
||||
// +--------------------------------
|
||||
assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
|
||||
assign av_debugaccess = uav_debugaccess;
|
||||
|
||||
// +-------------------
|
||||
// |Passthru Signals
|
||||
// +-------------------
|
||||
|
||||
reg [1 : 0] av_response_delayed;
|
||||
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
av_response_delayed <= 2'b0;
|
||||
end else begin
|
||||
av_response_delayed <= av_response;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb
|
||||
begin
|
||||
if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin
|
||||
uav_response = '0;
|
||||
end else begin
|
||||
if (AV_READLATENCY != 0 || USE_READDATAVALID) begin
|
||||
uav_response = av_response;
|
||||
end else begin
|
||||
uav_response = av_response_delayed;
|
||||
end
|
||||
end
|
||||
end
|
||||
// assign av_writeresponserequest = uav_writeresponserequest;
|
||||
assign uav_writeresponsevalid = av_writeresponsevalid;
|
||||
|
||||
//-------------------------
|
||||
//Writedata and Byteenable
|
||||
//-------------------------
|
||||
|
||||
always@* begin
|
||||
av_byteenable = '0;
|
||||
av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
|
||||
end
|
||||
|
||||
always@* begin
|
||||
av_writedata = '0;
|
||||
av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
|
||||
end
|
||||
|
||||
// +-------------------
|
||||
// |Calculated Signals
|
||||
// +-------------------
|
||||
|
||||
logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
|
||||
|
||||
function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
|
||||
input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
|
||||
|
||||
for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
|
||||
if(byteenable[i] == 1) begin
|
||||
return i;
|
||||
end
|
||||
end
|
||||
|
||||
return '0;
|
||||
|
||||
endfunction
|
||||
|
||||
reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
|
||||
reg [AV_ADDRESS_W - 1 : 0] address_reg;
|
||||
always@(posedge clk, posedge reset) begin
|
||||
if(reset) begin
|
||||
burstcount_reg <= '0;
|
||||
address_reg <= '0;
|
||||
end else begin
|
||||
burstcount_reg <= burstcount_reg;
|
||||
address_reg <= address_reg;
|
||||
if(av_beginbursttransfer) begin
|
||||
burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
|
||||
address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
|
||||
|
||||
always@* begin
|
||||
if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
|
||||
temp_wire = decode_byteenable(uav_byteenable);
|
||||
real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
|
||||
end else begin
|
||||
real_uav_address = uav_address;
|
||||
end
|
||||
|
||||
av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
|
||||
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
|
||||
av_address = address_reg;
|
||||
end
|
||||
|
||||
always@* begin
|
||||
av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
|
||||
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
|
||||
av_burstcount = burstcount_reg;
|
||||
end
|
||||
|
||||
always@* begin
|
||||
av_lock = uav_lock;
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Writebyteenable Assignment
|
||||
// -------------------
|
||||
always@* begin
|
||||
av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Waitrequest Assignment
|
||||
// -------------------
|
||||
|
||||
reg av_waitrequest_generated;
|
||||
reg av_waitrequest_generated_read;
|
||||
reg av_waitrequest_generated_write;
|
||||
reg waitrequest_reset_override;
|
||||
reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
|
||||
|
||||
always@(posedge reset, posedge clk) begin
|
||||
if(reset) begin
|
||||
wait_latency_counter <= '0;
|
||||
waitrequest_reset_override <= 1'h1;
|
||||
end else begin
|
||||
waitrequest_reset_override <= 1'h0;
|
||||
wait_latency_counter <= '0;
|
||||
if( ~uav_waitrequest | waitrequest_reset_override )
|
||||
wait_latency_counter <= '0;
|
||||
else if( uav_read | uav_write )
|
||||
wait_latency_counter <= wait_latency_counter + 1'h1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @* begin
|
||||
|
||||
av_read = uav_read;
|
||||
av_write = uav_write;
|
||||
av_waitrequest_generated = 1'h1;
|
||||
av_waitrequest_generated_read = 1'h1;
|
||||
av_waitrequest_generated_write = 1'h1;
|
||||
|
||||
if(LOG2_OF_LATENCY_SUM == 1)
|
||||
av_waitrequest_generated = 0;
|
||||
|
||||
if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
|
||||
av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
|
||||
av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
|
||||
av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
|
||||
av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
|
||||
|
||||
if(uav_write)
|
||||
av_waitrequest_generated = av_waitrequest_generated_write;
|
||||
else
|
||||
av_waitrequest_generated = av_waitrequest_generated_read;
|
||||
|
||||
end
|
||||
|
||||
if(USE_WAITREQUEST) begin
|
||||
uav_waitrequest = av_waitrequest;
|
||||
end else begin
|
||||
uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// --------------
|
||||
// Readdata Assignment
|
||||
// --------------
|
||||
|
||||
reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
|
||||
|
||||
always@(posedge clk, posedge reset) begin
|
||||
if(reset)
|
||||
av_readdata_pre <= 'b0;
|
||||
else
|
||||
av_readdata_pre <= av_readdata;
|
||||
end
|
||||
|
||||
always@* begin
|
||||
uav_readdata = {UAV_DATA_W{1'b0}};
|
||||
if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin
|
||||
uav_readdata[AV_DATA_W-1:0] = av_readdata;
|
||||
end else begin
|
||||
uav_readdata[AV_DATA_W-1:0] = av_readdata_pre;
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Readdatavalid Assigment
|
||||
// -------------------
|
||||
reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
|
||||
reg top_read_latency_shift_reg;
|
||||
|
||||
always@* begin
|
||||
uav_readdatavalid=top_read_latency_shift_reg;
|
||||
if(USE_READDATAVALID) begin
|
||||
uav_readdatavalid = av_readdatavalid;
|
||||
end
|
||||
end
|
||||
|
||||
always@* begin
|
||||
top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
|
||||
if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
|
||||
top_read_latency_shift_reg=read_latency_shift_reg;
|
||||
end
|
||||
if (AV_READLATENCY > 1) begin
|
||||
top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge reset, posedge clk) begin
|
||||
if (reset) begin
|
||||
read_latency_shift_reg <= '0;
|
||||
end else if (av_clken) begin
|
||||
read_latency_shift_reg[0] <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override;
|
||||
for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
|
||||
read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ------------
|
||||
// Chipselect and OutputEnable
|
||||
// ------------
|
||||
reg av_chipselect_pre;
|
||||
wire cs_extension;
|
||||
reg av_outputenable_pre;
|
||||
|
||||
assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
|
||||
assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
|
||||
assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
|
||||
|
||||
always@(posedge reset, posedge clk) begin
|
||||
if(reset)
|
||||
av_outputenable_pre <= 1'b0;
|
||||
else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 )
|
||||
av_outputenable_pre <= 0;
|
||||
else
|
||||
av_outputenable_pre <= cs_extension | uav_read;
|
||||
end
|
||||
|
||||
always@(posedge reset, posedge clk) begin
|
||||
if(reset) begin
|
||||
av_chipselect_pre <= 1'b0;
|
||||
end else begin
|
||||
av_chipselect_pre <= 1'b0;
|
||||
if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
|
||||
//The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
|
||||
//There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
|
||||
if(uav_read) begin
|
||||
av_chipselect_pre <= 1'b1;
|
||||
end else if(cs_extension == 1) begin
|
||||
av_chipselect_pre <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Begintransfer Assigment
|
||||
// -------------------
|
||||
reg end_begintransfer;
|
||||
|
||||
always@* begin
|
||||
av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
|
||||
end
|
||||
|
||||
always@ ( posedge clk or posedge reset ) begin
|
||||
if(reset) begin
|
||||
end_begintransfer <= 1'b0;
|
||||
end else begin
|
||||
if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
|
||||
end_begintransfer <= 1'b1;
|
||||
else if(uav_waitrequest)
|
||||
end_begintransfer <= end_begintransfer;
|
||||
else
|
||||
end_begintransfer <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Beginbursttransfer Assigment
|
||||
// -------------------
|
||||
reg end_beginbursttransfer;
|
||||
reg in_transfer;
|
||||
|
||||
always@* begin
|
||||
av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
|
||||
end
|
||||
|
||||
always@ ( posedge clk or posedge reset ) begin
|
||||
if(reset) begin
|
||||
end_beginbursttransfer <= 1'b0;
|
||||
in_transfer <= 1'b0;
|
||||
end else begin
|
||||
end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
|
||||
if(uav_write && uav_burstcount == symbols_per_word)
|
||||
in_transfer <=1'b0;
|
||||
else if(uav_write)
|
||||
in_transfer <=1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -11,20 +11,20 @@
|
|||
# agreement for further details.
|
||||
|
||||
|
||||
# +---------------------------------------------------
|
||||
# | Cut the async clear paths
|
||||
# +---------------------------------------------------
|
||||
set aclr_counter 0
|
||||
set clrn_counter 0
|
||||
set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
|
||||
set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
|
||||
set aclr_counter [get_collection_size $aclr_collection]
|
||||
set clrn_counter [get_collection_size $clrn_collection]
|
||||
|
||||
if {$aclr_counter > 0} {
|
||||
set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
|
||||
}
|
||||
|
||||
if {$clrn_counter > 0} {
|
||||
set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
|
||||
}
|
||||
# +---------------------------------------------------
|
||||
# | Cut the async clear paths
|
||||
# +---------------------------------------------------
|
||||
set aclr_counter 0
|
||||
set clrn_counter 0
|
||||
set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
|
||||
set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
|
||||
set aclr_counter [get_collection_size $aclr_collection]
|
||||
set clrn_counter [get_collection_size $clrn_collection]
|
||||
|
||||
if {$aclr_counter > 0} {
|
||||
set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
|
||||
}
|
||||
|
||||
if {$clrn_counter > 0} {
|
||||
set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,309 +11,309 @@
|
|||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2018/07/18 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// --------------------------------------
|
||||
// Reset controller
|
||||
//
|
||||
// Combines all the input resets and synchronizes
|
||||
// the result to the clk.
|
||||
// ACDS13.1 - Added reset request as part of reset sequencing
|
||||
// --------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_controller
|
||||
#(
|
||||
parameter NUM_RESET_INPUTS = 6,
|
||||
parameter USE_RESET_REQUEST_IN0 = 0,
|
||||
parameter USE_RESET_REQUEST_IN1 = 0,
|
||||
parameter USE_RESET_REQUEST_IN2 = 0,
|
||||
parameter USE_RESET_REQUEST_IN3 = 0,
|
||||
parameter USE_RESET_REQUEST_IN4 = 0,
|
||||
parameter USE_RESET_REQUEST_IN5 = 0,
|
||||
parameter USE_RESET_REQUEST_IN6 = 0,
|
||||
parameter USE_RESET_REQUEST_IN7 = 0,
|
||||
parameter USE_RESET_REQUEST_IN8 = 0,
|
||||
parameter USE_RESET_REQUEST_IN9 = 0,
|
||||
parameter USE_RESET_REQUEST_IN10 = 0,
|
||||
parameter USE_RESET_REQUEST_IN11 = 0,
|
||||
parameter USE_RESET_REQUEST_IN12 = 0,
|
||||
parameter USE_RESET_REQUEST_IN13 = 0,
|
||||
parameter USE_RESET_REQUEST_IN14 = 0,
|
||||
parameter USE_RESET_REQUEST_IN15 = 0,
|
||||
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
|
||||
parameter SYNC_DEPTH = 2,
|
||||
parameter RESET_REQUEST_PRESENT = 0,
|
||||
parameter RESET_REQ_WAIT_TIME = 3,
|
||||
parameter MIN_RST_ASSERTION_TIME = 11,
|
||||
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
|
||||
parameter ADAPT_RESET_REQUEST = 0
|
||||
)
|
||||
(
|
||||
// --------------------------------------
|
||||
// We support up to 16 reset inputs, for now
|
||||
// --------------------------------------
|
||||
input reset_in0,
|
||||
input reset_in1,
|
||||
input reset_in2,
|
||||
input reset_in3,
|
||||
input reset_in4,
|
||||
input reset_in5,
|
||||
input reset_in6,
|
||||
input reset_in7,
|
||||
input reset_in8,
|
||||
input reset_in9,
|
||||
input reset_in10,
|
||||
input reset_in11,
|
||||
input reset_in12,
|
||||
input reset_in13,
|
||||
input reset_in14,
|
||||
input reset_in15,
|
||||
input reset_req_in0,
|
||||
input reset_req_in1,
|
||||
input reset_req_in2,
|
||||
input reset_req_in3,
|
||||
input reset_req_in4,
|
||||
input reset_req_in5,
|
||||
input reset_req_in6,
|
||||
input reset_req_in7,
|
||||
input reset_req_in8,
|
||||
input reset_req_in9,
|
||||
input reset_req_in10,
|
||||
input reset_req_in11,
|
||||
input reset_req_in12,
|
||||
input reset_req_in13,
|
||||
input reset_req_in14,
|
||||
input reset_req_in15,
|
||||
|
||||
|
||||
input clk,
|
||||
output reg reset_out,
|
||||
output reg reset_req
|
||||
);
|
||||
|
||||
// Always use async reset synchronizer if reset_req is used
|
||||
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
|
||||
|
||||
// --------------------------------------
|
||||
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
|
||||
// --------------------------------------
|
||||
localparam MIN_METASTABLE = 3;
|
||||
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
|
||||
|
||||
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
|
||||
|
||||
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
|
||||
MIN_RST_ASSERTION_TIME + 1 :
|
||||
(
|
||||
(MIN_RST_ASSERTION_TIME > LARGER)?
|
||||
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
|
||||
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
|
||||
);
|
||||
|
||||
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
|
||||
// --------------------------------------
|
||||
|
||||
wire merged_reset;
|
||||
wire merged_reset_req_in;
|
||||
wire reset_out_pre;
|
||||
wire reset_req_pre;
|
||||
|
||||
// Registers and Interconnect
|
||||
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
|
||||
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
|
||||
reg r_sync_rst;
|
||||
reg r_early_rst;
|
||||
|
||||
// --------------------------------------
|
||||
// "Or" all the input resets together
|
||||
// --------------------------------------
|
||||
assign merged_reset = (
|
||||
reset_in0 |
|
||||
reset_in1 |
|
||||
reset_in2 |
|
||||
reset_in3 |
|
||||
reset_in4 |
|
||||
reset_in5 |
|
||||
reset_in6 |
|
||||
reset_in7 |
|
||||
reset_in8 |
|
||||
reset_in9 |
|
||||
reset_in10 |
|
||||
reset_in11 |
|
||||
reset_in12 |
|
||||
reset_in13 |
|
||||
reset_in14 |
|
||||
reset_in15
|
||||
);
|
||||
|
||||
assign merged_reset_req_in = (
|
||||
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
|
||||
);
|
||||
|
||||
|
||||
// --------------------------------------
|
||||
// And if required, synchronize it to the required clock domain,
|
||||
// with the correct synchronization type
|
||||
// --------------------------------------
|
||||
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
|
||||
|
||||
assign reset_out_pre = merged_reset;
|
||||
assign reset_req_pre = merged_reset_req_in;
|
||||
|
||||
end else begin
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH),
|
||||
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
|
||||
)
|
||||
alt_rst_sync_uq1
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (merged_reset),
|
||||
.reset_out (reset_out_pre)
|
||||
);
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH),
|
||||
.ASYNC_RESET(0)
|
||||
)
|
||||
alt_rst_req_sync_uq1
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (merged_reset_req_in),
|
||||
.reset_out (reset_req_pre)
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
|
||||
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
|
||||
always @* begin
|
||||
reset_out = reset_out_pre;
|
||||
reset_req = reset_req_pre;
|
||||
end
|
||||
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
|
||||
|
||||
wire reset_out_pre2;
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH+1),
|
||||
.ASYNC_RESET(0)
|
||||
)
|
||||
alt_rst_sync_uq2
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (reset_out_pre),
|
||||
.reset_out (reset_out_pre2)
|
||||
);
|
||||
|
||||
always @* begin
|
||||
reset_out = reset_out_pre2;
|
||||
reset_req = reset_req_pre;
|
||||
end
|
||||
|
||||
end
|
||||
else begin
|
||||
|
||||
// 3-FF Metastability Synchronizer
|
||||
initial
|
||||
begin
|
||||
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
|
||||
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
|
||||
end
|
||||
|
||||
// Synchronous reset pipe
|
||||
initial
|
||||
begin
|
||||
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
|
||||
begin
|
||||
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
|
||||
end
|
||||
else
|
||||
begin
|
||||
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
|
||||
end
|
||||
end
|
||||
|
||||
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
|
||||
// matches the early input.
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
|
||||
3'b000: r_sync_rst <= 1'b0; // Not reset
|
||||
3'b001: r_sync_rst <= 1'b0;
|
||||
3'b010: r_sync_rst <= 1'b0;
|
||||
3'b011: r_sync_rst <= 1'b1;
|
||||
3'b100: r_sync_rst <= 1'b1;
|
||||
3'b101: r_sync_rst <= 1'b1;
|
||||
3'b110: r_sync_rst <= 1'b1;
|
||||
3'b111: r_sync_rst <= 1'b1; // In Reset
|
||||
default: r_sync_rst <= 1'b1;
|
||||
endcase
|
||||
|
||||
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
|
||||
2'b00: r_early_rst <= 1'b0; // Not reset
|
||||
2'b01: r_early_rst <= 1'b1; // Coming out of reset
|
||||
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
|
||||
2'b11: r_early_rst <= 1'b1; // Held in reset
|
||||
default: r_early_rst <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @* begin
|
||||
reset_out = r_sync_rst;
|
||||
reset_req = r_early_rst;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2018/07/18 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// --------------------------------------
|
||||
// Reset controller
|
||||
//
|
||||
// Combines all the input resets and synchronizes
|
||||
// the result to the clk.
|
||||
// ACDS13.1 - Added reset request as part of reset sequencing
|
||||
// --------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_controller
|
||||
#(
|
||||
parameter NUM_RESET_INPUTS = 6,
|
||||
parameter USE_RESET_REQUEST_IN0 = 0,
|
||||
parameter USE_RESET_REQUEST_IN1 = 0,
|
||||
parameter USE_RESET_REQUEST_IN2 = 0,
|
||||
parameter USE_RESET_REQUEST_IN3 = 0,
|
||||
parameter USE_RESET_REQUEST_IN4 = 0,
|
||||
parameter USE_RESET_REQUEST_IN5 = 0,
|
||||
parameter USE_RESET_REQUEST_IN6 = 0,
|
||||
parameter USE_RESET_REQUEST_IN7 = 0,
|
||||
parameter USE_RESET_REQUEST_IN8 = 0,
|
||||
parameter USE_RESET_REQUEST_IN9 = 0,
|
||||
parameter USE_RESET_REQUEST_IN10 = 0,
|
||||
parameter USE_RESET_REQUEST_IN11 = 0,
|
||||
parameter USE_RESET_REQUEST_IN12 = 0,
|
||||
parameter USE_RESET_REQUEST_IN13 = 0,
|
||||
parameter USE_RESET_REQUEST_IN14 = 0,
|
||||
parameter USE_RESET_REQUEST_IN15 = 0,
|
||||
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
|
||||
parameter SYNC_DEPTH = 2,
|
||||
parameter RESET_REQUEST_PRESENT = 0,
|
||||
parameter RESET_REQ_WAIT_TIME = 3,
|
||||
parameter MIN_RST_ASSERTION_TIME = 11,
|
||||
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
|
||||
parameter ADAPT_RESET_REQUEST = 0
|
||||
)
|
||||
(
|
||||
// --------------------------------------
|
||||
// We support up to 16 reset inputs, for now
|
||||
// --------------------------------------
|
||||
input reset_in0,
|
||||
input reset_in1,
|
||||
input reset_in2,
|
||||
input reset_in3,
|
||||
input reset_in4,
|
||||
input reset_in5,
|
||||
input reset_in6,
|
||||
input reset_in7,
|
||||
input reset_in8,
|
||||
input reset_in9,
|
||||
input reset_in10,
|
||||
input reset_in11,
|
||||
input reset_in12,
|
||||
input reset_in13,
|
||||
input reset_in14,
|
||||
input reset_in15,
|
||||
input reset_req_in0,
|
||||
input reset_req_in1,
|
||||
input reset_req_in2,
|
||||
input reset_req_in3,
|
||||
input reset_req_in4,
|
||||
input reset_req_in5,
|
||||
input reset_req_in6,
|
||||
input reset_req_in7,
|
||||
input reset_req_in8,
|
||||
input reset_req_in9,
|
||||
input reset_req_in10,
|
||||
input reset_req_in11,
|
||||
input reset_req_in12,
|
||||
input reset_req_in13,
|
||||
input reset_req_in14,
|
||||
input reset_req_in15,
|
||||
|
||||
|
||||
input clk,
|
||||
output reg reset_out,
|
||||
output reg reset_req
|
||||
);
|
||||
|
||||
// Always use async reset synchronizer if reset_req is used
|
||||
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
|
||||
|
||||
// --------------------------------------
|
||||
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
|
||||
// --------------------------------------
|
||||
localparam MIN_METASTABLE = 3;
|
||||
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
|
||||
|
||||
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
|
||||
|
||||
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
|
||||
MIN_RST_ASSERTION_TIME + 1 :
|
||||
(
|
||||
(MIN_RST_ASSERTION_TIME > LARGER)?
|
||||
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
|
||||
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
|
||||
);
|
||||
|
||||
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
|
||||
// --------------------------------------
|
||||
|
||||
wire merged_reset;
|
||||
wire merged_reset_req_in;
|
||||
wire reset_out_pre;
|
||||
wire reset_req_pre;
|
||||
|
||||
// Registers and Interconnect
|
||||
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
|
||||
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
|
||||
reg r_sync_rst;
|
||||
reg r_early_rst;
|
||||
|
||||
// --------------------------------------
|
||||
// "Or" all the input resets together
|
||||
// --------------------------------------
|
||||
assign merged_reset = (
|
||||
reset_in0 |
|
||||
reset_in1 |
|
||||
reset_in2 |
|
||||
reset_in3 |
|
||||
reset_in4 |
|
||||
reset_in5 |
|
||||
reset_in6 |
|
||||
reset_in7 |
|
||||
reset_in8 |
|
||||
reset_in9 |
|
||||
reset_in10 |
|
||||
reset_in11 |
|
||||
reset_in12 |
|
||||
reset_in13 |
|
||||
reset_in14 |
|
||||
reset_in15
|
||||
);
|
||||
|
||||
assign merged_reset_req_in = (
|
||||
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
|
||||
);
|
||||
|
||||
|
||||
// --------------------------------------
|
||||
// And if required, synchronize it to the required clock domain,
|
||||
// with the correct synchronization type
|
||||
// --------------------------------------
|
||||
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
|
||||
|
||||
assign reset_out_pre = merged_reset;
|
||||
assign reset_req_pre = merged_reset_req_in;
|
||||
|
||||
end else begin
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH),
|
||||
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
|
||||
)
|
||||
alt_rst_sync_uq1
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (merged_reset),
|
||||
.reset_out (reset_out_pre)
|
||||
);
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH),
|
||||
.ASYNC_RESET(0)
|
||||
)
|
||||
alt_rst_req_sync_uq1
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (merged_reset_req_in),
|
||||
.reset_out (reset_req_pre)
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
|
||||
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
|
||||
always @* begin
|
||||
reset_out = reset_out_pre;
|
||||
reset_req = reset_req_pre;
|
||||
end
|
||||
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
|
||||
|
||||
wire reset_out_pre2;
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH+1),
|
||||
.ASYNC_RESET(0)
|
||||
)
|
||||
alt_rst_sync_uq2
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (reset_out_pre),
|
||||
.reset_out (reset_out_pre2)
|
||||
);
|
||||
|
||||
always @* begin
|
||||
reset_out = reset_out_pre2;
|
||||
reset_req = reset_req_pre;
|
||||
end
|
||||
|
||||
end
|
||||
else begin
|
||||
|
||||
// 3-FF Metastability Synchronizer
|
||||
initial
|
||||
begin
|
||||
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
|
||||
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
|
||||
end
|
||||
|
||||
// Synchronous reset pipe
|
||||
initial
|
||||
begin
|
||||
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
|
||||
begin
|
||||
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
|
||||
end
|
||||
else
|
||||
begin
|
||||
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
|
||||
end
|
||||
end
|
||||
|
||||
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
|
||||
// matches the early input.
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
|
||||
3'b000: r_sync_rst <= 1'b0; // Not reset
|
||||
3'b001: r_sync_rst <= 1'b0;
|
||||
3'b010: r_sync_rst <= 1'b0;
|
||||
3'b011: r_sync_rst <= 1'b1;
|
||||
3'b100: r_sync_rst <= 1'b1;
|
||||
3'b101: r_sync_rst <= 1'b1;
|
||||
3'b110: r_sync_rst <= 1'b1;
|
||||
3'b111: r_sync_rst <= 1'b1; // In Reset
|
||||
default: r_sync_rst <= 1'b1;
|
||||
endcase
|
||||
|
||||
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
|
||||
2'b00: r_early_rst <= 1'b0; // Not reset
|
||||
2'b01: r_early_rst <= 1'b1; // Coming out of reset
|
||||
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
|
||||
2'b11: r_early_rst <= 1'b1; // Held in reset
|
||||
default: r_early_rst <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @* begin
|
||||
reset_out = r_sync_rst;
|
||||
reset_req = r_early_rst;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -11,77 +11,77 @@
|
|||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2018/07/18 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// -----------------------------------------------
|
||||
// Reset Synchronizer
|
||||
// -----------------------------------------------
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_synchronizer
|
||||
#(
|
||||
parameter ASYNC_RESET = 1,
|
||||
parameter DEPTH = 2
|
||||
)
|
||||
(
|
||||
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
|
||||
|
||||
input clk,
|
||||
output reset_out
|
||||
);
|
||||
|
||||
// -----------------------------------------------
|
||||
// Synchronizer register chain. We cannot reuse the
|
||||
// standard synchronizer in this implementation
|
||||
// because our timing constraints are different.
|
||||
//
|
||||
// Instead of cutting the timing path to the d-input
|
||||
// on the first flop we need to cut the aclr input.
|
||||
//
|
||||
// We omit the "preserve" attribute on the final
|
||||
// output register, so that the synthesis tool can
|
||||
// duplicate it where needed.
|
||||
// -----------------------------------------------
|
||||
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
|
||||
reg altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
generate if (ASYNC_RESET) begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert asynchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk or posedge reset_in) begin
|
||||
if (reset_in) begin
|
||||
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
|
||||
altera_reset_synchronizer_int_chain_out <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end else begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert synchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk) begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2018/07/18 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// -----------------------------------------------
|
||||
// Reset Synchronizer
|
||||
// -----------------------------------------------
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_synchronizer
|
||||
#(
|
||||
parameter ASYNC_RESET = 1,
|
||||
parameter DEPTH = 2
|
||||
)
|
||||
(
|
||||
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
|
||||
|
||||
input clk,
|
||||
output reset_out
|
||||
);
|
||||
|
||||
// -----------------------------------------------
|
||||
// Synchronizer register chain. We cannot reuse the
|
||||
// standard synchronizer in this implementation
|
||||
// because our timing constraints are different.
|
||||
//
|
||||
// Instead of cutting the timing path to the d-input
|
||||
// on the first flop we need to cut the aclr input.
|
||||
//
|
||||
// We omit the "preserve" attribute on the final
|
||||
// output register, so that the synthesis tool can
|
||||
// duplicate it where needed.
|
||||
// -----------------------------------------------
|
||||
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
|
||||
reg altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
generate if (ASYNC_RESET) begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert asynchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk or posedge reset_in) begin
|
||||
if (reset_in) begin
|
||||
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
|
||||
altera_reset_synchronizer_int_chain_out <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end else begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert synchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk) begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -1,42 +1,42 @@
|
|||
WIDTH=32;
|
||||
DEPTH=32;
|
||||
|
||||
ADDRESS_RADIX=HEX;
|
||||
DATA_RADIX=HEX;
|
||||
|
||||
CONTENT BEGIN
|
||||
|
||||
00 : deadbeef;
|
||||
01 : deadbeef;
|
||||
02 : deadbeef;
|
||||
03 : deadbeef;
|
||||
04 : deadbeef;
|
||||
05 : deadbeef;
|
||||
06 : deadbeef;
|
||||
07 : deadbeef;
|
||||
08 : deadbeef;
|
||||
09 : deadbeef;
|
||||
0a : deadbeef;
|
||||
0b : deadbeef;
|
||||
0c : deadbeef;
|
||||
0d : deadbeef;
|
||||
0e : deadbeef;
|
||||
0f : deadbeef;
|
||||
10 : deadbeef;
|
||||
11 : deadbeef;
|
||||
12 : deadbeef;
|
||||
13 : deadbeef;
|
||||
14 : deadbeef;
|
||||
15 : deadbeef;
|
||||
16 : deadbeef;
|
||||
17 : deadbeef;
|
||||
18 : deadbeef;
|
||||
19 : deadbeef;
|
||||
1a : deadbeef;
|
||||
1b : deadbeef;
|
||||
1c : deadbeef;
|
||||
1d : deadbeef;
|
||||
1e : deadbeef;
|
||||
1f : deadbeef;
|
||||
|
||||
END;
|
||||
WIDTH=32;
|
||||
DEPTH=32;
|
||||
|
||||
ADDRESS_RADIX=HEX;
|
||||
DATA_RADIX=HEX;
|
||||
|
||||
CONTENT BEGIN
|
||||
|
||||
00 : deadbeef;
|
||||
01 : deadbeef;
|
||||
02 : deadbeef;
|
||||
03 : deadbeef;
|
||||
04 : deadbeef;
|
||||
05 : deadbeef;
|
||||
06 : deadbeef;
|
||||
07 : deadbeef;
|
||||
08 : deadbeef;
|
||||
09 : deadbeef;
|
||||
0a : deadbeef;
|
||||
0b : deadbeef;
|
||||
0c : deadbeef;
|
||||
0d : deadbeef;
|
||||
0e : deadbeef;
|
||||
0f : deadbeef;
|
||||
10 : deadbeef;
|
||||
11 : deadbeef;
|
||||
12 : deadbeef;
|
||||
13 : deadbeef;
|
||||
14 : deadbeef;
|
||||
15 : deadbeef;
|
||||
16 : deadbeef;
|
||||
17 : deadbeef;
|
||||
18 : deadbeef;
|
||||
19 : deadbeef;
|
||||
1a : deadbeef;
|
||||
1b : deadbeef;
|
||||
1c : deadbeef;
|
||||
1d : deadbeef;
|
||||
1e : deadbeef;
|
||||
1f : deadbeef;
|
||||
|
||||
END;
|
||||
|
|
|
|||
|
|
@ -1,42 +1,42 @@
|
|||
WIDTH=32;
|
||||
DEPTH=32;
|
||||
|
||||
ADDRESS_RADIX=HEX;
|
||||
DATA_RADIX=HEX;
|
||||
|
||||
CONTENT BEGIN
|
||||
|
||||
00 : deadbeef;
|
||||
01 : deadbeef;
|
||||
02 : deadbeef;
|
||||
03 : deadbeef;
|
||||
04 : deadbeef;
|
||||
05 : deadbeef;
|
||||
06 : deadbeef;
|
||||
07 : deadbeef;
|
||||
08 : deadbeef;
|
||||
09 : deadbeef;
|
||||
0a : deadbeef;
|
||||
0b : deadbeef;
|
||||
0c : deadbeef;
|
||||
0d : deadbeef;
|
||||
0e : deadbeef;
|
||||
0f : deadbeef;
|
||||
10 : deadbeef;
|
||||
11 : deadbeef;
|
||||
12 : deadbeef;
|
||||
13 : deadbeef;
|
||||
14 : deadbeef;
|
||||
15 : deadbeef;
|
||||
16 : deadbeef;
|
||||
17 : deadbeef;
|
||||
18 : deadbeef;
|
||||
19 : deadbeef;
|
||||
1a : deadbeef;
|
||||
1b : deadbeef;
|
||||
1c : deadbeef;
|
||||
1d : deadbeef;
|
||||
1e : deadbeef;
|
||||
1f : deadbeef;
|
||||
|
||||
END;
|
||||
WIDTH=32;
|
||||
DEPTH=32;
|
||||
|
||||
ADDRESS_RADIX=HEX;
|
||||
DATA_RADIX=HEX;
|
||||
|
||||
CONTENT BEGIN
|
||||
|
||||
00 : deadbeef;
|
||||
01 : deadbeef;
|
||||
02 : deadbeef;
|
||||
03 : deadbeef;
|
||||
04 : deadbeef;
|
||||
05 : deadbeef;
|
||||
06 : deadbeef;
|
||||
07 : deadbeef;
|
||||
08 : deadbeef;
|
||||
09 : deadbeef;
|
||||
0a : deadbeef;
|
||||
0b : deadbeef;
|
||||
0c : deadbeef;
|
||||
0d : deadbeef;
|
||||
0e : deadbeef;
|
||||
0f : deadbeef;
|
||||
10 : deadbeef;
|
||||
11 : deadbeef;
|
||||
12 : deadbeef;
|
||||
13 : deadbeef;
|
||||
14 : deadbeef;
|
||||
15 : deadbeef;
|
||||
16 : deadbeef;
|
||||
17 : deadbeef;
|
||||
18 : deadbeef;
|
||||
19 : deadbeef;
|
||||
1a : deadbeef;
|
||||
1b : deadbeef;
|
||||
1c : deadbeef;
|
||||
1d : deadbeef;
|
||||
1e : deadbeef;
|
||||
1f : deadbeef;
|
||||
|
||||
END;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,12 +1,12 @@
|
|||
// niosII_mm_interconnect_0_avalon_st_adapter.v
|
||||
|
||||
// niosII_mm_interconnect_0_avalon_st_adapter.v
|
||||
|
||||
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
|
||||
// will probably be lost.
|
||||
//
|
||||
// Generated using ACDS version 18.1 625
|
||||
|
||||
// Generated using ACDS version 18.1 625
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module niosII_mm_interconnect_0_avalon_st_adapter #(
|
||||
module niosII_mm_interconnect_0_avalon_st_adapter #(
|
||||
parameter inBitsPerSymbol = 34,
|
||||
parameter inUsePackets = 0,
|
||||
parameter inDataWidth = 34,
|
||||
|
|
@ -23,7 +23,7 @@ module niosII_mm_interconnect_0_avalon_st_adapter #(
|
|||
parameter outUseValid = 1,
|
||||
parameter outUseReady = 1,
|
||||
parameter outReadyLatency = 0
|
||||
) (
|
||||
) (
|
||||
input wire in_clk_0_clk, // in_clk_0.clk
|
||||
input wire in_rst_0_reset, // in_rst_0.reset
|
||||
input wire [33:0] in_0_data, // in_0.data
|
||||
|
|
@ -33,14 +33,14 @@ module niosII_mm_interconnect_0_avalon_st_adapter #(
|
|||
output wire out_0_valid, // .valid
|
||||
input wire out_0_ready, // .ready
|
||||
output wire [0:0] out_0_error // .error
|
||||
);
|
||||
|
||||
generate
|
||||
// If any of the display statements (or deliberately broken
|
||||
// instantiations) within this generate block triggers then this module
|
||||
// has been instantiated this module with a set of parameters different
|
||||
// from those it was generated for. This will usually result in a
|
||||
// non-functioning system.
|
||||
);
|
||||
|
||||
generate
|
||||
// If any of the display statements (or deliberately broken
|
||||
// instantiations) within this generate block triggers then this module
|
||||
// has been instantiated this module with a set of parameters different
|
||||
// from those it was generated for. This will usually result in a
|
||||
// non-functioning system.
|
||||
if (inBitsPerSymbol != 34)
|
||||
begin
|
||||
initial begin
|
||||
|
|
@ -185,8 +185,8 @@ module niosII_mm_interconnect_0_avalon_st_adapter #(
|
|||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
outreadylatency_check ( .error(1'b1) );
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endgenerate
|
||||
|
||||
niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
|
||||
.clk (in_clk_0_clk), // clk.clk
|
||||
.reset_n (~in_rst_0_reset), // reset.reset_n
|
||||
|
|
@ -197,6 +197,6 @@ module niosII_mm_interconnect_0_avalon_st_adapter #(
|
|||
.out_valid (out_0_valid), // .valid
|
||||
.out_ready (out_0_ready), // .ready
|
||||
.out_error (out_0_error) // .error
|
||||
);
|
||||
|
||||
endmodule
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -29,8 +29,8 @@
|
|||
// Generation parameters:
|
||||
// output_name: niosII_mm_interconnect_0_cmd_demux
|
||||
// ST_DATA_W: 94
|
||||
// ST_CHANNEL_W: 7
|
||||
// NUM_OUTPUTS: 6
|
||||
// ST_CHANNEL_W: 6
|
||||
// NUM_OUTPUTS: 5
|
||||
// VALID_WIDTH: 1
|
||||
// ------------------------------------------
|
||||
|
||||
|
|
@ -47,7 +47,7 @@ module niosII_mm_interconnect_0_cmd_demux
|
|||
// -------------------
|
||||
input [1-1 : 0] sink_valid,
|
||||
input [94-1 : 0] sink_data, // ST_DATA_W=94
|
||||
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
|
||||
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
output sink_ready,
|
||||
|
|
@ -57,46 +57,39 @@ module niosII_mm_interconnect_0_cmd_demux
|
|||
// -------------------
|
||||
output reg src0_valid,
|
||||
output reg [94-1 : 0] src0_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
|
||||
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
|
||||
output reg src0_startofpacket,
|
||||
output reg src0_endofpacket,
|
||||
input src0_ready,
|
||||
|
||||
output reg src1_valid,
|
||||
output reg [94-1 : 0] src1_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
|
||||
output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
|
||||
output reg src1_startofpacket,
|
||||
output reg src1_endofpacket,
|
||||
input src1_ready,
|
||||
|
||||
output reg src2_valid,
|
||||
output reg [94-1 : 0] src2_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src2_channel, // ST_CHANNEL_W=7
|
||||
output reg [6-1 : 0] src2_channel, // ST_CHANNEL_W=6
|
||||
output reg src2_startofpacket,
|
||||
output reg src2_endofpacket,
|
||||
input src2_ready,
|
||||
|
||||
output reg src3_valid,
|
||||
output reg [94-1 : 0] src3_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src3_channel, // ST_CHANNEL_W=7
|
||||
output reg [6-1 : 0] src3_channel, // ST_CHANNEL_W=6
|
||||
output reg src3_startofpacket,
|
||||
output reg src3_endofpacket,
|
||||
input src3_ready,
|
||||
|
||||
output reg src4_valid,
|
||||
output reg [94-1 : 0] src4_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src4_channel, // ST_CHANNEL_W=7
|
||||
output reg [6-1 : 0] src4_channel, // ST_CHANNEL_W=6
|
||||
output reg src4_startofpacket,
|
||||
output reg src4_endofpacket,
|
||||
input src4_ready,
|
||||
|
||||
output reg src5_valid,
|
||||
output reg [94-1 : 0] src5_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src5_channel, // ST_CHANNEL_W=7
|
||||
output reg src5_startofpacket,
|
||||
output reg src5_endofpacket,
|
||||
input src5_ready,
|
||||
|
||||
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
|
|
@ -108,7 +101,7 @@ module niosII_mm_interconnect_0_cmd_demux
|
|||
|
||||
);
|
||||
|
||||
localparam NUM_OUTPUTS = 6;
|
||||
localparam NUM_OUTPUTS = 5;
|
||||
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
|
||||
|
||||
// -------------------
|
||||
|
|
@ -150,13 +143,6 @@ module niosII_mm_interconnect_0_cmd_demux
|
|||
|
||||
src4_valid = sink_channel[4] && sink_valid;
|
||||
|
||||
src5_data = sink_data;
|
||||
src5_startofpacket = sink_startofpacket;
|
||||
src5_endofpacket = sink_endofpacket;
|
||||
src5_channel = sink_channel >> NUM_OUTPUTS;
|
||||
|
||||
src5_valid = sink_channel[5] && sink_valid;
|
||||
|
||||
end
|
||||
|
||||
// -------------------
|
||||
|
|
@ -167,7 +153,6 @@ module niosII_mm_interconnect_0_cmd_demux
|
|||
assign ready_vector[2] = src2_ready;
|
||||
assign ready_vector[3] = src3_ready;
|
||||
assign ready_vector[4] = src4_ready;
|
||||
assign ready_vector[5] = src5_ready;
|
||||
|
||||
assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@
|
|||
// Generation parameters:
|
||||
// output_name: niosII_mm_interconnect_0_cmd_demux_001
|
||||
// ST_DATA_W: 94
|
||||
// ST_CHANNEL_W: 7
|
||||
// ST_CHANNEL_W: 6
|
||||
// NUM_OUTPUTS: 2
|
||||
// VALID_WIDTH: 1
|
||||
// ------------------------------------------
|
||||
|
|
@ -47,7 +47,7 @@ module niosII_mm_interconnect_0_cmd_demux_001
|
|||
// -------------------
|
||||
input [1-1 : 0] sink_valid,
|
||||
input [94-1 : 0] sink_data, // ST_DATA_W=94
|
||||
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
|
||||
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
output sink_ready,
|
||||
|
|
@ -57,14 +57,14 @@ module niosII_mm_interconnect_0_cmd_demux_001
|
|||
// -------------------
|
||||
output reg src0_valid,
|
||||
output reg [94-1 : 0] src0_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
|
||||
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
|
||||
output reg src0_startofpacket,
|
||||
output reg src0_endofpacket,
|
||||
input src0_ready,
|
||||
|
||||
output reg src1_valid,
|
||||
output reg [94-1 : 0] src1_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
|
||||
output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
|
||||
output reg src1_startofpacket,
|
||||
output reg src1_endofpacket,
|
||||
input src1_ready,
|
||||
|
|
@ -109,7 +109,7 @@ module niosII_mm_interconnect_0_cmd_demux_001
|
|||
assign ready_vector[0] = src0_ready;
|
||||
assign ready_vector[1] = src1_ready;
|
||||
|
||||
assign sink_ready = |(sink_channel & {{5{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
|
||||
assign sink_ready = |(sink_channel & {{4{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
// PIPELINE_ARB: 1
|
||||
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
|
||||
// ST_DATA_W: 94
|
||||
// ST_CHANNEL_W: 7
|
||||
// ST_CHANNEL_W: 6
|
||||
// ------------------------------------------
|
||||
|
||||
module niosII_mm_interconnect_0_cmd_mux
|
||||
|
|
@ -55,7 +55,7 @@ module niosII_mm_interconnect_0_cmd_mux
|
|||
// ----------------------
|
||||
input sink0_valid,
|
||||
input [94-1 : 0] sink0_data,
|
||||
input [7-1: 0] sink0_channel,
|
||||
input [6-1: 0] sink0_channel,
|
||||
input sink0_startofpacket,
|
||||
input sink0_endofpacket,
|
||||
output sink0_ready,
|
||||
|
|
@ -66,7 +66,7 @@ module niosII_mm_interconnect_0_cmd_mux
|
|||
// ----------------------
|
||||
output src_valid,
|
||||
output [94-1 : 0] src_data,
|
||||
output [7-1 : 0] src_channel,
|
||||
output [6-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready,
|
||||
|
|
@ -77,12 +77,12 @@ module niosII_mm_interconnect_0_cmd_mux
|
|||
input clk,
|
||||
input reset
|
||||
);
|
||||
localparam PAYLOAD_W = 94 + 7 + 2;
|
||||
localparam PAYLOAD_W = 94 + 6 + 2;
|
||||
localparam NUM_INPUTS = 1;
|
||||
localparam SHARE_COUNTER_W = 1;
|
||||
localparam PIPELINE_ARB = 1;
|
||||
localparam ST_DATA_W = 94;
|
||||
localparam ST_CHANNEL_W = 7;
|
||||
localparam ST_CHANNEL_W = 6;
|
||||
localparam PKT_TRANS_LOCK = 58;
|
||||
|
||||
assign src_valid = sink0_valid;
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
// PIPELINE_ARB: 1
|
||||
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
|
||||
// ST_DATA_W: 94
|
||||
// ST_CHANNEL_W: 7
|
||||
// ST_CHANNEL_W: 6
|
||||
// ------------------------------------------
|
||||
|
||||
module niosII_mm_interconnect_0_cmd_mux_002
|
||||
|
|
@ -55,14 +55,14 @@ module niosII_mm_interconnect_0_cmd_mux_002
|
|||
// ----------------------
|
||||
input sink0_valid,
|
||||
input [94-1 : 0] sink0_data,
|
||||
input [7-1: 0] sink0_channel,
|
||||
input [6-1: 0] sink0_channel,
|
||||
input sink0_startofpacket,
|
||||
input sink0_endofpacket,
|
||||
output sink0_ready,
|
||||
|
||||
input sink1_valid,
|
||||
input [94-1 : 0] sink1_data,
|
||||
input [7-1: 0] sink1_channel,
|
||||
input [6-1: 0] sink1_channel,
|
||||
input sink1_startofpacket,
|
||||
input sink1_endofpacket,
|
||||
output sink1_ready,
|
||||
|
|
@ -73,7 +73,7 @@ module niosII_mm_interconnect_0_cmd_mux_002
|
|||
// ----------------------
|
||||
output src_valid,
|
||||
output [94-1 : 0] src_data,
|
||||
output [7-1 : 0] src_channel,
|
||||
output [6-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready,
|
||||
|
|
@ -84,12 +84,12 @@ module niosII_mm_interconnect_0_cmd_mux_002
|
|||
input clk,
|
||||
input reset
|
||||
);
|
||||
localparam PAYLOAD_W = 94 + 7 + 2;
|
||||
localparam PAYLOAD_W = 94 + 6 + 2;
|
||||
localparam NUM_INPUTS = 2;
|
||||
localparam SHARE_COUNTER_W = 1;
|
||||
localparam PIPELINE_ARB = 1;
|
||||
localparam ST_DATA_W = 94;
|
||||
localparam ST_CHANNEL_W = 7;
|
||||
localparam ST_CHANNEL_W = 6;
|
||||
localparam PKT_TRANS_LOCK = 58;
|
||||
|
||||
// ------------------------------------------
|
||||
|
|
|
|||
|
|
@ -44,15 +44,15 @@
|
|||
|
||||
module niosII_mm_interconnect_0_router_default_decode
|
||||
#(
|
||||
parameter DEFAULT_CHANNEL = 5,
|
||||
parameter DEFAULT_CHANNEL = 4,
|
||||
DEFAULT_WR_CHANNEL = -1,
|
||||
DEFAULT_RD_CHANNEL = -1,
|
||||
DEFAULT_DESTID = 3
|
||||
)
|
||||
(output [80 - 78 : 0] default_destination_id,
|
||||
output [7-1 : 0] default_wr_channel,
|
||||
output [7-1 : 0] default_rd_channel,
|
||||
output [7-1 : 0] default_src_channel
|
||||
output [6-1 : 0] default_wr_channel,
|
||||
output [6-1 : 0] default_rd_channel,
|
||||
output [6-1 : 0] default_src_channel
|
||||
);
|
||||
|
||||
assign default_destination_id =
|
||||
|
|
@ -63,7 +63,7 @@ module niosII_mm_interconnect_0_router_default_decode
|
|||
assign default_src_channel = '0;
|
||||
end
|
||||
else begin : default_channel_assignment
|
||||
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
|
||||
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_default_decode
|
|||
assign default_rd_channel = '0;
|
||||
end
|
||||
else begin : default_rw_channel_assignment
|
||||
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
|
||||
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
@ -103,7 +103,7 @@ module niosII_mm_interconnect_0_router
|
|||
// -------------------
|
||||
output src_valid,
|
||||
output reg [94-1 : 0] src_data,
|
||||
output reg [7-1 : 0] src_channel,
|
||||
output reg [6-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready
|
||||
|
|
@ -119,7 +119,7 @@ module niosII_mm_interconnect_0_router
|
|||
localparam PKT_PROTECTION_H = 84;
|
||||
localparam PKT_PROTECTION_L = 82;
|
||||
localparam ST_DATA_W = 94;
|
||||
localparam ST_CHANNEL_W = 7;
|
||||
localparam ST_CHANNEL_W = 6;
|
||||
localparam DECODER_TYPE = 0;
|
||||
|
||||
localparam PKT_TRANS_WRITE = 56;
|
||||
|
|
@ -136,16 +136,15 @@ module niosII_mm_interconnect_0_router
|
|||
// -------------------------------------------------------
|
||||
localparam PAD0 = log2ceil(64'h20000 - 64'h0);
|
||||
localparam PAD1 = log2ceil(64'h21000 - 64'h20800);
|
||||
localparam PAD2 = log2ceil(64'h21040 - 64'h21000);
|
||||
localparam PAD3 = log2ceil(64'h21060 - 64'h21040);
|
||||
localparam PAD4 = log2ceil(64'h21068 - 64'h21060);
|
||||
localparam PAD5 = log2ceil(64'h21070 - 64'h21068);
|
||||
localparam PAD2 = log2ceil(64'h21020 - 64'h21000);
|
||||
localparam PAD3 = log2ceil(64'h21028 - 64'h21020);
|
||||
localparam PAD4 = log2ceil(64'h2102c - 64'h21028);
|
||||
// -------------------------------------------------------
|
||||
// Work out which address bits are significant based on the
|
||||
// address range of the slaves. If the required width is too
|
||||
// large or too small, we use the address field width instead.
|
||||
// -------------------------------------------------------
|
||||
localparam ADDR_RANGE = 64'h21070;
|
||||
localparam ADDR_RANGE = 64'h2102c;
|
||||
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
|
||||
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
|
||||
(RANGE_ADDR_WIDTH == 0) ?
|
||||
|
|
@ -169,7 +168,7 @@ module niosII_mm_interconnect_0_router
|
|||
assign src_startofpacket = sink_startofpacket;
|
||||
assign src_endofpacket = sink_endofpacket;
|
||||
wire [PKT_DEST_ID_W-1:0] default_destid;
|
||||
wire [7-1 : 0] default_src_channel;
|
||||
wire [6-1 : 0] default_src_channel;
|
||||
|
||||
|
||||
|
||||
|
|
@ -200,40 +199,34 @@ module niosII_mm_interconnect_0_router
|
|||
|
||||
// ( 0x0 .. 0x20000 )
|
||||
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0 ) begin
|
||||
src_channel = 7'b100000;
|
||||
src_channel = 6'b10000;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
|
||||
end
|
||||
|
||||
// ( 0x20800 .. 0x21000 )
|
||||
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800 ) begin
|
||||
src_channel = 7'b000100;
|
||||
src_channel = 6'b00100;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
|
||||
end
|
||||
|
||||
// ( 0x21000 .. 0x21040 )
|
||||
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h21000 && write_transaction ) begin
|
||||
src_channel = 7'b001000;
|
||||
// ( 0x21000 .. 0x21020 )
|
||||
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h21000 ) begin
|
||||
src_channel = 6'b01000;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
|
||||
end
|
||||
|
||||
// ( 0x21040 .. 0x21060 )
|
||||
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h21040 ) begin
|
||||
src_channel = 7'b010000;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
|
||||
end
|
||||
|
||||
// ( 0x21060 .. 0x21068 )
|
||||
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h21060 ) begin
|
||||
src_channel = 7'b000010;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
|
||||
end
|
||||
|
||||
// ( 0x21068 .. 0x21070 )
|
||||
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 18'h21068 ) begin
|
||||
src_channel = 7'b000001;
|
||||
// ( 0x21020 .. 0x21028 )
|
||||
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h21020 ) begin
|
||||
src_channel = 6'b00001;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
|
||||
end
|
||||
|
||||
// ( 0x21028 .. 0x2102c )
|
||||
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h21028 && write_transaction ) begin
|
||||
src_channel = 6'b00010;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -50,9 +50,9 @@ module niosII_mm_interconnect_0_router_001_default_decode
|
|||
DEFAULT_DESTID = 2
|
||||
)
|
||||
(output [80 - 78 : 0] default_destination_id,
|
||||
output [7-1 : 0] default_wr_channel,
|
||||
output [7-1 : 0] default_rd_channel,
|
||||
output [7-1 : 0] default_src_channel
|
||||
output [6-1 : 0] default_wr_channel,
|
||||
output [6-1 : 0] default_rd_channel,
|
||||
output [6-1 : 0] default_src_channel
|
||||
);
|
||||
|
||||
assign default_destination_id =
|
||||
|
|
@ -63,7 +63,7 @@ module niosII_mm_interconnect_0_router_001_default_decode
|
|||
assign default_src_channel = '0;
|
||||
end
|
||||
else begin : default_channel_assignment
|
||||
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
|
||||
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_001_default_decode
|
|||
assign default_rd_channel = '0;
|
||||
end
|
||||
else begin : default_rw_channel_assignment
|
||||
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
|
||||
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
@ -103,7 +103,7 @@ module niosII_mm_interconnect_0_router_001
|
|||
// -------------------
|
||||
output src_valid,
|
||||
output reg [94-1 : 0] src_data,
|
||||
output reg [7-1 : 0] src_channel,
|
||||
output reg [6-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready
|
||||
|
|
@ -119,7 +119,7 @@ module niosII_mm_interconnect_0_router_001
|
|||
localparam PKT_PROTECTION_H = 84;
|
||||
localparam PKT_PROTECTION_L = 82;
|
||||
localparam ST_DATA_W = 94;
|
||||
localparam ST_CHANNEL_W = 7;
|
||||
localparam ST_CHANNEL_W = 6;
|
||||
localparam DECODER_TYPE = 0;
|
||||
|
||||
localparam PKT_TRANS_WRITE = 56;
|
||||
|
|
@ -165,7 +165,7 @@ module niosII_mm_interconnect_0_router_001
|
|||
assign src_startofpacket = sink_startofpacket;
|
||||
assign src_endofpacket = sink_endofpacket;
|
||||
wire [PKT_DEST_ID_W-1:0] default_destid;
|
||||
wire [7-1 : 0] default_src_channel;
|
||||
wire [6-1 : 0] default_src_channel;
|
||||
|
||||
|
||||
|
||||
|
|
@ -191,13 +191,13 @@ module niosII_mm_interconnect_0_router_001
|
|||
|
||||
// ( 0x0 .. 0x20000 )
|
||||
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0 ) begin
|
||||
src_channel = 7'b10;
|
||||
src_channel = 6'b10;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
|
||||
end
|
||||
|
||||
// ( 0x20800 .. 0x21000 )
|
||||
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800 ) begin
|
||||
src_channel = 7'b01;
|
||||
src_channel = 6'b01;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -50,9 +50,9 @@ module niosII_mm_interconnect_0_router_002_default_decode
|
|||
DEFAULT_DESTID = 0
|
||||
)
|
||||
(output [80 - 78 : 0] default_destination_id,
|
||||
output [7-1 : 0] default_wr_channel,
|
||||
output [7-1 : 0] default_rd_channel,
|
||||
output [7-1 : 0] default_src_channel
|
||||
output [6-1 : 0] default_wr_channel,
|
||||
output [6-1 : 0] default_rd_channel,
|
||||
output [6-1 : 0] default_src_channel
|
||||
);
|
||||
|
||||
assign default_destination_id =
|
||||
|
|
@ -63,7 +63,7 @@ module niosII_mm_interconnect_0_router_002_default_decode
|
|||
assign default_src_channel = '0;
|
||||
end
|
||||
else begin : default_channel_assignment
|
||||
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
|
||||
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_002_default_decode
|
|||
assign default_rd_channel = '0;
|
||||
end
|
||||
else begin : default_rw_channel_assignment
|
||||
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
|
||||
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
@ -103,7 +103,7 @@ module niosII_mm_interconnect_0_router_002
|
|||
// -------------------
|
||||
output src_valid,
|
||||
output reg [94-1 : 0] src_data,
|
||||
output reg [7-1 : 0] src_channel,
|
||||
output reg [6-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready
|
||||
|
|
@ -119,7 +119,7 @@ module niosII_mm_interconnect_0_router_002
|
|||
localparam PKT_PROTECTION_H = 84;
|
||||
localparam PKT_PROTECTION_L = 82;
|
||||
localparam ST_DATA_W = 94;
|
||||
localparam ST_CHANNEL_W = 7;
|
||||
localparam ST_CHANNEL_W = 6;
|
||||
localparam DECODER_TYPE = 1;
|
||||
|
||||
localparam PKT_TRANS_WRITE = 56;
|
||||
|
|
@ -158,7 +158,7 @@ module niosII_mm_interconnect_0_router_002
|
|||
assign src_valid = sink_valid;
|
||||
assign src_startofpacket = sink_startofpacket;
|
||||
assign src_endofpacket = sink_endofpacket;
|
||||
wire [7-1 : 0] default_src_channel;
|
||||
wire [6-1 : 0] default_src_channel;
|
||||
|
||||
|
||||
|
||||
|
|
@ -185,7 +185,7 @@ module niosII_mm_interconnect_0_router_002
|
|||
|
||||
|
||||
if (destid == 0 ) begin
|
||||
src_channel = 7'b1;
|
||||
src_channel = 6'b1;
|
||||
end
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,224 +1,224 @@
|
|||
// (C) 2001-2018 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2018/07/18 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Merlin Router
|
||||
//
|
||||
// Asserts the appropriate one-hot encoded channel based on
|
||||
// either (a) the address or (b) the dest id. The DECODER_TYPE
|
||||
// parameter controls this behaviour. 0 means address decoder,
|
||||
// 1 means dest id decoder.
|
||||
//
|
||||
// In the case of (a), it also sets the destination id.
|
||||
// -------------------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module niosII_mm_interconnect_0_router_004_default_decode
|
||||
#(
|
||||
parameter DEFAULT_CHANNEL = 0,
|
||||
DEFAULT_WR_CHANNEL = -1,
|
||||
DEFAULT_RD_CHANNEL = -1,
|
||||
DEFAULT_DESTID = 0
|
||||
)
|
||||
(output [80 - 78 : 0] default_destination_id,
|
||||
output [7-1 : 0] default_wr_channel,
|
||||
output [7-1 : 0] default_rd_channel,
|
||||
output [7-1 : 0] default_src_channel
|
||||
);
|
||||
|
||||
assign default_destination_id =
|
||||
DEFAULT_DESTID[80 - 78 : 0];
|
||||
|
||||
generate
|
||||
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
|
||||
assign default_src_channel = '0;
|
||||
end
|
||||
else begin : default_channel_assignment
|
||||
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
|
||||
assign default_wr_channel = '0;
|
||||
assign default_rd_channel = '0;
|
||||
end
|
||||
else begin : default_rw_channel_assignment
|
||||
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module niosII_mm_interconnect_0_router_004
|
||||
(
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// -------------------
|
||||
// Command Sink (Input)
|
||||
// -------------------
|
||||
input sink_valid,
|
||||
input [94-1 : 0] sink_data,
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
output sink_ready,
|
||||
|
||||
// -------------------
|
||||
// Command Source (Output)
|
||||
// -------------------
|
||||
output src_valid,
|
||||
output reg [94-1 : 0] src_data,
|
||||
output reg [7-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready
|
||||
);
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Local parameters and variables
|
||||
// -------------------------------------------------------
|
||||
localparam PKT_ADDR_H = 53;
|
||||
localparam PKT_ADDR_L = 36;
|
||||
localparam PKT_DEST_ID_H = 80;
|
||||
localparam PKT_DEST_ID_L = 78;
|
||||
localparam PKT_PROTECTION_H = 84;
|
||||
localparam PKT_PROTECTION_L = 82;
|
||||
localparam ST_DATA_W = 94;
|
||||
localparam ST_CHANNEL_W = 7;
|
||||
localparam DECODER_TYPE = 1;
|
||||
|
||||
localparam PKT_TRANS_WRITE = 56;
|
||||
localparam PKT_TRANS_READ = 57;
|
||||
|
||||
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
|
||||
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
|
||||
|
||||
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Figure out the number of bits to mask off for each slave span
|
||||
// during address decoding
|
||||
// -------------------------------------------------------
|
||||
// -------------------------------------------------------
|
||||
// Work out which address bits are significant based on the
|
||||
// address range of the slaves. If the required width is too
|
||||
// large or too small, we use the address field width instead.
|
||||
// -------------------------------------------------------
|
||||
localparam ADDR_RANGE = 64'h0;
|
||||
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
|
||||
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
|
||||
(RANGE_ADDR_WIDTH == 0) ?
|
||||
PKT_ADDR_H :
|
||||
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
|
||||
|
||||
localparam RG = RANGE_ADDR_WIDTH;
|
||||
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
|
||||
|
||||
reg [PKT_DEST_ID_W-1 : 0] destid;
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Pass almost everything through, untouched
|
||||
// -------------------------------------------------------
|
||||
assign sink_ready = src_ready;
|
||||
assign src_valid = sink_valid;
|
||||
assign src_startofpacket = sink_startofpacket;
|
||||
assign src_endofpacket = sink_endofpacket;
|
||||
wire [7-1 : 0] default_src_channel;
|
||||
|
||||
|
||||
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Write and read transaction signals
|
||||
// -------------------------------------------------------
|
||||
wire read_transaction;
|
||||
assign read_transaction = sink_data[PKT_TRANS_READ];
|
||||
|
||||
|
||||
niosII_mm_interconnect_0_router_004_default_decode the_default_decode(
|
||||
.default_destination_id (),
|
||||
.default_wr_channel (),
|
||||
.default_rd_channel (),
|
||||
.default_src_channel (default_src_channel)
|
||||
);
|
||||
|
||||
always @* begin
|
||||
src_data = sink_data;
|
||||
src_channel = default_src_channel;
|
||||
|
||||
// --------------------------------------------------
|
||||
// DestinationID Decoder
|
||||
// Sets the channel based on the destination ID.
|
||||
// --------------------------------------------------
|
||||
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
|
||||
|
||||
|
||||
|
||||
if (destid == 0 ) begin
|
||||
src_channel = 7'b01;
|
||||
end
|
||||
|
||||
if (destid == 1 && read_transaction) begin
|
||||
src_channel = 7'b10;
|
||||
end
|
||||
|
||||
|
||||
end
|
||||
|
||||
|
||||
// --------------------------------------------------
|
||||
// Ceil(log2()) function
|
||||
// --------------------------------------------------
|
||||
function integer log2ceil;
|
||||
input reg[65:0] val;
|
||||
reg [65:0] i;
|
||||
|
||||
begin
|
||||
i = 1;
|
||||
log2ceil = 0;
|
||||
|
||||
while (i < val) begin
|
||||
log2ceil = log2ceil + 1;
|
||||
i = i << 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
// (C) 2001-2018 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2018/07/18 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Merlin Router
|
||||
//
|
||||
// Asserts the appropriate one-hot encoded channel based on
|
||||
// either (a) the address or (b) the dest id. The DECODER_TYPE
|
||||
// parameter controls this behaviour. 0 means address decoder,
|
||||
// 1 means dest id decoder.
|
||||
//
|
||||
// In the case of (a), it also sets the destination id.
|
||||
// -------------------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module niosII_mm_interconnect_0_router_004_default_decode
|
||||
#(
|
||||
parameter DEFAULT_CHANNEL = 0,
|
||||
DEFAULT_WR_CHANNEL = -1,
|
||||
DEFAULT_RD_CHANNEL = -1,
|
||||
DEFAULT_DESTID = 0
|
||||
)
|
||||
(output [80 - 78 : 0] default_destination_id,
|
||||
output [6-1 : 0] default_wr_channel,
|
||||
output [6-1 : 0] default_rd_channel,
|
||||
output [6-1 : 0] default_src_channel
|
||||
);
|
||||
|
||||
assign default_destination_id =
|
||||
DEFAULT_DESTID[80 - 78 : 0];
|
||||
|
||||
generate
|
||||
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
|
||||
assign default_src_channel = '0;
|
||||
end
|
||||
else begin : default_channel_assignment
|
||||
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
|
||||
assign default_wr_channel = '0;
|
||||
assign default_rd_channel = '0;
|
||||
end
|
||||
else begin : default_rw_channel_assignment
|
||||
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module niosII_mm_interconnect_0_router_004
|
||||
(
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// -------------------
|
||||
// Command Sink (Input)
|
||||
// -------------------
|
||||
input sink_valid,
|
||||
input [94-1 : 0] sink_data,
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
output sink_ready,
|
||||
|
||||
// -------------------
|
||||
// Command Source (Output)
|
||||
// -------------------
|
||||
output src_valid,
|
||||
output reg [94-1 : 0] src_data,
|
||||
output reg [6-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready
|
||||
);
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Local parameters and variables
|
||||
// -------------------------------------------------------
|
||||
localparam PKT_ADDR_H = 53;
|
||||
localparam PKT_ADDR_L = 36;
|
||||
localparam PKT_DEST_ID_H = 80;
|
||||
localparam PKT_DEST_ID_L = 78;
|
||||
localparam PKT_PROTECTION_H = 84;
|
||||
localparam PKT_PROTECTION_L = 82;
|
||||
localparam ST_DATA_W = 94;
|
||||
localparam ST_CHANNEL_W = 6;
|
||||
localparam DECODER_TYPE = 1;
|
||||
|
||||
localparam PKT_TRANS_WRITE = 56;
|
||||
localparam PKT_TRANS_READ = 57;
|
||||
|
||||
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
|
||||
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
|
||||
|
||||
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Figure out the number of bits to mask off for each slave span
|
||||
// during address decoding
|
||||
// -------------------------------------------------------
|
||||
// -------------------------------------------------------
|
||||
// Work out which address bits are significant based on the
|
||||
// address range of the slaves. If the required width is too
|
||||
// large or too small, we use the address field width instead.
|
||||
// -------------------------------------------------------
|
||||
localparam ADDR_RANGE = 64'h0;
|
||||
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
|
||||
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
|
||||
(RANGE_ADDR_WIDTH == 0) ?
|
||||
PKT_ADDR_H :
|
||||
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
|
||||
|
||||
localparam RG = RANGE_ADDR_WIDTH;
|
||||
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
|
||||
|
||||
reg [PKT_DEST_ID_W-1 : 0] destid;
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Pass almost everything through, untouched
|
||||
// -------------------------------------------------------
|
||||
assign sink_ready = src_ready;
|
||||
assign src_valid = sink_valid;
|
||||
assign src_startofpacket = sink_startofpacket;
|
||||
assign src_endofpacket = sink_endofpacket;
|
||||
wire [6-1 : 0] default_src_channel;
|
||||
|
||||
|
||||
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Write and read transaction signals
|
||||
// -------------------------------------------------------
|
||||
wire read_transaction;
|
||||
assign read_transaction = sink_data[PKT_TRANS_READ];
|
||||
|
||||
|
||||
niosII_mm_interconnect_0_router_004_default_decode the_default_decode(
|
||||
.default_destination_id (),
|
||||
.default_wr_channel (),
|
||||
.default_rd_channel (),
|
||||
.default_src_channel (default_src_channel)
|
||||
);
|
||||
|
||||
always @* begin
|
||||
src_data = sink_data;
|
||||
src_channel = default_src_channel;
|
||||
|
||||
// --------------------------------------------------
|
||||
// DestinationID Decoder
|
||||
// Sets the channel based on the destination ID.
|
||||
// --------------------------------------------------
|
||||
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
|
||||
|
||||
|
||||
|
||||
if (destid == 0 ) begin
|
||||
src_channel = 6'b01;
|
||||
end
|
||||
|
||||
if (destid == 1 && read_transaction) begin
|
||||
src_channel = 6'b10;
|
||||
end
|
||||
|
||||
|
||||
end
|
||||
|
||||
|
||||
// --------------------------------------------------
|
||||
// Ceil(log2()) function
|
||||
// --------------------------------------------------
|
||||
function integer log2ceil;
|
||||
input reg[65:0] val;
|
||||
reg [65:0] i;
|
||||
|
||||
begin
|
||||
i = 1;
|
||||
log2ceil = 0;
|
||||
|
||||
while (i < val) begin
|
||||
log2ceil = log2ceil + 1;
|
||||
i = i << 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@
|
|||
// Generation parameters:
|
||||
// output_name: niosII_mm_interconnect_0_rsp_demux
|
||||
// ST_DATA_W: 94
|
||||
// ST_CHANNEL_W: 7
|
||||
// ST_CHANNEL_W: 6
|
||||
// NUM_OUTPUTS: 1
|
||||
// VALID_WIDTH: 1
|
||||
// ------------------------------------------
|
||||
|
|
@ -47,7 +47,7 @@ module niosII_mm_interconnect_0_rsp_demux
|
|||
// -------------------
|
||||
input [1-1 : 0] sink_valid,
|
||||
input [94-1 : 0] sink_data, // ST_DATA_W=94
|
||||
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
|
||||
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
output sink_ready,
|
||||
|
|
@ -57,7 +57,7 @@ module niosII_mm_interconnect_0_rsp_demux
|
|||
// -------------------
|
||||
output reg src0_valid,
|
||||
output reg [94-1 : 0] src0_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
|
||||
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
|
||||
output reg src0_startofpacket,
|
||||
output reg src0_endofpacket,
|
||||
input src0_ready,
|
||||
|
|
@ -94,7 +94,7 @@ module niosII_mm_interconnect_0_rsp_demux
|
|||
// -------------------
|
||||
assign ready_vector[0] = src0_ready;
|
||||
|
||||
assign sink_ready = |(sink_channel & {{6{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
|
||||
assign sink_ready = |(sink_channel & {{5{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -39,13 +39,13 @@
|
|||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: niosII_mm_interconnect_0_rsp_mux
|
||||
// NUM_INPUTS: 6
|
||||
// ARBITRATION_SHARES: 1 1 1 1 1 1
|
||||
// NUM_INPUTS: 5
|
||||
// ARBITRATION_SHARES: 1 1 1 1 1
|
||||
// ARBITRATION_SCHEME "no-arb"
|
||||
// PIPELINE_ARB: 0
|
||||
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
|
||||
// ST_DATA_W: 94
|
||||
// ST_CHANNEL_W: 7
|
||||
// ST_CHANNEL_W: 6
|
||||
// ------------------------------------------
|
||||
|
||||
module niosII_mm_interconnect_0_rsp_mux
|
||||
|
|
@ -55,53 +55,46 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
// ----------------------
|
||||
input sink0_valid,
|
||||
input [94-1 : 0] sink0_data,
|
||||
input [7-1: 0] sink0_channel,
|
||||
input [6-1: 0] sink0_channel,
|
||||
input sink0_startofpacket,
|
||||
input sink0_endofpacket,
|
||||
output sink0_ready,
|
||||
|
||||
input sink1_valid,
|
||||
input [94-1 : 0] sink1_data,
|
||||
input [7-1: 0] sink1_channel,
|
||||
input [6-1: 0] sink1_channel,
|
||||
input sink1_startofpacket,
|
||||
input sink1_endofpacket,
|
||||
output sink1_ready,
|
||||
|
||||
input sink2_valid,
|
||||
input [94-1 : 0] sink2_data,
|
||||
input [7-1: 0] sink2_channel,
|
||||
input [6-1: 0] sink2_channel,
|
||||
input sink2_startofpacket,
|
||||
input sink2_endofpacket,
|
||||
output sink2_ready,
|
||||
|
||||
input sink3_valid,
|
||||
input [94-1 : 0] sink3_data,
|
||||
input [7-1: 0] sink3_channel,
|
||||
input [6-1: 0] sink3_channel,
|
||||
input sink3_startofpacket,
|
||||
input sink3_endofpacket,
|
||||
output sink3_ready,
|
||||
|
||||
input sink4_valid,
|
||||
input [94-1 : 0] sink4_data,
|
||||
input [7-1: 0] sink4_channel,
|
||||
input [6-1: 0] sink4_channel,
|
||||
input sink4_startofpacket,
|
||||
input sink4_endofpacket,
|
||||
output sink4_ready,
|
||||
|
||||
input sink5_valid,
|
||||
input [94-1 : 0] sink5_data,
|
||||
input [7-1: 0] sink5_channel,
|
||||
input sink5_startofpacket,
|
||||
input sink5_endofpacket,
|
||||
output sink5_ready,
|
||||
|
||||
|
||||
// ----------------------
|
||||
// Source
|
||||
// ----------------------
|
||||
output src_valid,
|
||||
output [94-1 : 0] src_data,
|
||||
output [7-1 : 0] src_channel,
|
||||
output [6-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready,
|
||||
|
|
@ -112,12 +105,12 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
input clk,
|
||||
input reset
|
||||
);
|
||||
localparam PAYLOAD_W = 94 + 7 + 2;
|
||||
localparam NUM_INPUTS = 6;
|
||||
localparam PAYLOAD_W = 94 + 6 + 2;
|
||||
localparam NUM_INPUTS = 5;
|
||||
localparam SHARE_COUNTER_W = 1;
|
||||
localparam PIPELINE_ARB = 0;
|
||||
localparam ST_DATA_W = 94;
|
||||
localparam ST_CHANNEL_W = 7;
|
||||
localparam ST_CHANNEL_W = 6;
|
||||
localparam PKT_TRANS_LOCK = 58;
|
||||
|
||||
// ------------------------------------------
|
||||
|
|
@ -138,14 +131,12 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
wire [PAYLOAD_W - 1 : 0] sink2_payload;
|
||||
wire [PAYLOAD_W - 1 : 0] sink3_payload;
|
||||
wire [PAYLOAD_W - 1 : 0] sink4_payload;
|
||||
wire [PAYLOAD_W - 1 : 0] sink5_payload;
|
||||
|
||||
assign valid[0] = sink0_valid;
|
||||
assign valid[1] = sink1_valid;
|
||||
assign valid[2] = sink2_valid;
|
||||
assign valid[3] = sink3_valid;
|
||||
assign valid[4] = sink4_valid;
|
||||
assign valid[5] = sink5_valid;
|
||||
|
||||
|
||||
// ------------------------------------------
|
||||
|
|
@ -160,7 +151,6 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
lock[2] = sink2_data[58];
|
||||
lock[3] = sink3_data[58];
|
||||
lock[4] = sink4_data[58];
|
||||
lock[5] = sink5_data[58];
|
||||
end
|
||||
|
||||
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
|
||||
|
|
@ -196,13 +186,11 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
// 2 | 1 | 0
|
||||
// 3 | 1 | 0
|
||||
// 4 | 1 | 0
|
||||
// 5 | 1 | 0
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
|
||||
|
||||
// ------------------------------------------
|
||||
// Choose the share value corresponding to the grant.
|
||||
|
|
@ -214,8 +202,7 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
|
||||
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
|
||||
share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
|
||||
share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
|
||||
share_5 & { SHARE_COUNTER_W {next_grant[5]} };
|
||||
share_4 & { SHARE_COUNTER_W {next_grant[4]} };
|
||||
end
|
||||
|
||||
// ------------------------------------------
|
||||
|
|
@ -287,14 +274,11 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
|
||||
wire final_packet_4 = 1'b1;
|
||||
|
||||
wire final_packet_5 = 1'b1;
|
||||
|
||||
|
||||
// ------------------------------------------
|
||||
// Concatenate all final_packet signals (wire or reg) into a handy vector.
|
||||
// ------------------------------------------
|
||||
wire [NUM_INPUTS - 1 : 0] final_packet = {
|
||||
final_packet_5,
|
||||
final_packet_4,
|
||||
final_packet_3,
|
||||
final_packet_2,
|
||||
|
|
@ -388,7 +372,6 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
assign sink2_ready = src_ready && grant[2];
|
||||
assign sink3_ready = src_ready && grant[3];
|
||||
assign sink4_ready = src_ready && grant[4];
|
||||
assign sink5_ready = src_ready && grant[5];
|
||||
|
||||
assign src_valid = |(grant & valid);
|
||||
|
||||
|
|
@ -398,8 +381,7 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
sink1_payload & {PAYLOAD_W {grant[1]} } |
|
||||
sink2_payload & {PAYLOAD_W {grant[2]} } |
|
||||
sink3_payload & {PAYLOAD_W {grant[3]} } |
|
||||
sink4_payload & {PAYLOAD_W {grant[4]} } |
|
||||
sink5_payload & {PAYLOAD_W {grant[5]} };
|
||||
sink4_payload & {PAYLOAD_W {grant[4]} };
|
||||
end
|
||||
|
||||
// ------------------------------------------
|
||||
|
|
@ -416,8 +398,6 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
sink3_startofpacket,sink3_endofpacket};
|
||||
assign sink4_payload = {sink4_channel,sink4_data,
|
||||
sink4_startofpacket,sink4_endofpacket};
|
||||
assign sink5_payload = {sink5_channel,sink5_data,
|
||||
sink5_startofpacket,sink5_endofpacket};
|
||||
|
||||
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
// PIPELINE_ARB: 0
|
||||
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
|
||||
// ST_DATA_W: 94
|
||||
// ST_CHANNEL_W: 7
|
||||
// ST_CHANNEL_W: 6
|
||||
// ------------------------------------------
|
||||
|
||||
module niosII_mm_interconnect_0_rsp_mux_001
|
||||
|
|
@ -55,14 +55,14 @@ module niosII_mm_interconnect_0_rsp_mux_001
|
|||
// ----------------------
|
||||
input sink0_valid,
|
||||
input [94-1 : 0] sink0_data,
|
||||
input [7-1: 0] sink0_channel,
|
||||
input [6-1: 0] sink0_channel,
|
||||
input sink0_startofpacket,
|
||||
input sink0_endofpacket,
|
||||
output sink0_ready,
|
||||
|
||||
input sink1_valid,
|
||||
input [94-1 : 0] sink1_data,
|
||||
input [7-1: 0] sink1_channel,
|
||||
input [6-1: 0] sink1_channel,
|
||||
input sink1_startofpacket,
|
||||
input sink1_endofpacket,
|
||||
output sink1_ready,
|
||||
|
|
@ -73,7 +73,7 @@ module niosII_mm_interconnect_0_rsp_mux_001
|
|||
// ----------------------
|
||||
output src_valid,
|
||||
output [94-1 : 0] src_data,
|
||||
output [7-1 : 0] src_channel,
|
||||
output [6-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready,
|
||||
|
|
@ -84,12 +84,12 @@ module niosII_mm_interconnect_0_rsp_mux_001
|
|||
input clk,
|
||||
input reset
|
||||
);
|
||||
localparam PAYLOAD_W = 94 + 7 + 2;
|
||||
localparam PAYLOAD_W = 94 + 6 + 2;
|
||||
localparam NUM_INPUTS = 2;
|
||||
localparam SHARE_COUNTER_W = 1;
|
||||
localparam PIPELINE_ARB = 0;
|
||||
localparam ST_DATA_W = 94;
|
||||
localparam ST_CHANNEL_W = 7;
|
||||
localparam ST_CHANNEL_W = 6;
|
||||
localparam PKT_TRANS_LOCK = 58;
|
||||
|
||||
// ------------------------------------------
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2023.01.17.19:01:29</td>
|
||||
<td class="l">2023.01.27.19:00:16</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
|
|
@ -100,8 +100,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<a href="#module_mem"><b>mem</b>
|
||||
</a> altera_avalon_onchip_memory2 18.1
|
||||
<br/>  
|
||||
<a href="#module_sem"><b>sem</b>
|
||||
</a> sem 1.1
|
||||
<a href="#module_sigdel_0"><b>sigdel_0</b>
|
||||
</a> sigdel 1.0
|
||||
<br/>  
|
||||
<a href="#module_sys_clk_timer"><b>sys_clk_timer</b>
|
||||
</a> altera_avalon_timer 18.1</span>
|
||||
|
|
@ -144,7 +144,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="slaveb">avalon_jtag_slave </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021068</td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021020</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
|
|
@ -167,20 +167,15 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="slavemodule"> 
|
||||
<a href="#module_sem"><b>sem</b>
|
||||
<a href="#module_sigdel_0"><b>sigdel_0</b>
|
||||
</a>
|
||||
</td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">ctl_slave </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021060</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">ram_slave </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
|
||||
<td class="slaveb">avalon_slave </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021028</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
|
|
@ -193,7 +188,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="slaveb">s1 </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021040</td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
</table>
|
||||
|
|
@ -256,7 +251,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<a href="#module_clk">clk</a>
|
||||
</td>
|
||||
<td class="from">clk  </td>
|
||||
<td class="main" rowspan="31">cpu</td>
|
||||
<td class="main" rowspan="29">cpu</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  clk</td>
|
||||
|
|
@ -307,24 +302,14 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<td></td>
|
||||
<td></td>
|
||||
<td class="from">data_master  </td>
|
||||
<td class="neighbor" rowspan="6">
|
||||
<a href="#module_sem">sem</a>
|
||||
<td class="neighbor" rowspan="4">
|
||||
<a href="#module_sigdel_0">sigdel_0</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  ctl_slave</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="from">data_master  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  ram_slave</td>
|
||||
<td class="to">  avalon_slave</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
|
|
@ -334,7 +319,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  reset_n</td>
|
||||
<td class="to">  reset_sink</td>
|
||||
</tr>
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
|
|
@ -1107,7 +1092,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">dataSlaveMapParam</td>
|
||||
<td class="parametervalue"><address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map></td>
|
||||
<td class="parametervalue"><address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21020' end='0x21028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sigdel_0.avalon_slave' start='0x21028' end='0x2102C' type='sigdel.avalon_slave' /></address-map></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
|
||||
|
|
@ -1763,34 +1748,28 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_sem"> </a>
|
||||
<a name="module_sigdel_0"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>sem</h2>sem v1.1
|
||||
<h2>sigdel_0</h2>sigdel v1.0
|
||||
<br/>
|
||||
<div class="greydiv">
|
||||
<table class="connectionboxes">
|
||||
<tr>
|
||||
<td class="neighbor" rowspan="6">
|
||||
<td class="neighbor" rowspan="4">
|
||||
<a href="#module_cpu">cpu</a>
|
||||
</td>
|
||||
<td class="from">data_master  </td>
|
||||
<td class="main" rowspan="11">sem</td>
|
||||
<td class="main" rowspan="9">sigdel_0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  ctl_slave</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="from">data_master  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  ram_slave</td>
|
||||
<td class="to">  avalon_slave</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="from">debug_reset_request  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  reset_n</td>
|
||||
<td class="to">  reset_sink</td>
|
||||
</tr>
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
|
|
@ -1808,7 +1787,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<td class="from">clk_reset  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  reset_n</td>
|
||||
<td class="to">  reset_sink</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
|
|
@ -1820,8 +1799,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">m</td>
|
||||
<td class="parametervalue">32</td>
|
||||
<td class="parametername">PHACC_WIDTH</td>
|
||||
<td class="parametervalue">14</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
|
|
@ -2039,7 +2018,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.01 seconds</td>
|
||||
<td class="r">rendering took 0.03 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2023.01.17.19:01:31</td>
|
||||
<td class="l">2023.01.27.19:00:18</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
|
|
@ -100,8 +100,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<a href="#module_niosII_inst_mem"><b>niosII_inst_mem</b>
|
||||
</a> altera_avalon_onchip_memory2 18.1
|
||||
<br/>  
|
||||
<a href="#module_niosII_inst_sem"><b>niosII_inst_sem</b>
|
||||
</a> sem 1.1
|
||||
<a href="#module_niosII_inst_sigdel_0"><b>niosII_inst_sigdel_0</b>
|
||||
</a> sigdel 1.0
|
||||
<br/>  
|
||||
<a href="#module_niosII_inst_sys_clk_timer"><b>niosII_inst_sys_clk_timer</b>
|
||||
</a> altera_avalon_timer 18.1</span>
|
||||
|
|
@ -144,7 +144,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="slaveb">avalon_jtag_slave </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021068</td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021020</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
|
|
@ -167,20 +167,15 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="slavemodule"> 
|
||||
<a href="#module_niosII_inst_sem"><b>niosII_inst_sem</b>
|
||||
<a href="#module_niosII_inst_sigdel_0"><b>niosII_inst_sigdel_0</b>
|
||||
</a>
|
||||
</td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">ctl_slave </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021060</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">ram_slave </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
|
||||
<td class="slaveb">avalon_slave </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021028</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
|
|
@ -193,7 +188,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="slaveb">s1 </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021040</td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
</table>
|
||||
|
|
@ -211,7 +206,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<table>
|
||||
<tr>
|
||||
<td class="parametername">AUTO_GENERATION_ID</td>
|
||||
<td class="parametervalue">1673967691</td>
|
||||
<td class="parametervalue">1674831618</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">AUTO_UNIQUE_ID</td>
|
||||
|
|
@ -398,7 +393,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<td></td>
|
||||
<td class="from">clk  </td>
|
||||
<td class="neighbor" rowspan="4">
|
||||
<a href="#module_niosII_inst_sem">niosII_inst_sem</a>
|
||||
<a href="#module_niosII_inst_sigdel_0">niosII_inst_sigdel_0</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
|
|
@ -414,7 +409,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  reset_n</td>
|
||||
<td class="to">  reset_sink</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
|
|
@ -472,7 +467,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<a href="#module_niosII_inst_clk">niosII_inst_clk</a>
|
||||
</td>
|
||||
<td class="from">clk  </td>
|
||||
<td class="main" rowspan="31">niosII_inst_cpu</td>
|
||||
<td class="main" rowspan="29">niosII_inst_cpu</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  clk</td>
|
||||
|
|
@ -523,24 +518,14 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<td></td>
|
||||
<td></td>
|
||||
<td class="from">data_master  </td>
|
||||
<td class="neighbor" rowspan="6">
|
||||
<a href="#module_niosII_inst_sem">niosII_inst_sem</a>
|
||||
<td class="neighbor" rowspan="4">
|
||||
<a href="#module_niosII_inst_sigdel_0">niosII_inst_sigdel_0</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  ctl_slave</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="from">data_master  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  ram_slave</td>
|
||||
<td class="to">  avalon_slave</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
|
|
@ -550,7 +535,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  reset_n</td>
|
||||
<td class="to">  reset_sink</td>
|
||||
</tr>
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
|
|
@ -1323,7 +1308,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">dataSlaveMapParam</td>
|
||||
<td class="parametervalue"><address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map></td>
|
||||
<td class="parametervalue"><address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21020' end='0x21028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sigdel_0.avalon_slave' start='0x21028' end='0x2102C' type='sigdel.avalon_slave' /></address-map></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
|
||||
|
|
@ -1979,34 +1964,28 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_niosII_inst_sem"> </a>
|
||||
<a name="module_niosII_inst_sigdel_0"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>niosII_inst_sem</h2>sem v1.1
|
||||
<h2>niosII_inst_sigdel_0</h2>sigdel v1.0
|
||||
<br/>
|
||||
<div class="greydiv">
|
||||
<table class="connectionboxes">
|
||||
<tr>
|
||||
<td class="neighbor" rowspan="6">
|
||||
<td class="neighbor" rowspan="4">
|
||||
<a href="#module_niosII_inst_cpu">niosII_inst_cpu</a>
|
||||
</td>
|
||||
<td class="from">data_master  </td>
|
||||
<td class="main" rowspan="11">niosII_inst_sem</td>
|
||||
<td class="main" rowspan="9">niosII_inst_sigdel_0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  ctl_slave</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="from">data_master  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  ram_slave</td>
|
||||
<td class="to">  avalon_slave</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="from">debug_reset_request  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  reset_n</td>
|
||||
<td class="to">  reset_sink</td>
|
||||
</tr>
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
|
|
@ -2024,7 +2003,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<td class="from">clk_reset  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  reset_n</td>
|
||||
<td class="to">  reset_sink</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
|
|
@ -2036,8 +2015,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">m</td>
|
||||
<td class="parametervalue">32</td>
|
||||
<td class="parametername">PHACC_WIDTH</td>
|
||||
<td class="parametervalue">14</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
|
|
@ -2360,7 +2339,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.02 seconds</td>
|
||||
<td class="r">rendering took 0.03 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
|
|
|
|||
|
|
@ -7,33 +7,33 @@
|
|||
description=""
|
||||
tags=""
|
||||
categories="" />
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element niosII_inst
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element niosII_inst_clk_bfm
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "1";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element niosII_inst_reset_bfm
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "2";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
}
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element niosII_inst
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element niosII_inst_clk_bfm
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "1";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element niosII_inst_reset_bfm
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "2";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<parameter name="device" value="EP4CE115F29C7" />
|
||||
|
|
|
|||
|
|
@ -4,52 +4,30 @@
|
|||
|
||||
`timescale 1 ps / 1 ps
|
||||
module niosII_tb (
|
||||
);
|
||||
);
|
||||
|
||||
wire niosii_inst_clk_bfm_clk_clk; // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk]
|
||||
wire niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n
|
||||
reg train;
|
||||
wire red, yellow, green;
|
||||
wire niosii_inst_clk_bfm_clk_clk; // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk]
|
||||
wire niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n
|
||||
|
||||
niosII niosii_inst (
|
||||
.clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk
|
||||
.reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
|
||||
.sem_export_train (train), // sem_export.train
|
||||
.sem_export_red (red), // .red
|
||||
.sem_export_yellow (yellow), // .yellow
|
||||
.sem_export_green (green) // .green
|
||||
);
|
||||
|
||||
altera_avalon_clock_source #(
|
||||
.CLOCK_RATE (50000000),
|
||||
.CLOCK_UNIT (1)
|
||||
) niosii_inst_clk_bfm (
|
||||
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
|
||||
);
|
||||
|
||||
altera_avalon_reset_source #(
|
||||
.ASSERT_HIGH_RESET (0),
|
||||
.INITIAL_RESET_CYCLES (50)
|
||||
) niosii_inst_reset_bfm (
|
||||
.reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
|
||||
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
|
||||
);
|
||||
initial begin
|
||||
train = 0;
|
||||
wait (niosii_inst_reset_bfm_reset_reset);
|
||||
forever begin
|
||||
wait ({red,yellow,green}==3'b001);
|
||||
repeat (29000) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||
repeat(8) begin
|
||||
train = 1;
|
||||
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||
train = 0;
|
||||
wait ({red,yellow,green}==3'b001);
|
||||
repeat (200) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||
end
|
||||
end
|
||||
end
|
||||
niosII niosii_inst (
|
||||
.clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk
|
||||
.conduit_end_writeresponsevalid_n (), // conduit_end.writeresponsevalid_n
|
||||
.reset_reset_n (niosii_inst_reset_bfm_reset_reset) // reset.reset_n
|
||||
);
|
||||
|
||||
altera_avalon_clock_source #(
|
||||
.CLOCK_RATE (50000000),
|
||||
.CLOCK_UNIT (1)
|
||||
) niosii_inst_clk_bfm (
|
||||
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
|
||||
);
|
||||
|
||||
altera_avalon_reset_source #(
|
||||
.ASSERT_HIGH_RESET (0),
|
||||
.INITIAL_RESET_CYCLES (50)
|
||||
) niosii_inst_reset_bfm (
|
||||
.reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
|
||||
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
# system info niosII_tb on 2023.01.17.19:01:35
|
||||
# system info niosII_tb on 2023.01.27.19:00:20
|
||||
system_info:
|
||||
name,value
|
||||
DEVICE,EP4CE115F29C7
|
||||
DEVICE_FAMILY,Cyclone IV E
|
||||
GENERATION_ID,1673967691
|
||||
GENERATION_ID,1674831618
|
||||
#
|
||||
#
|
||||
# Files generated for niosII_tb on 2023.01.17.19:01:35
|
||||
# Files generated for niosII_tb on 2023.01.27.19:00:20
|
||||
files:
|
||||
filepath,kind,attributes,module,is_top
|
||||
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
|
||||
|
|
@ -19,54 +19,6 @@ niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v,VERILOG,,niosII_cp
|
|||
niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/dec.sv,SYSTEM_VERILOG,,dec,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/periodram.v,VERILOG,,dec,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v,VERILOG,,niosII_sys_clk_timer,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v,VERILOG,,niosII_mm_interconnect_0,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VERILOG,,niosII_irq_mapper,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v,VERILOG,,altera_avalon_sc_fifo,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_001,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_002,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_004,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_008,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux_001,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_demux,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v,VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter,false
|
||||
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0,false
|
||||
#
|
||||
# Map from instance-path to kind of module
|
||||
instances:
|
||||
|
|
@ -76,75 +28,9 @@ niosII_tb.niosII_inst.cpu,niosII_cpu
|
|||
niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu
|
||||
niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart
|
||||
niosII_tb.niosII_inst.mem,niosII_mem
|
||||
niosII_tb.niosII_inst.sem,dec
|
||||
niosII_tb.niosII_inst.sigdel_0,niosII_sigdel_0
|
||||
niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer
|
||||
niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_translator,altera_merlin_master_translator
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_translator,altera_merlin_master_translator
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_translator,altera_merlin_slave_translator
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_translator,altera_merlin_slave_translator
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_translator,altera_merlin_slave_translator
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_translator,altera_merlin_slave_translator
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_translator,altera_merlin_slave_translator
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_translator,altera_merlin_slave_translator
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_translator,altera_merlin_slave_translator
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_agent,altera_merlin_master_agent
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_agent,altera_merlin_master_agent
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent,altera_merlin_slave_agent
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent,altera_merlin_slave_agent
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent,altera_merlin_slave_agent
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent,altera_merlin_slave_agent
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent,altera_merlin_slave_agent
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent,altera_merlin_slave_agent
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent,altera_merlin_slave_agent
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent_rsp_fifo,altera_avalon_sc_fifo
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent_rsp_fifo,altera_avalon_sc_fifo
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent_rsp_fifo,altera_avalon_sc_fifo
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent_rsp_fifo,altera_avalon_sc_fifo
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent_rsp_fifo,altera_avalon_sc_fifo
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent_rsp_fifo,altera_avalon_sc_fifo
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent_rsp_fifo,altera_avalon_sc_fifo
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.router,niosII_mm_interconnect_0_router
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.router_001,niosII_mm_interconnect_0_router_001
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.router_002,niosII_mm_interconnect_0_router_002
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.router_003,niosII_mm_interconnect_0_router_002
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.router_005,niosII_mm_interconnect_0_router_002
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.router_006,niosII_mm_interconnect_0_router_002
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.router_007,niosII_mm_interconnect_0_router_002
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.router_004,niosII_mm_interconnect_0_router_004
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.router_008,niosII_mm_interconnect_0_router_008
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux,niosII_mm_interconnect_0_cmd_demux
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux_001,niosII_mm_interconnect_0_cmd_demux_001
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_002,niosII_mm_interconnect_0_cmd_demux_001
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux,niosII_mm_interconnect_0_cmd_mux
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_001,niosII_mm_interconnect_0_cmd_mux
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_003,niosII_mm_interconnect_0_cmd_mux
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_004,niosII_mm_interconnect_0_cmd_mux
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_005,niosII_mm_interconnect_0_cmd_mux
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_006,niosII_mm_interconnect_0_cmd_mux
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_002,niosII_mm_interconnect_0_cmd_mux_002
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux,niosII_mm_interconnect_0_rsp_demux
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_001,niosII_mm_interconnect_0_rsp_demux
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_003,niosII_mm_interconnect_0_rsp_demux
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_004,niosII_mm_interconnect_0_rsp_demux
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_005,niosII_mm_interconnect_0_rsp_demux
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_006,niosII_mm_interconnect_0_rsp_demux
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux,niosII_mm_interconnect_0_rsp_mux
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux_001,niosII_mm_interconnect_0_rsp_mux_001
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter,niosII_mm_interconnect_0_avalon_st_adapter
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001,niosII_mm_interconnect_0_avalon_st_adapter
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002,niosII_mm_interconnect_0_avalon_st_adapter
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003,niosII_mm_interconnect_0_avalon_st_adapter
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004,niosII_mm_interconnect_0_avalon_st_adapter
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005,niosII_mm_interconnect_0_avalon_st_adapter
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006,niosII_mm_interconnect_0_avalon_st_adapter
|
||||
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
|
||||
niosII_tb.niosII_inst.irq_mapper,niosII_irq_mapper
|
||||
niosII_tb.niosII_inst.rst_controller,altera_reset_controller
|
||||
niosII_tb.niosII_inst_clk_bfm,altera_avalon_clock_source
|
||||
|
|
|
|||
|
|
|
@ -5,198 +5,6 @@
|
|||
type="SYSTEM_VERILOG"
|
||||
library="altera_common_sv_packages"
|
||||
systemVerilogPackageName="avalon_vip_verbosity_pkg" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="error_adapter_0" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v"
|
||||
type="VERILOG"
|
||||
library="avalon_st_adapter" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="rsp_mux_001" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="rsp_mux_001" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="rsp_mux" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="rsp_mux" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="rsp_demux" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="cmd_mux_002" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="cmd_mux_002" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="cmd_mux" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="cmd_mux" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="cmd_demux_001" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="cmd_demux" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="router_008" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="router_004" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="router_002" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="router_001" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="router" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v"
|
||||
type="VERILOG"
|
||||
library="jtag_uart_avalon_jtag_slave_agent_rsp_fifo" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="jtag_uart_avalon_jtag_slave_agent" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="jtag_uart_avalon_jtag_slave_agent" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="cpu_data_master_agent" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="jtag_uart_avalon_jtag_slave_translator" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="cpu_data_master_translator" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v"
|
||||
type="VERILOG"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat"
|
||||
type="DAT"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat"
|
||||
type="DAT"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif"
|
||||
type="MIF"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat"
|
||||
type="DAT"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do"
|
||||
type="OTHER"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex"
|
||||
type="HEX"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v"
|
||||
type="VERILOG"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v"
|
||||
type="VERILOG"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif"
|
||||
type="MIF"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v"
|
||||
type="VERILOG"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc"
|
||||
type="SDC"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v"
|
||||
type="VERILOG"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex"
|
||||
type="HEX"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif"
|
||||
type="MIF"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex"
|
||||
type="HEX"
|
||||
library="cpu" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v"
|
||||
type="VERILOG"
|
||||
library="rst_controller" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v"
|
||||
type="VERILOG"
|
||||
library="rst_controller" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc"
|
||||
type="SDC"
|
||||
library="rst_controller" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="irq_mapper" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v"
|
||||
type="VERILOG"
|
||||
library="mm_interconnect_0" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v"
|
||||
type="VERILOG"
|
||||
library="sys_clk_timer" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/dec.sv"
|
||||
type="SYSTEM_VERILOG"
|
||||
library="sem" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/periodram.v"
|
||||
type="VERILOG"
|
||||
library="sem" />
|
||||
<file
|
||||
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex"
|
||||
type="HEX"
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE115F29C7
|
|||
set_global_assignment -name TOP_LEVEL_ENTITY top
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:34:55 OCTOBER 18, 2022"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
|
|
|
|||
BIN
Top/semafor.qws
BIN
Top/semafor.qws
Binary file not shown.
|
|
@ -0,0 +1,143 @@
|
|||
# TCL File Generated by Component Editor 18.1
|
||||
# Fri Jan 27 18:48:38 MSK 2023
|
||||
# DO NOT MODIFY
|
||||
|
||||
|
||||
#
|
||||
# sigdel "Sigma-Delta Modulator" v1.0
|
||||
# 2023.01.27.18:48:38
|
||||
#
|
||||
#
|
||||
|
||||
#
|
||||
# request TCL package from ACDS 16.1
|
||||
#
|
||||
package require -exact qsys 16.1
|
||||
|
||||
|
||||
#
|
||||
# module sigdel
|
||||
#
|
||||
set_module_property DESCRIPTION ""
|
||||
set_module_property NAME sigdel
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property INTERNAL false
|
||||
set_module_property OPAQUE_ADDRESS_MAP true
|
||||
set_module_property GROUP "User Logic"
|
||||
set_module_property AUTHOR ""
|
||||
set_module_property DISPLAY_NAME "Sigma-Delta Modulator"
|
||||
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
|
||||
set_module_property EDITABLE true
|
||||
set_module_property REPORT_TO_TALKBACK false
|
||||
set_module_property ALLOW_GREYBOX_GENERATION false
|
||||
set_module_property REPORT_HIERARCHY false
|
||||
|
||||
|
||||
#
|
||||
# file sets
|
||||
#
|
||||
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
|
||||
set_fileset_property QUARTUS_SYNTH TOP_LEVEL sigdel
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
|
||||
add_fileset_file phacc.sv SYSTEM_VERILOG PATH ../HDL/phacc.sv
|
||||
add_fileset_file sdmod.sv SYSTEM_VERILOG PATH ../HDL/sdmod.sv
|
||||
add_fileset_file sigdel.sv SYSTEM_VERILOG PATH ../HDL/sigdel.sv TOP_LEVEL_FILE
|
||||
add_fileset_file sinelut.v VERILOG PATH ../HDL/IP/sinelut.v
|
||||
add_fileset_file sine256.mif MIF PATH ../HDL/IP/sine256.mif
|
||||
|
||||
|
||||
#
|
||||
# parameters
|
||||
#
|
||||
add_parameter PHACC_WIDTH INTEGER 14
|
||||
set_parameter_property PHACC_WIDTH DEFAULT_VALUE 14
|
||||
set_parameter_property PHACC_WIDTH DISPLAY_NAME PHACC_WIDTH
|
||||
set_parameter_property PHACC_WIDTH TYPE INTEGER
|
||||
set_parameter_property PHACC_WIDTH UNITS None
|
||||
set_parameter_property PHACC_WIDTH ALLOWED_RANGES -2147483648:2147483647
|
||||
set_parameter_property PHACC_WIDTH HDL_PARAMETER true
|
||||
|
||||
|
||||
#
|
||||
# display items
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# connection point clock
|
||||
#
|
||||
add_interface clock clock end
|
||||
set_interface_property clock clockRate 0
|
||||
set_interface_property clock ENABLED true
|
||||
set_interface_property clock EXPORT_OF ""
|
||||
set_interface_property clock PORT_NAME_MAP ""
|
||||
set_interface_property clock CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property clock SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port clock clk clk Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point reset_sink
|
||||
#
|
||||
add_interface reset_sink reset end
|
||||
set_interface_property reset_sink associatedClock clock
|
||||
set_interface_property reset_sink synchronousEdges DEASSERT
|
||||
set_interface_property reset_sink ENABLED true
|
||||
set_interface_property reset_sink EXPORT_OF ""
|
||||
set_interface_property reset_sink PORT_NAME_MAP ""
|
||||
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property reset_sink SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port reset_sink clr_n reset_n Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point conduit_end
|
||||
#
|
||||
add_interface conduit_end conduit end
|
||||
set_interface_property conduit_end associatedClock ""
|
||||
set_interface_property conduit_end associatedReset ""
|
||||
set_interface_property conduit_end ENABLED true
|
||||
set_interface_property conduit_end EXPORT_OF ""
|
||||
set_interface_property conduit_end PORT_NAME_MAP ""
|
||||
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property conduit_end SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port conduit_end fout writeresponsevalid_n Output 1
|
||||
|
||||
|
||||
#
|
||||
# connection point avalon_slave
|
||||
#
|
||||
add_interface avalon_slave avalon end
|
||||
set_interface_property avalon_slave addressUnits WORDS
|
||||
set_interface_property avalon_slave associatedClock clock
|
||||
set_interface_property avalon_slave associatedReset reset_sink
|
||||
set_interface_property avalon_slave bitsPerSymbol 8
|
||||
set_interface_property avalon_slave burstOnBurstBoundariesOnly false
|
||||
set_interface_property avalon_slave burstcountUnits WORDS
|
||||
set_interface_property avalon_slave explicitAddressSpan 0
|
||||
set_interface_property avalon_slave holdTime 0
|
||||
set_interface_property avalon_slave linewrapBursts false
|
||||
set_interface_property avalon_slave maximumPendingReadTransactions 0
|
||||
set_interface_property avalon_slave maximumPendingWriteTransactions 0
|
||||
set_interface_property avalon_slave readLatency 0
|
||||
set_interface_property avalon_slave readWaitTime 1
|
||||
set_interface_property avalon_slave setupTime 0
|
||||
set_interface_property avalon_slave timingUnits Cycles
|
||||
set_interface_property avalon_slave writeWaitTime 0
|
||||
set_interface_property avalon_slave ENABLED true
|
||||
set_interface_property avalon_slave EXPORT_OF ""
|
||||
set_interface_property avalon_slave PORT_NAME_MAP ""
|
||||
set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port avalon_slave wr_n write_n Input 1
|
||||
add_interface_port avalon_slave wr_data writedata Input 32
|
||||
set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
|
||||
set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
|
||||
set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
|
||||
set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
|
||||
|
||||
59
Top/top.sv
59
Top/top.sv
|
|
@ -1,20 +1,53 @@
|
|||
module top
|
||||
//(
|
||||
// input logic clk,
|
||||
// input logic train,
|
||||
// output logic green,
|
||||
// output logic red,
|
||||
// output logic yellow
|
||||
//);
|
||||
//
|
||||
// niosII u0 (
|
||||
// .clk_clk (clk), // clk.clk
|
||||
// .reset_reset_n (1'b1), // reset.reset_n
|
||||
// .sem_export_train (~train), // sem_export.train
|
||||
// .sem_export_red (red), // .red
|
||||
// .sem_export_yellow (yellow), // .yellow
|
||||
// .sem_export_green (green) // .green
|
||||
// );
|
||||
|
||||
(
|
||||
input logic clk,
|
||||
input logic train,
|
||||
output logic green,
|
||||
output logic red,
|
||||
output logic yellow
|
||||
|
||||
//////////// CLOCK //////////
|
||||
CLOCK_50,
|
||||
CLOCK2_50,
|
||||
CLOCK3_50,
|
||||
|
||||
//////////// LED //////////
|
||||
LEDG,
|
||||
LEDR,
|
||||
FOUTA
|
||||
);
|
||||
|
||||
niosII u0 (
|
||||
.clk_clk (clk), // clk.clk
|
||||
.reset_reset_n (1'b1), // reset.reset_n
|
||||
.sem_export_train (~train), // sem_export.train
|
||||
.sem_export_red (red), // .red
|
||||
.sem_export_yellow (yellow), // .yellow
|
||||
.sem_export_green (green) // .green
|
||||
|
||||
output FOUTA;
|
||||
//////////// CLOCK //////////
|
||||
input CLOCK_50;
|
||||
input CLOCK2_50;
|
||||
input CLOCK3_50;
|
||||
|
||||
//////////// LED //////////
|
||||
output [8:0] LEDG;
|
||||
output [17:0] LEDR;
|
||||
|
||||
niosII u0 (
|
||||
.clk_clk (CLOCK_50), // clk.clk
|
||||
.conduit_end_writeresponsevalid_n (LEDG[0]), // conduit_end.writeresponsevalid_n
|
||||
.reset_reset_n (1'b1) // reset.reset_n
|
||||
);
|
||||
|
||||
|
||||
assign LEDG[7:1] = 1'b0;
|
||||
assign LEDR[17:0] = 1'b0;
|
||||
assign FOUTA = LEDG[0];
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue