fpga-lab-2/HDL/sdmod.sv

24 lines
448 B
Systemverilog

module sdmod (
input signed [7:0] val,
input clk,
input reset,
output daco
);
logic out;
logic signed [7:0] eps;
logic signed [7:0] un;
always_ff @(posedge clk, negedge reset) begin
if (~reset) begin
un <= 8'd0;
end else begin
un <= val - eps;
end
end
assign out = (un >= $signed(8'd0)) ? 1'd1 : 1'd0;
assign eps = (un >= $signed(8'd0)) ? $signed(8'd126) - un : $signed(-8'd126) - un;
assign daco = out;
endmodule