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fpga-lab-2
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Ivan I. Ovchinnikov dad79c26fb wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
HDL wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
Testbench wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
Top wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
.gitignore wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00