fpga-lab-2/Top
Ivan I. Ovchinnikov dad79c26fb wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
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niosII wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
software wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00
.gitignore done in hardware 2023-01-24 12:46:22 +03:00
Semafor_hw.tcl simulated individual, looks ok 2022-12-24 02:08:20 +03:00
Semafor_hw.tcl~ simulated individual, looks ok 2022-12-24 02:08:20 +03:00
niosII.qsys wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII.sopcinfo wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_tb.csv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_tb.spd wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
semafor.qpf done in hardware 2023-01-24 12:46:22 +03:00
semafor.qsf wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
semafor.qws wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
semafor_assignment_defaults.qdf done in hardware 2023-01-24 12:46:22 +03:00
sigdel_hw.tcl wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
top.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00