fpga-lab-2/HDL/IP/sinelut.qip

6 lines
350 B
Plaintext
Raw Normal View History

2023-01-27 11:15:11 +03:00
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sinelut.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sinelut_bb.v"]