fpga-lab-2/Top/top.sv

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Systemverilog
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2023-01-24 12:46:22 +03:00
module top
(
input logic clk,
input logic train,
output logic green,
output logic red,
output logic yellow
);
niosII u0 (
.clk_clk (clk), // clk.clk
.reset_reset_n (1'b1), // reset.reset_n
.sem_export_train (~train), // sem_export.train
.sem_export_red (red), // .red
.sem_export_yellow (yellow), // .yellow
.sem_export_green (green) // .green
);
endmodule