fpga-lab-2/Top/niosII/niosII.cmp

	component niosII is
		port (
			clk_clk                          : in  std_logic := 'X'; -- clk
			conduit_end_writeresponsevalid_n : out std_logic;        -- writeresponsevalid_n
			reset_reset_n                    : in  std_logic := 'X'  -- reset_n
		);
	end component niosII;