fpga-lab-2/Top/niosII_tb.spd

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<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file
path="niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv"
type="SYSTEM_VERILOG"
library="altera_common_sv_packages"
systemVerilogPackageName="avalon_vip_verbosity_pkg" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex"
type="HEX"
library="mem" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v"
type="VERILOG"
library="mem" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v"
type="VERILOG"
library="jtag_uart" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv"
type="SYSTEM_VERILOG"
library="niosII_inst_reset_bfm" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv"
type="SYSTEM_VERILOG"
library="niosII_inst_clk_bfm" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII.v"
type="VERILOG"
library="niosII_inst" />
<file
path="niosII/testbench/niosII_tb/simulation/niosII_tb.v"
type="VERILOG" />
<topLevel name="niosII_tb" />
<deviceFamily name="cycloneive" />
<modelMap
controllerPath="niosII_tb.niosII_inst.mem"
modelPath="niosII_tb.niosII_inst.mem" />
</simPackage>