45 lines
1.4 KiB
XML
45 lines
1.4 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<simPackage>
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<file
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path="niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv"
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type="SYSTEM_VERILOG"
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library="altera_common_sv_packages"
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systemVerilogPackageName="avalon_vip_verbosity_pkg" />
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<file
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path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex"
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type="HEX"
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library="mem" />
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<file
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path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v"
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type="VERILOG"
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library="mem" />
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<file
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path="niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v"
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type="VERILOG"
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library="jtag_uart" />
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<file
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path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v"
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type="VERILOG"
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library="cpu" />
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<file
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path="niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv"
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type="SYSTEM_VERILOG"
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library="niosII_inst_reset_bfm" />
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<file
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path="niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv"
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type="SYSTEM_VERILOG"
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library="niosII_inst_clk_bfm" />
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<file
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path="niosII/testbench/niosII_tb/simulation/submodules/niosII.v"
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type="VERILOG"
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library="niosII_inst" />
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<file
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path="niosII/testbench/niosII_tb/simulation/niosII_tb.v"
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type="VERILOG" />
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<topLevel name="niosII_tb" />
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<deviceFamily name="cycloneive" />
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<modelMap
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controllerPath="niosII_tb.niosII_inst.mem"
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modelPath="niosII_tb.niosII_inst.mem" />
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</simPackage>
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