fpga-lab-2/HDL/IP/periodram.qip

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2023-01-24 12:46:22 +03:00
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "periodram.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "periodram_inst.v"]