38 lines
723 B
Systemverilog
38 lines
723 B
Systemverilog
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//top-level module
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module sigdel
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#(
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PHACC_WIDTH = 14
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) (
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//clock and reset
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input logic clk, clr_n,
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//control slave
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input logic [31:0] wr_data,
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input logic wr_n,
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output logic fout
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);
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logic [7:0] phinc_val;
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//control slave logic
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always_ff @ (posedge clk or negedge clr_n) begin
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if (!clr_n) begin
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phinc_val[7:0] <= 8'd0;
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end else begin
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if (!wr_n) begin
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phinc_val[7:0] <= wr_data[31:0];
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end
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end
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end
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phacc phacc_inst (.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
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defparam phacc_inst.WIDTH = PHACC_WIDTH;
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sinelut sinelut_inst (
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.address (phase), .clock (clk), .q(sine)
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);
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sdmod sdmod_inst (
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.val(sine), .clk(clk), .reset(clr_n), .daco(fout)
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);
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endmodule
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