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pt2 done, qsys added, compiled successfully

This commit is contained in:
Ivan I. Ovchinnikov 2022-10-19 13:25:43 +03:00
parent f331b13121
commit 56257bbcaf
57 changed files with 80331 additions and 51 deletions
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# TCL File Generated by Component Editor 18.1
# Wed Oct 19 14:12:17 MSK 2022
# DO NOT MODIFY
#
# Semafor "Semafor" v1.0
# 2022.10.19.14:12:17
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module Semafor
#
set_module_property DESCRIPTION ""
set_module_property NAME Semafor
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "User Logic"
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME Semafor
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL dec
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv TOP_LEVEL_FILE
add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
#
# parameters
#
add_parameter m INTEGER 8
set_parameter_property m DEFAULT_VALUE 8
set_parameter_property m DISPLAY_NAME m
set_parameter_property m TYPE INTEGER
set_parameter_property m UNITS None
set_parameter_property m HDL_PARAMETER true
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point ctl_slave
#
add_interface ctl_slave avalon end
set_interface_property ctl_slave addressUnits WORDS
set_interface_property ctl_slave associatedClock clock
set_interface_property ctl_slave associatedReset reset_n
set_interface_property ctl_slave bitsPerSymbol 8
set_interface_property ctl_slave burstOnBurstBoundariesOnly false
set_interface_property ctl_slave burstcountUnits WORDS
set_interface_property ctl_slave explicitAddressSpan 0
set_interface_property ctl_slave holdTime 0
set_interface_property ctl_slave linewrapBursts false
set_interface_property ctl_slave maximumPendingReadTransactions 0
set_interface_property ctl_slave maximumPendingWriteTransactions 0
set_interface_property ctl_slave readLatency 0
set_interface_property ctl_slave readWaitStates 0
set_interface_property ctl_slave readWaitTime 0
set_interface_property ctl_slave setupTime 0
set_interface_property ctl_slave timingUnits Cycles
set_interface_property ctl_slave writeWaitTime 0
set_interface_property ctl_slave ENABLED true
set_interface_property ctl_slave EXPORT_OF ""
set_interface_property ctl_slave PORT_NAME_MAP ""
set_interface_property ctl_slave CMSIS_SVD_VARIABLES ""
set_interface_property ctl_slave SVD_ADDRESS_GROUP ""
add_interface_port ctl_slave ctl_wr write Input 1
add_interface_port ctl_slave ctl_rd read Input 1
add_interface_port ctl_slave ctl_addr address Input 1
add_interface_port ctl_slave ctl_wrdata writedata Input 32
add_interface_port ctl_slave ctl_rddata readdata Output 32
set_interface_assignment ctl_slave embeddedsw.configuration.isFlash 0
set_interface_assignment ctl_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment ctl_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment ctl_slave embeddedsw.configuration.isPrintableDevice 0
#
# connection point reset_n
#
add_interface reset_n reset end
set_interface_property reset_n associatedClock clock
set_interface_property reset_n synchronousEdges DEASSERT
set_interface_property reset_n ENABLED true
set_interface_property reset_n EXPORT_OF ""
set_interface_property reset_n PORT_NAME_MAP ""
set_interface_property reset_n CMSIS_SVD_VARIABLES ""
set_interface_property reset_n SVD_ADDRESS_GROUP ""
add_interface_port reset_n clrn reset_n Input 1
#
# connection point ram_slave
#
add_interface ram_slave avalon end
set_interface_property ram_slave addressUnits WORDS
set_interface_property ram_slave associatedClock clock
set_interface_property ram_slave associatedReset reset_n
set_interface_property ram_slave bitsPerSymbol 8
set_interface_property ram_slave burstOnBurstBoundariesOnly false
set_interface_property ram_slave burstcountUnits WORDS
set_interface_property ram_slave explicitAddressSpan 0
set_interface_property ram_slave holdTime 0
set_interface_property ram_slave linewrapBursts false
set_interface_property ram_slave maximumPendingReadTransactions 0
set_interface_property ram_slave maximumPendingWriteTransactions 0
set_interface_property ram_slave readLatency 0
set_interface_property ram_slave readWaitTime 1
set_interface_property ram_slave setupTime 0
set_interface_property ram_slave timingUnits Cycles
set_interface_property ram_slave writeWaitTime 0
set_interface_property ram_slave ENABLED true
set_interface_property ram_slave EXPORT_OF ""
set_interface_property ram_slave PORT_NAME_MAP ""
set_interface_property ram_slave CMSIS_SVD_VARIABLES ""
set_interface_property ram_slave SVD_ADDRESS_GROUP ""
add_interface_port ram_slave ram_wr write Input 1
add_interface_port ram_slave ram_addr address Input 2
add_interface_port ram_slave ram_wrdata writedata Input 32
set_interface_assignment ram_slave embeddedsw.configuration.isFlash 0
set_interface_assignment ram_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment ram_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment ram_slave embeddedsw.configuration.isPrintableDevice 0
#
# connection point sem
#
add_interface sem conduit end
set_interface_property sem associatedClock ""
set_interface_property sem associatedReset reset_n
set_interface_property sem ENABLED true
set_interface_property sem EXPORT_OF ""
set_interface_property sem PORT_NAME_MAP ""
set_interface_property sem CMSIS_SVD_VARIABLES ""
set_interface_property sem SVD_ADDRESS_GROUP ""
add_interface_port sem train train Input 1
add_interface_port sem red red Output 1
add_interface_port sem yellow yellow Output 1
add_interface_port sem green green Output 1

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*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.1"))
(symbol (symbol
(rect 0 0 224 144) (rect 0 0 288 232)
(text "niosII" (rect 98 -1 118 11)(font "Arial" (font_size 10))) (text "niosII" (rect 130 -1 150 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 128 20 140)(font "Arial" )) (text "inst" (rect 8 216 20 228)(font "Arial" ))
(port (port
(pt 0 72) (pt 0 72)
(input) (input)
(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8))) (text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8))) (text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 80 72)(line_width 1)) (line (pt 0 72)(pt 112 72)(line_width 1))
) )
(port (port
(pt 0 112) (pt 0 112)
(input) (input)
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8))) (text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
(text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8))) (text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 80 112)(line_width 1)) (line (pt 0 112)(pt 112 112)(line_width 1))
)
(port
(pt 0 152)
(input)
(text "sem_export_train" (rect 0 0 70 12)(font "Arial" (font_size 8)))
(text "sem_export_train" (rect 4 141 100 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 112 152)(line_width 1))
)
(port
(pt 0 168)
(output)
(text "sem_export_red" (rect 0 0 67 12)(font "Arial" (font_size 8)))
(text "sem_export_red" (rect 4 157 88 168)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 112 168)(line_width 1))
)
(port
(pt 0 184)
(output)
(text "sem_export_yellow" (rect 0 0 77 12)(font "Arial" (font_size 8)))
(text "sem_export_yellow" (rect 4 173 106 184)(font "Arial" (font_size 8)))
(line (pt 0 184)(pt 112 184)(line_width 1))
)
(port
(pt 0 200)
(output)
(text "sem_export_green" (rect 0 0 76 12)(font "Arial" (font_size 8)))
(text "sem_export_green" (rect 4 189 100 200)(font "Arial" (font_size 8)))
(line (pt 0 200)(pt 112 200)(line_width 1))
) )
(drawing (drawing
(text "clk" (rect 65 43 148 99)(font "Arial" (color 128 0 0)(font_size 9))) (text "clk" (rect 97 43 212 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 85 67 188 144)(font "Arial" (color 0 0 0))) (text "clk" (rect 117 67 252 144)(font "Arial" (color 0 0 0)))
(text "reset" (rect 51 83 132 179)(font "Arial" (color 128 0 0)(font_size 9))) (text "reset" (rect 83 83 196 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 85 107 212 224)(font "Arial" (color 0 0 0))) (text "reset_n" (rect 117 107 276 224)(font "Arial" (color 0 0 0)))
(text " system " (rect 189 128 426 266)(font "Arial" )) (text "sem_export" (rect 44 123 148 259)(font "Arial" (color 128 0 0)(font_size 9)))
(line (pt 80 32)(pt 144 32)(line_width 1)) (text "train" (rect 117 147 264 304)(font "Arial" (color 0 0 0)))
(line (pt 144 32)(pt 144 128)(line_width 1)) (text "red" (rect 117 163 252 336)(font "Arial" (color 0 0 0)))
(line (pt 80 128)(pt 144 128)(line_width 1)) (text "yellow" (rect 117 179 270 368)(font "Arial" (color 0 0 0)))
(line (pt 80 32)(pt 80 128)(line_width 1)) (text "green" (rect 117 195 264 400)(font "Arial" (color 0 0 0)))
(line (pt 81 52)(pt 81 76)(line_width 1)) (text " niosII " (rect 262 216 572 442)(font "Arial" ))
(line (pt 82 52)(pt 82 76)(line_width 1)) (line (pt 112 32)(pt 176 32)(line_width 1))
(line (pt 81 92)(pt 81 116)(line_width 1)) (line (pt 176 32)(pt 176 216)(line_width 1))
(line (pt 82 92)(pt 82 116)(line_width 1)) (line (pt 112 216)(pt 176 216)(line_width 1))
(line (pt 0 0)(pt 224 0)(line_width 1)) (line (pt 112 32)(pt 112 216)(line_width 1))
(line (pt 224 0)(pt 224 144)(line_width 1)) (line (pt 113 52)(pt 113 76)(line_width 1))
(line (pt 0 144)(pt 224 144)(line_width 1)) (line (pt 114 52)(pt 114 76)(line_width 1))
(line (pt 0 0)(pt 0 144)(line_width 1)) (line (pt 113 92)(pt 113 116)(line_width 1))
(line (pt 114 92)(pt 114 116)(line_width 1))
(line (pt 113 132)(pt 113 204)(line_width 1))
(line (pt 114 132)(pt 114 204)(line_width 1))
(line (pt 0 0)(pt 288 0)(line_width 1))
(line (pt 288 0)(pt 288 232)(line_width 1))
(line (pt 0 232)(pt 288 232)(line_width 1))
(line (pt 0 0)(pt 0 232)(line_width 1))
) )
) )

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component niosII is component niosII is
port ( port (
clk_clk : in std_logic := 'X'; -- clk clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X' -- reset_n reset_reset_n : in std_logic := 'X'; -- reset_n
sem_export_train : in std_logic := 'X'; -- train
sem_export_red : out std_logic; -- red
sem_export_yellow : out std_logic; -- yellow
sem_export_green : out std_logic -- green
); );
end component niosII; end component niosII;

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module niosII ( module niosII (
clk_clk, clk_clk,
reset_reset_n); reset_reset_n,
sem_export_train,
sem_export_red,
sem_export_yellow,
sem_export_green);
input clk_clk; input clk_clk;
input reset_reset_n; input reset_reset_n;
input sem_export_train;
output sem_export_red;
output sem_export_yellow;
output sem_export_green;
endmodule endmodule

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Top/niosII/niosII_inst.v
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niosII u0 ( niosII u0 (
.clk_clk (<connected-to-clk_clk>), // clk.clk .clk_clk (<connected-to-clk_clk>), // clk.clk
.reset_reset_n (<connected-to-reset_reset_n>) // reset.reset_n .reset_reset_n (<connected-to-reset_reset_n>), // reset.reset_n
.sem_export_train (<connected-to-sem_export_train>), // sem_export.train
.sem_export_red (<connected-to-sem_export_red>), // .red
.sem_export_yellow (<connected-to-sem_export_yellow>), // .yellow
.sem_export_green (<connected-to-sem_export_green>) // .green
); );

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component niosII is component niosII is
port ( port (
clk_clk : in std_logic := 'X'; -- clk clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X' -- reset_n reset_reset_n : in std_logic := 'X'; -- reset_n
sem_export_train : in std_logic := 'X'; -- train
sem_export_red : out std_logic; -- red
sem_export_yellow : out std_logic; -- yellow
sem_export_green : out std_logic -- green
); );
end component niosII; end component niosII;
u0 : component niosII u0 : component niosII
port map ( port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sem_export_train => CONNECTED_TO_sem_export_train, -- sem_export.train
sem_export_red => CONNECTED_TO_sem_export_red, -- .red
sem_export_yellow => CONNECTED_TO_sem_export_yellow, -- .yellow
sem_export_green => CONNECTED_TO_sem_export_green -- .green
); );

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<?xml version="1.0"?>
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
<name>niosII</name>
<peripherals>
<peripheral>
<name>niosII_sys_clk_timer_s1_altera_avalon_timer</name><baseAddress>0x00000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>16</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>status</name>
<displayName>Status</displayName>
<description>The status register has two defined bits. TO (timeout), RUN</description>
<addressOffset>0x0</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffff</resetMask>
<fields>
<field><name>TO</name>
<description>The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<readAction>clear</readAction>
</field>
<field><name>RUN</name>
<description>The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by
a write operation to the status register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
<access>read-write</access>
<parameters>
<parameter>
<name>Reserved</name>
<value>true</value>
</parameter>
</parameters>
</field>
</fields>
</register>
<register>
<name>control</name>
<description>The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP</description>
<addressOffset>0x1</addressOffset>
<size>16</size>
<access>read-write</access>
<reset>
<value>0x0</value>
</reset>
<field>
<name>ITO</name>
<description>If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CONT</name>
<description>The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>START</name>
<description>Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>STOP</name>
<description>Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<access>read-write</access>
<parameters>
<parameter>
<name>Reserved</name>
<value>true</value>
</parameter>
</parameters>
</field>
</register>
<register>
<name>${period_name_0}</name>
<description>The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.</description>
<addressOffset>0x2</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>${period_name_0_reset_value}</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${period_name_1}</name>
<description></description>
<addressOffset>0x3</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>${period_name_1_reset_value}</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${period_snap_0}</name>
<description></description>
<addressOffset>0x4</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>${period_snap_0_reset_value}</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${period_snap_1}</name>
<description></description>
<addressOffset>0x5</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>${period_snap_1_reset_value}</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${snap_0}</name>
<description>A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.</description>
<addressOffset>0x6</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${snap_1}</name>
<description></description>
<addressOffset>0x7</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${snap_2}</name>
<description></description>
<addressOffset>0x8</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${snap_3}</name>
<description></description>
<addressOffset>0x9</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffff</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>niosII_jtag_uart_avalon_jtag_slave_altera_avalon_jtag_uart</name><baseAddress>0x00000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>8</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DATA</name>
<displayName>Data</displayName>
<description>Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>data</name>
<description>The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field><name>rvalid</name>
<description>Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.</description>
<bitOffset>0xf</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field><name>ravail</name>
<description>The number of characters remaining in the read FIFO (after the current read).</description>
<bitOffset>0x10</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CONTROL</name>
<displayName>Control</displayName>
<description>Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>re</name>
<description>Interrupt-enable bit for read interrupts.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field><name>we</name>
<description>Interrupt-enable bit for write interrupts</description>
<bitOffset>0x1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field><name>ri</name>
<description>Indicates that the read interrupt is pending.</description>
<bitOffset>0x8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field><name>wi</name>
<description>Indicates that the write interrupt is pending.</description>
<bitOffset>0x9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field><name>ac</name>
<description>Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.</description>
<bitOffset>0xa</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field><name>wspace</name>
<description>The number of spaces available in the write FIFO</description>
<bitOffset>0x10</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>

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// niosII.v
// Generated using ACDS version 18.1 625
`timescale 1 ps / 1 ps
module niosII (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
input wire sem_export_train, // sem_export.train
output wire sem_export_red, // .red
output wire sem_export_yellow, // .yellow
output wire sem_export_green // .green
);
wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata
wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest
wire cpu_data_master_debugaccess; // cpu:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess
wire [17:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address
wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable
wire cpu_data_master_read; // cpu:d_read -> mm_interconnect_0:cpu_data_master_read
wire cpu_data_master_write; // cpu:d_write -> mm_interconnect_0:cpu_data_master_write
wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata
wire [31:0] cpu_instruction_master_readdata; // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata
wire cpu_instruction_master_waitrequest; // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest
wire [17:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address
wire cpu_instruction_master_read; // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire [31:0] mm_interconnect_0_sem_ctl_slave_readdata; // sem:ctl_rddata -> mm_interconnect_0:sem_ctl_slave_readdata
wire [0:0] mm_interconnect_0_sem_ctl_slave_address; // mm_interconnect_0:sem_ctl_slave_address -> sem:ctl_addr
wire mm_interconnect_0_sem_ctl_slave_read; // mm_interconnect_0:sem_ctl_slave_read -> sem:ctl_rd
wire mm_interconnect_0_sem_ctl_slave_write; // mm_interconnect_0:sem_ctl_slave_write -> sem:ctl_wr
wire [31:0] mm_interconnect_0_sem_ctl_slave_writedata; // mm_interconnect_0:sem_ctl_slave_writedata -> sem:ctl_wrdata
wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_readdata; // cpu:debug_mem_slave_readdata -> mm_interconnect_0:cpu_debug_mem_slave_readdata
wire mm_interconnect_0_cpu_debug_mem_slave_waitrequest; // cpu:debug_mem_slave_waitrequest -> mm_interconnect_0:cpu_debug_mem_slave_waitrequest
wire mm_interconnect_0_cpu_debug_mem_slave_debugaccess; // mm_interconnect_0:cpu_debug_mem_slave_debugaccess -> cpu:debug_mem_slave_debugaccess
wire [8:0] mm_interconnect_0_cpu_debug_mem_slave_address; // mm_interconnect_0:cpu_debug_mem_slave_address -> cpu:debug_mem_slave_address
wire mm_interconnect_0_cpu_debug_mem_slave_read; // mm_interconnect_0:cpu_debug_mem_slave_read -> cpu:debug_mem_slave_read
wire [3:0] mm_interconnect_0_cpu_debug_mem_slave_byteenable; // mm_interconnect_0:cpu_debug_mem_slave_byteenable -> cpu:debug_mem_slave_byteenable
wire mm_interconnect_0_cpu_debug_mem_slave_write; // mm_interconnect_0:cpu_debug_mem_slave_write -> cpu:debug_mem_slave_write
wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_writedata; // mm_interconnect_0:cpu_debug_mem_slave_writedata -> cpu:debug_mem_slave_writedata
wire [1:0] mm_interconnect_0_sem_ram_slave_address; // mm_interconnect_0:sem_ram_slave_address -> sem:ram_addr
wire mm_interconnect_0_sem_ram_slave_write; // mm_interconnect_0:sem_ram_slave_write -> sem:ram_wr
wire [31:0] mm_interconnect_0_sem_ram_slave_writedata; // mm_interconnect_0:sem_ram_slave_writedata -> sem:ram_wrdata
wire mm_interconnect_0_sys_clk_timer_s1_chipselect; // mm_interconnect_0:sys_clk_timer_s1_chipselect -> sys_clk_timer:chipselect
wire [15:0] mm_interconnect_0_sys_clk_timer_s1_readdata; // sys_clk_timer:readdata -> mm_interconnect_0:sys_clk_timer_s1_readdata
wire [2:0] mm_interconnect_0_sys_clk_timer_s1_address; // mm_interconnect_0:sys_clk_timer_s1_address -> sys_clk_timer:address
wire mm_interconnect_0_sys_clk_timer_s1_write; // mm_interconnect_0:sys_clk_timer_s1_write -> sys_clk_timer:write_n
wire [15:0] mm_interconnect_0_sys_clk_timer_s1_writedata; // mm_interconnect_0:sys_clk_timer_s1_writedata -> sys_clk_timer:writedata
wire mm_interconnect_0_mem_s2_chipselect; // mm_interconnect_0:mem_s2_chipselect -> mem:chipselect2
wire [31:0] mm_interconnect_0_mem_s2_readdata; // mem:readdata2 -> mm_interconnect_0:mem_s2_readdata
wire [14:0] mm_interconnect_0_mem_s2_address; // mm_interconnect_0:mem_s2_address -> mem:address2
wire [3:0] mm_interconnect_0_mem_s2_byteenable; // mm_interconnect_0:mem_s2_byteenable -> mem:byteenable2
wire mm_interconnect_0_mem_s2_write; // mm_interconnect_0:mem_s2_write -> mem:write2
wire [31:0] mm_interconnect_0_mem_s2_writedata; // mm_interconnect_0:mem_s2_writedata -> mem:writedata2
wire mm_interconnect_0_mem_s2_clken; // mm_interconnect_0:mem_s2_clken -> mem:clken2
wire mm_interconnect_0_mem_s1_chipselect; // mm_interconnect_0:mem_s1_chipselect -> mem:chipselect
wire [31:0] mm_interconnect_0_mem_s1_readdata; // mem:readdata -> mm_interconnect_0:mem_s1_readdata
wire [14:0] mm_interconnect_0_mem_s1_address; // mm_interconnect_0:mem_s1_address -> mem:address
wire [3:0] mm_interconnect_0_mem_s1_byteenable; // mm_interconnect_0:mem_s1_byteenable -> mem:byteenable
wire mm_interconnect_0_mem_s1_write; // mm_interconnect_0:mem_s1_write -> mem:write
wire [31:0] mm_interconnect_0_mem_s1_writedata; // mm_interconnect_0:mem_s1_writedata -> mem:writedata
wire mm_interconnect_0_mem_s1_clken; // mm_interconnect_0:mem_s1_clken -> mem:clken
wire irq_mapper_receiver0_irq; // sys_clk_timer:irq -> irq_mapper:receiver0_irq
wire irq_mapper_receiver1_irq; // jtag_uart:av_irq -> irq_mapper:receiver1_irq
wire [31:0] cpu_irq_irq; // irq_mapper:sender_irq -> cpu:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [cpu:reset_n, irq_mapper:reset, jtag_uart:rst_n, mem:reset, mm_interconnect_0:cpu_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sem:clrn, sys_clk_timer:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [cpu:reset_req, mem:reset_req, rst_translator:reset_req_in]
wire cpu_debug_reset_request_reset; // cpu:debug_reset_request -> rst_controller:reset_in1
niosII_cpu cpu (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.d_address (cpu_data_master_address), // data_master.address
.d_byteenable (cpu_data_master_byteenable), // .byteenable
.d_read (cpu_data_master_read), // .read
.d_readdata (cpu_data_master_readdata), // .readdata
.d_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.d_write (cpu_data_master_write), // .write
.d_writedata (cpu_data_master_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (cpu_data_master_debugaccess), // .debugaccess
.i_address (cpu_instruction_master_address), // instruction_master.address
.i_read (cpu_instruction_master_read), // .read
.i_readdata (cpu_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.irq (cpu_irq_irq), // irq.irq
.debug_reset_request (cpu_debug_reset_request_reset), // debug_reset_request.reset
.debug_mem_slave_address (mm_interconnect_0_cpu_debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (mm_interconnect_0_cpu_debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (mm_interconnect_0_cpu_debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (mm_interconnect_0_cpu_debug_mem_slave_read), // .read
.debug_mem_slave_readdata (mm_interconnect_0_cpu_debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (mm_interconnect_0_cpu_debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (mm_interconnect_0_cpu_debug_mem_slave_write), // .write
.debug_mem_slave_writedata (mm_interconnect_0_cpu_debug_mem_slave_writedata), // .writedata
.dummy_ci_port () // custom_instruction_master.readra
);
niosII_jtag_uart jtag_uart (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver1_irq) // irq.irq
);
niosII_mem mem (
.address (mm_interconnect_0_mem_s1_address), // s1.address
.clken (mm_interconnect_0_mem_s1_clken), // .clken
.chipselect (mm_interconnect_0_mem_s1_chipselect), // .chipselect
.write (mm_interconnect_0_mem_s1_write), // .write
.readdata (mm_interconnect_0_mem_s1_readdata), // .readdata
.writedata (mm_interconnect_0_mem_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_mem_s1_byteenable), // .byteenable
.address2 (mm_interconnect_0_mem_s2_address), // s2.address
.chipselect2 (mm_interconnect_0_mem_s2_chipselect), // .chipselect
.clken2 (mm_interconnect_0_mem_s2_clken), // .clken
.write2 (mm_interconnect_0_mem_s2_write), // .write
.readdata2 (mm_interconnect_0_mem_s2_readdata), // .readdata
.writedata2 (mm_interconnect_0_mem_s2_writedata), // .writedata
.byteenable2 (mm_interconnect_0_mem_s2_byteenable), // .byteenable
.clk (clk_clk), // clk1.clk
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.freeze (1'b0) // (terminated)
);
dec #(
.m (8)
) sem (
.clk (clk_clk), // clock.clk
.ctl_wr (mm_interconnect_0_sem_ctl_slave_write), // ctl_slave.write
.ctl_rd (mm_interconnect_0_sem_ctl_slave_read), // .read
.ctl_addr (mm_interconnect_0_sem_ctl_slave_address), // .address
.ctl_wrdata (mm_interconnect_0_sem_ctl_slave_writedata), // .writedata
.ctl_rddata (mm_interconnect_0_sem_ctl_slave_readdata), // .readdata
.clrn (~rst_controller_reset_out_reset), // reset_n.reset_n
.ram_wr (mm_interconnect_0_sem_ram_slave_write), // ram_slave.write
.ram_addr (mm_interconnect_0_sem_ram_slave_address), // .address
.ram_wrdata (mm_interconnect_0_sem_ram_slave_writedata), // .writedata
.train (sem_export_train), // sem.train
.red (sem_export_red), // .red
.yellow (sem_export_yellow), // .yellow
.green (sem_export_green) // .green
);
niosII_sys_clk_timer sys_clk_timer (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sys_clk_timer_s1_address), // s1.address
.writedata (mm_interconnect_0_sys_clk_timer_s1_writedata), // .writedata
.readdata (mm_interconnect_0_sys_clk_timer_s1_readdata), // .readdata
.chipselect (mm_interconnect_0_sys_clk_timer_s1_chipselect), // .chipselect
.write_n (~mm_interconnect_0_sys_clk_timer_s1_write), // .write_n
.irq (irq_mapper_receiver0_irq) // irq.irq
);
niosII_mm_interconnect_0 mm_interconnect_0 (
.clk_clk_clk (clk_clk), // clk_clk.clk
.cpu_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // cpu_reset_reset_bridge_in_reset.reset
.cpu_data_master_address (cpu_data_master_address), // cpu_data_master.address
.cpu_data_master_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.cpu_data_master_byteenable (cpu_data_master_byteenable), // .byteenable
.cpu_data_master_read (cpu_data_master_read), // .read
.cpu_data_master_readdata (cpu_data_master_readdata), // .readdata
.cpu_data_master_write (cpu_data_master_write), // .write
.cpu_data_master_writedata (cpu_data_master_writedata), // .writedata
.cpu_data_master_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.cpu_instruction_master_address (cpu_instruction_master_address), // cpu_instruction_master.address
.cpu_instruction_master_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.cpu_instruction_master_read (cpu_instruction_master_read), // .read
.cpu_instruction_master_readdata (cpu_instruction_master_readdata), // .readdata
.cpu_debug_mem_slave_address (mm_interconnect_0_cpu_debug_mem_slave_address), // cpu_debug_mem_slave.address
.cpu_debug_mem_slave_write (mm_interconnect_0_cpu_debug_mem_slave_write), // .write
.cpu_debug_mem_slave_read (mm_interconnect_0_cpu_debug_mem_slave_read), // .read
.cpu_debug_mem_slave_readdata (mm_interconnect_0_cpu_debug_mem_slave_readdata), // .readdata
.cpu_debug_mem_slave_writedata (mm_interconnect_0_cpu_debug_mem_slave_writedata), // .writedata
.cpu_debug_mem_slave_byteenable (mm_interconnect_0_cpu_debug_mem_slave_byteenable), // .byteenable
.cpu_debug_mem_slave_waitrequest (mm_interconnect_0_cpu_debug_mem_slave_waitrequest), // .waitrequest
.cpu_debug_mem_slave_debugaccess (mm_interconnect_0_cpu_debug_mem_slave_debugaccess), // .debugaccess
.jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address
.jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write
.jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read
.jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.mem_s1_address (mm_interconnect_0_mem_s1_address), // mem_s1.address
.mem_s1_write (mm_interconnect_0_mem_s1_write), // .write
.mem_s1_readdata (mm_interconnect_0_mem_s1_readdata), // .readdata
.mem_s1_writedata (mm_interconnect_0_mem_s1_writedata), // .writedata
.mem_s1_byteenable (mm_interconnect_0_mem_s1_byteenable), // .byteenable
.mem_s1_chipselect (mm_interconnect_0_mem_s1_chipselect), // .chipselect
.mem_s1_clken (mm_interconnect_0_mem_s1_clken), // .clken
.mem_s2_address (mm_interconnect_0_mem_s2_address), // mem_s2.address
.mem_s2_write (mm_interconnect_0_mem_s2_write), // .write
.mem_s2_readdata (mm_interconnect_0_mem_s2_readdata), // .readdata
.mem_s2_writedata (mm_interconnect_0_mem_s2_writedata), // .writedata
.mem_s2_byteenable (mm_interconnect_0_mem_s2_byteenable), // .byteenable
.mem_s2_chipselect (mm_interconnect_0_mem_s2_chipselect), // .chipselect
.mem_s2_clken (mm_interconnect_0_mem_s2_clken), // .clken
.sem_ctl_slave_address (mm_interconnect_0_sem_ctl_slave_address), // sem_ctl_slave.address
.sem_ctl_slave_write (mm_interconnect_0_sem_ctl_slave_write), // .write
.sem_ctl_slave_read (mm_interconnect_0_sem_ctl_slave_read), // .read
.sem_ctl_slave_readdata (mm_interconnect_0_sem_ctl_slave_readdata), // .readdata
.sem_ctl_slave_writedata (mm_interconnect_0_sem_ctl_slave_writedata), // .writedata
.sem_ram_slave_address (mm_interconnect_0_sem_ram_slave_address), // sem_ram_slave.address
.sem_ram_slave_write (mm_interconnect_0_sem_ram_slave_write), // .write
.sem_ram_slave_writedata (mm_interconnect_0_sem_ram_slave_writedata), // .writedata
.sys_clk_timer_s1_address (mm_interconnect_0_sys_clk_timer_s1_address), // sys_clk_timer_s1.address
.sys_clk_timer_s1_write (mm_interconnect_0_sys_clk_timer_s1_write), // .write
.sys_clk_timer_s1_readdata (mm_interconnect_0_sys_clk_timer_s1_readdata), // .readdata
.sys_clk_timer_s1_writedata (mm_interconnect_0_sys_clk_timer_s1_writedata), // .writedata
.sys_clk_timer_s1_chipselect (mm_interconnect_0_sys_clk_timer_s1_chipselect) // .chipselect
);
niosII_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.sender_irq (cpu_irq_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (cpu_debug_reset_request_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule

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Top/niosII/synthesis/submodules/altera_avalon_sc_fifo.v Normal file
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@ -0,0 +1,915 @@
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2010 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $
// $Revision: #3 $
// $Date: 2010/07/07 $
// $Author: jyeap $
/* -----------------------------------------------------------------------
Round-robin/fixed arbitration implementation.
Q: how do you find the least-significant set-bit in an n-bit binary number, X?
A: M = X & (~X + 1)
Example: X = 101000100
101000100 &
010111011 + 1 =
101000100 &
010111100 =
-----------
000000100
The method can be generalized to find the first set-bit
at a bit index no lower than bit-index N, simply by adding
2**N rather than 1.
Q: how does this relate to round-robin arbitration?
A:
Let X be the concatenation of all request signals.
Let the number to be added to X (hereafter called the
top_priority) initialize to 1, and be assigned from the
concatenation of the previous saved-grant, left-rotated
by one position, each time arbitration occurs. The
concatenation of grants is then M.
Problem: consider this case:
top_priority = 010000
request = 001001
~request + top_priority = 000110
next_grant = 000000 <- no one is granted!
There was no "set bit at a bit index no lower than bit-index 4", so
the result was 0.
We need to propagate the carry out from (~request + top_priority) to the LSB, so
that the sum becomes 000111, and next_grant is 000001. This operation could be
called a "circular add".
A bit of experimentation on the circular add reveals a significant amount of
delay in exiting and re-entering the carry chain - this will vary with device
family. Quartus also reports a combinational loop warning. Finally,
Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But
Modelsim _doesn't_ report a combinational loop!)
An alternate solution: concatenate the request vector with itself, and OR
corresponding bits from the top and bottom halves to determine next_grant.
Example:
top_priority = 010000
{request, request} = 001001 001001
{~request, ~request} + top_priority = 110111 000110
result of & operation = 000001 000000
next_grant = 000001
Notice that if request = 0, the sum operation will overflow, but we can ignore
this; the next_grant result is 0 (no one granted), as you might expect.
In the implementation, the last-granted value must be maintained as
a non-zero value - best probably simply not to update it when no requests
occur.
----------------------------------------------------------------------- */
`timescale 1 ns / 1 ns
module altera_merlin_arbitrator
#(
parameter NUM_REQUESTERS = 8,
// --------------------------------------
// Implemented schemes
// "round-robin"
// "fixed-priority"
// "no-arb"
// --------------------------------------
parameter SCHEME = "round-robin",
parameter PIPELINE = 0
)
(
input clk,
input reset,
// --------------------------------------
// Requests
// --------------------------------------
input [NUM_REQUESTERS-1:0] request,
// --------------------------------------
// Grants
// --------------------------------------
output [NUM_REQUESTERS-1:0] grant,
// --------------------------------------
// Control Signals
// --------------------------------------
input increment_top_priority,
input save_top_priority
);
// --------------------------------------
// Signals
// --------------------------------------
wire [NUM_REQUESTERS-1:0] top_priority;
reg [NUM_REQUESTERS-1:0] top_priority_reg;
reg [NUM_REQUESTERS-1:0] last_grant;
wire [2*NUM_REQUESTERS-1:0] result;
// --------------------------------------
// Scheme Selection
// --------------------------------------
generate
if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
assign top_priority = top_priority_reg;
end
else begin
// Fixed arbitration (or single-requester corner case)
assign top_priority = 1'b1;
end
endgenerate
// --------------------------------------
// Decision Logic
// --------------------------------------
altera_merlin_arb_adder
#(
.WIDTH (2 * NUM_REQUESTERS)
)
adder
(
.a ({ ~request, ~request }),
.b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
.sum (result)
);
generate if (SCHEME == "no-arb") begin
// --------------------------------------
// No arbitration: just wire request directly to grant
// --------------------------------------
assign grant = request;
end else begin
// Do the math in double-vector domain
wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
assign grant_double_vector = {request, request} & result;
// --------------------------------------
// Extract grant from the top and bottom halves
// of the double vector.
// --------------------------------------
assign grant =
grant_double_vector[NUM_REQUESTERS - 1 : 0] |
grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
end
endgenerate
// --------------------------------------
// Left-rotate the last grant vector to create top_priority.
// --------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
top_priority_reg <= 1'b1;
end
else begin
if (PIPELINE) begin
if (increment_top_priority) begin
top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1]} : top_priority_reg;
end
end else begin
if (increment_top_priority) begin
if (|request)
top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1] };
else
top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
end
else if (save_top_priority) begin
top_priority_reg <= grant;
end
end
end
end
endmodule
// ----------------------------------------------
// Adder for the standard arbitrator
// ----------------------------------------------
module altera_merlin_arb_adder
#(
parameter WIDTH = 8
)
(
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output [WIDTH-1:0] sum
);
wire [WIDTH:0] sum_lint;
// ----------------------------------------------
// Benchmarks indicate that for small widths, the full
// adder has higher fmax because synthesis can merge
// it with the mux, allowing partial decisions to be
// made early.
//
// The magic number is 4 requesters, which means an
// 8 bit adder.
// ----------------------------------------------
genvar i;
generate if (WIDTH <= 8) begin : full_adder
wire cout[WIDTH-1:0];
assign sum[0] = (a[0] ^ b[0]);
assign cout[0] = (a[0] & b[0]);
for (i = 1; i < WIDTH; i = i+1) begin : arb
assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
end
end else begin : carry_chain
assign sum_lint = a + b;
assign sum = sum_lint[WIDTH-1:0];
end
endgenerate
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// ------------------------------------------
// Merlin Burst Uncompressor
//
// Compressed read bursts -> uncompressed
// ------------------------------------------
`timescale 1 ns / 1 ns
module altera_merlin_burst_uncompressor
#(
parameter ADDR_W = 16,
parameter BURSTWRAP_W = 3,
parameter BYTE_CNT_W = 4,
parameter PKT_SYMBOLS = 4,
parameter BURST_SIZE_W = 3
)
(
input clk,
input reset,
// sink ST signals
input sink_startofpacket,
input sink_endofpacket,
input sink_valid,
output sink_ready,
// sink ST "data"
input [ADDR_W - 1: 0] sink_addr,
input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
input sink_is_compressed,
input [BURST_SIZE_W-1 : 0] sink_burstsize,
// source ST signals
output source_startofpacket,
output source_endofpacket,
output source_valid,
input source_ready,
// source ST "data"
output [ADDR_W - 1: 0] source_addr,
output [BURSTWRAP_W - 1 : 0] source_burstwrap,
output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
// Note: in the slave agent, the output should always be uncompressed. In
// other applications, it may be required to leave-compressed or not. How to
// control? Seems like a simple mux - pass-through if no uncompression is
// required.
output source_is_compressed,
output [BURST_SIZE_W-1 : 0] source_burstsize
);
//----------------------------------------------------
// AXSIZE decoding
//
// Turns the axsize value into the actual number of bytes
// being transferred.
// ---------------------------------------------------
function reg[63:0] bytes_in_transfer;
input [BURST_SIZE_W-1:0] axsize;
case (axsize)
4'b0000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
4'b0001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010;
4'b0010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100;
4'b0011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000;
4'b0100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000;
4'b0101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000;
4'b0110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000;
4'b0111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000;
4'b1000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000100000000;
4'b1001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000001000000000;
default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
endcase
endfunction
// num_symbols is PKT_SYMBOLS, appropriately sized.
wire [31:0] int_num_symbols = PKT_SYMBOLS;
wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
// def: Burst Compression. In a merlin network, a compressed burst is one
// which is transmitted in a single beat. Example: read burst. In
// constrast, an uncompressed burst (example: write burst) is transmitted in
// one beat per writedata item.
//
// For compressed bursts which require response packets, burst
// uncompression is required. Concrete example: a read burst of size 8
// occupies one response-fifo position. When that fifo position reaches the
// front of the FIFO, the slave starts providing the required 8 readdatavalid
// pulses. The 8 return response beats must be provided in a single packet,
// with incrementing address and decrementing byte_cnt fields. Upon receipt
// of the final readdata item of the burst, the response FIFO item is
// retired.
// Burst uncompression logic provides:
// a) 2-state FSM (idle, busy)
// reset to idle state
// transition to busy state for 2nd and subsequent rdv pulses
// - a single-cycle burst (aka non-burst read) causes no transition to
// busy state.
// b) response startofpacket/endofpacket logic. The response FIFO item
// will have sop asserted, and may have eop asserted. (In the case of
// multiple read bursts transmit in the command fabric in a single packet,
// the eop assertion will come in a later FIFO item.) To support packet
// conservation, and emit a well-formed packet on the response fabric,
// i) response fabric startofpacket is asserted only for the first resp.
// beat;
// ii) response fabric endofpacket is asserted only for the last resp.
// beat.
// c) response address field. The response address field contains an
// incrementing sequence, such that each readdata item is associated with
// its slave-map location. N.b. a) computing the address correctly requires
// knowledge of burstwrap behavior b) there may be no clients of the address
// field, which makes this field a good target for optimization. See
// burst_uncompress_address_counter below.
// d) response byte_cnt field. The response byte_cnt field contains a
// decrementing sequence, such that each beat of the response contains the
// count of bytes to follow. In the case of sub-bursts in a single packet,
// the byte_cnt field may decrement down to num_symbols, then back up to
// some value, multiple times in the packet.
reg burst_uncompress_busy;
reg [BYTE_CNT_W:0] burst_uncompress_byte_counter;
wire [BYTE_CNT_W-1:0] burst_uncompress_byte_counter_lint;
wire first_packet_beat;
wire last_packet_beat;
assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
assign burst_uncompress_byte_counter_lint = burst_uncompress_byte_counter[BYTE_CNT_W-1:0];
// First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to
// the output.
assign source_byte_cnt =
first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter_lint;
assign source_valid = sink_valid;
// Last packet beat is set throughout receipt of an uncompressed read burst
// from the response FIFO - this forces all the burst uncompression machinery
// idle.
assign last_packet_beat = ~sink_is_compressed |
(
burst_uncompress_busy ?
(sink_valid & (burst_uncompress_byte_counter_lint == num_symbols)) :
sink_valid & (sink_byte_cnt == num_symbols)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
burst_uncompress_busy <= '0;
burst_uncompress_byte_counter <= '0;
end
else begin
if (source_valid & source_ready & sink_valid) begin
// No matter what the current state, last_packet_beat leads to
// idle.
if (last_packet_beat) begin
burst_uncompress_busy <= '0;
burst_uncompress_byte_counter <= '0;
end
else begin
if (burst_uncompress_busy) begin
burst_uncompress_byte_counter <= (burst_uncompress_byte_counter > 0) ?
(burst_uncompress_byte_counter_lint - num_symbols) :
(sink_byte_cnt - num_symbols);
end
else begin // not busy, at least one more beat to go
burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols;
// To do: should busy go true for numsymbols-size compressed
// bursts?
burst_uncompress_busy <= 1'b1;
end
end
end
end
end
reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
wire [63:0] decoded_burstsize_wire;
wire [ADDR_W-1:0] decoded_burstsize;
localparam ADD_BURSTWRAP_W = (ADDR_W > BURSTWRAP_W) ? ADDR_W : BURSTWRAP_W;
wire [ADD_BURSTWRAP_W-1:0] addr_width_burstwrap;
// The input burstwrap value can be used as a mask against address values,
// but with one caveat: the address width may be (probably is) wider than
// the burstwrap width. The spec says: extend the msb of the burstwrap
// value out over the entire address width (but only if the address width
// actually is wider than the burstwrap width; otherwise it's a 0-width or
// negative range and concatenation multiplier).
generate
if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
// Sign-extend, just wires:
assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
{(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
assign addr_width_burstwrap[BURSTWRAP_W-1:0] = sink_burstwrap [BURSTWRAP_W-1:0];
end
else begin
assign addr_width_burstwrap[BURSTWRAP_W-1 : 0] = sink_burstwrap;
end
endgenerate
always @(posedge clk or posedge reset) begin
if (reset) begin
burst_uncompress_address_base <= '0;
end
else if (first_packet_beat & source_ready) begin
burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
end
end
assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits
assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed
wire [ADDR_W : 0] p1_burst_uncompress_address_offset =
(
(first_packet_beat ?
sink_addr :
burst_uncompress_address_offset) + decoded_burstsize
) &
addr_width_burstwrap[ADDR_W-1:0];
wire [ADDR_W-1:0] p1_burst_uncompress_address_offset_lint = p1_burst_uncompress_address_offset [ADDR_W-1:0];
always @(posedge clk or posedge reset) begin
if (reset) begin
burst_uncompress_address_offset <= '0;
end
else begin
if (source_ready & source_valid) begin
burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
// if (first_packet_beat) begin
// burst_uncompress_address_offset <=
// (sink_addr + num_symbols) & addr_width_burstwrap;
// end
// else begin
// burst_uncompress_address_offset <=
// (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap;
// end
end
end
end
// On the first packet beat, send the input address out unchanged,
// while values are computed/registered for 2nd and subsequent beats.
assign source_addr = first_packet_beat ? sink_addr :
burst_uncompress_address_base | burst_uncompress_address_offset;
assign source_burstwrap = sink_burstwrap;
assign source_burstsize = sink_burstsize;
//-------------------------------------------------------------------
// A single (compressed) read burst will have sop/eop in the same beat.
// A sequence of read sub-bursts emitted by a burst adapter in response to a
// single read burst will have sop on the first sub-burst, eop on the last.
// Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve
// packet conservation.
assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
assign source_endofpacket = sink_endofpacket & last_packet_beat;
assign sink_ready = source_valid & source_ready & last_packet_beat;
// This is correct for the slave agent usage, but won't always be true in the
// width adapter. To do: add an "please uncompress" input, and use it to
// pass-through or modify, and set source_is_compressed accordingly.
assign source_is_compressed = 1'b0;
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// --------------------------------------
// Merlin Master Agent
//
// Converts Avalon-MM transactions into
// Merlin network packets.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_merlin_master_agent
#(
// -------------------
// Packet Format Parameters
// -------------------
parameter
PKT_QOS_H = 109,
PKT_QOS_L = 106,
PKT_DATA_SIDEBAND_H = 105,
PKT_DATA_SIDEBAND_L = 98,
PKT_ADDR_SIDEBAND_H = 97,
PKT_ADDR_SIDEBAND_L = 93,
PKT_CACHE_H = 92,
PKT_CACHE_L = 89,
PKT_THREAD_ID_H = 88,
PKT_THREAD_ID_L = 87,
PKT_BEGIN_BURST = 81,
PKT_PROTECTION_H = 80,
PKT_PROTECTION_L = 80,
PKT_BURSTWRAP_H = 79,
PKT_BURSTWRAP_L = 77,
PKT_BYTE_CNT_H = 76,
PKT_BYTE_CNT_L = 74,
PKT_ADDR_H = 73,
PKT_ADDR_L = 42,
PKT_BURST_SIZE_H = 86,
PKT_BURST_SIZE_L = 84,
PKT_BURST_TYPE_H = 94,
PKT_BURST_TYPE_L = 93,
PKT_TRANS_EXCLUSIVE = 83,
PKT_TRANS_LOCK = 82,
PKT_TRANS_COMPRESSED_READ = 41,
PKT_TRANS_POSTED = 40,
PKT_TRANS_WRITE = 39,
PKT_TRANS_READ = 38,
PKT_DATA_H = 37,
PKT_DATA_L = 6,
PKT_BYTEEN_H = 5,
PKT_BYTEEN_L = 2,
PKT_SRC_ID_H = 1,
PKT_SRC_ID_L = 1,
PKT_DEST_ID_H = 0,
PKT_DEST_ID_L = 0,
PKT_RESPONSE_STATUS_L = 110,
PKT_RESPONSE_STATUS_H = 111,
PKT_ORI_BURST_SIZE_L = 112,
PKT_ORI_BURST_SIZE_H = 114,
ST_DATA_W = 115,
ST_CHANNEL_W = 1,
// -------------------
// Agent Parameters
// -------------------
AV_BURSTCOUNT_W = 3,
ID = 1,
SUPPRESS_0_BYTEEN_RSP = 1,
BURSTWRAP_VALUE = 4,
CACHE_VALUE = 0,
SECURE_ACCESS_BIT = 1,
USE_READRESPONSE = 0,
USE_WRITERESPONSE = 0,
// -------------------
// Derived Parameters
// -------------------
PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
PKT_PROTECTION_W = PKT_PROTECTION_H - PKT_PROTECTION_L + 1,
PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1,
PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1,
PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1,
PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1,
PKT_BURST_SIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1
) (
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Avalon-MM Anti-Master
// -------------------
input [PKT_ADDR_W-1 : 0] av_address,
input av_write,
input av_read,
input [PKT_DATA_W-1 : 0] av_writedata,
output reg [PKT_DATA_W-1 : 0] av_readdata,
output reg av_waitrequest,
output reg av_readdatavalid,
input [PKT_BYTEEN_W-1 : 0] av_byteenable,
input [AV_BURSTCOUNT_W-1 : 0] av_burstcount,
input av_debugaccess,
input av_lock,
output reg [1 : 0] av_response,
output reg av_writeresponsevalid,
// -------------------
// Command Source
// -------------------
output reg cp_valid,
output reg [ST_DATA_W-1 : 0] cp_data,
output wire cp_startofpacket,
output wire cp_endofpacket,
input cp_ready,
// -------------------
// Response Sink
// -------------------
input rp_valid,
input [ST_DATA_W-1 : 0] rp_data,
input [ST_CHANNEL_W-1 : 0] rp_channel,
input rp_startofpacket,
input rp_endofpacket,
output reg rp_ready
);
// ------------------------------------------------------------
// Utility Functions
// ------------------------------------------------------------
function integer clogb2;
input [31 : 0] value;
begin
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
value = value >> 1;
clogb2 = clogb2 - 1;
end
endfunction // clogb2
localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1);
localparam NUMSYMBOLS = PKT_BYTEEN_W;
localparam BURSTING = (MAX_BURST > NUMSYMBOLS);
localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS);
localparam BURST_SIZE = clogb2(NUMSYMBOLS);
typedef enum bit [1 : 0]
{
FIXED = 2'b00,
INCR = 2'b01,
WRAP = 2'b10,
OTHER_WRAP = 2'b11
} MerlinBurstType;
// --------------------------------------
// Potential optimization: compare in words to save bits?
// --------------------------------------
wire is_burst;
assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS);
wire [31 : 0] burstwrap_value_int = BURSTWRAP_VALUE;
wire [31 : 0] id_int = ID;
wire [PKT_BURST_SIZE_W-1 : 0] burstsize_sig = BURST_SIZE[PKT_BURST_SIZE_W-1 : 0];
wire [1 : 0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP;
// --------------------------------------
// Address alignment
//
// The packet format requires that addresses be aligned to
// the transaction size.
// --------------------------------------
wire [PKT_ADDR_W-1 : 0] av_address_aligned;
generate
if (NUMSYMBOLS > 1) begin
assign av_address_aligned =
{av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}};
end
else begin
assign av_address_aligned = av_address;
end
endgenerate
// --------------------------------------
// Command & Response Construction
// --------------------------------------
always_comb begin
cp_data = '0;
cp_data[PKT_PROTECTION_L] = av_debugaccess;
cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // secure cache bit
cp_data[PKT_PROTECTION_L+2] = 1'b0; // instruction/data cache bit
cp_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L] = burstwrap_value_int[PKT_BURSTWRAP_W-1 : 0];
cp_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = av_burstcount;
cp_data[PKT_ADDR_H : PKT_ADDR_L] = av_address_aligned;
cp_data[PKT_TRANS_EXCLUSIVE] = 1'b0;
cp_data[PKT_TRANS_LOCK] = av_lock;
cp_data[PKT_TRANS_COMPRESSED_READ] = av_read & is_burst;
cp_data[PKT_TRANS_READ] = av_read;
cp_data[PKT_TRANS_WRITE] = av_write;
cp_data[PKT_TRANS_POSTED] = av_write & !USE_WRITERESPONSE;
cp_data[PKT_DATA_H : PKT_DATA_L] = av_writedata;
cp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] = av_byteenable;
cp_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L] = burstsize_sig;
cp_data[PKT_ORI_BURST_SIZE_H : PKT_ORI_BURST_SIZE_L] = burstsize_sig;
cp_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L] = bursttype_value;
cp_data[PKT_SRC_ID_H : PKT_SRC_ID_L] = id_int[PKT_SRC_ID_W-1 : 0];
cp_data[PKT_THREAD_ID_H : PKT_THREAD_ID_L] = '0;
cp_data[PKT_CACHE_H : PKT_CACHE_L] = CACHE_VALUE[3 : 0];
cp_data[PKT_QOS_H : PKT_QOS_L] = '0;
cp_data[PKT_ADDR_SIDEBAND_H : PKT_ADDR_SIDEBAND_L] = '0;
cp_data[PKT_DATA_SIDEBAND_H : PKT_DATA_SIDEBAND_L] = '0;
av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L];
if (USE_WRITERESPONSE || USE_READRESPONSE)
av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L];
else
av_response = '0;
end
// --------------------------------------
// Command Control
// --------------------------------------
reg hold_waitrequest;
always @ (posedge clk, posedge reset) begin
if (reset)
hold_waitrequest <= 1'b1;
else
hold_waitrequest <= 1'b0;
end
always_comb begin
cp_valid = 0;
if ((av_write || av_read) && ~hold_waitrequest)
cp_valid = 1;
end
generate if (BURSTING) begin
reg sop_enable;
always @(posedge clk, posedge reset) begin
if (reset) begin
sop_enable <= 1'b1;
end
else begin
if (cp_valid && cp_ready) begin
sop_enable <= 1'b0;
if (cp_endofpacket)
sop_enable <= 1'b1;
end
end
end
assign cp_startofpacket = sop_enable;
assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS);
end
else begin
assign cp_startofpacket = 1'b1;
assign cp_endofpacket = 1'b1;
end
endgenerate
// --------------------------------------
// Backpressure & Readdatavalid
// --------------------------------------
always_comb begin
rp_ready = 1;
av_readdatavalid = 0;
av_writeresponsevalid = 0;
av_waitrequest = hold_waitrequest | !cp_ready;
if (USE_WRITERESPONSE && (rp_data[PKT_TRANS_WRITE] == 1))
av_writeresponsevalid = rp_valid;
else
av_readdatavalid = rp_valid;
if (SUPPRESS_0_BYTEEN_RSP) begin
if (rp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] == 0)
av_readdatavalid = 0;
end
end
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// --------------------------------------
// Merlin Master Translator
//
// Converts an Avalon-MM master interface into an
// Avalon-MM "universal" master interface.
//
// The universal interface is defined as the superset of ports
// and parameters that can represent any legal Avalon
// interface.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_merlin_master_translator #(
parameter
// widths
AV_ADDRESS_W = 32,
AV_DATA_W = 32,
AV_BURSTCOUNT_W = 4,
AV_BYTEENABLE_W = 4,
UAV_ADDRESS_W = 38,
UAV_BURSTCOUNT_W = 10,
// optional ports
USE_BURSTCOUNT = 1,
USE_BEGINBURSTTRANSFER = 0,
USE_BEGINTRANSFER = 0,
USE_CHIPSELECT = 0,
USE_READ = 1,
USE_READDATAVALID = 1,
USE_WRITE = 1,
USE_WAITREQUEST = 1,
USE_WRITERESPONSE = 0,
USE_READRESPONSE = 0,
AV_REGISTERINCOMINGSIGNALS = 0,
AV_SYMBOLS_PER_WORD = 4,
AV_ADDRESS_SYMBOLS = 0,
// must be enabled for a bursting master
AV_CONSTANT_BURST_BEHAVIOR = 1,
UAV_CONSTANT_BURST_BEHAVIOR = 0,
AV_BURSTCOUNT_SYMBOLS = 0,
AV_LINEWRAPBURSTS = 0
)(
input wire clk,
input wire reset,
// Universal Avalon Master
output reg uav_write,
output reg uav_read,
output reg [UAV_ADDRESS_W -1 : 0] uav_address,
output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount,
output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable,
output wire [AV_DATA_W -1 : 0] uav_writedata,
output wire uav_lock,
output wire uav_debugaccess,
output wire uav_clken,
input wire [AV_DATA_W -1 : 0] uav_readdata,
input wire uav_readdatavalid,
input wire uav_waitrequest,
input wire [1 : 0] uav_response,
input wire uav_writeresponsevalid,
// Avalon-MM Anti-master (slave)
input reg av_write,
input reg av_read,
input wire [AV_ADDRESS_W -1 : 0] av_address,
input wire [AV_BYTEENABLE_W -1 : 0] av_byteenable,
input wire [AV_BURSTCOUNT_W -1 : 0] av_burstcount,
input wire [AV_DATA_W -1 : 0] av_writedata,
input wire av_begintransfer,
input wire av_beginbursttransfer,
input wire av_lock,
input wire av_chipselect,
input wire av_debugaccess,
input wire av_clken,
output wire [AV_DATA_W -1 : 0] av_readdata,
output wire av_readdatavalid,
output reg av_waitrequest,
output reg [1 : 0] av_response,
output reg av_writeresponsevalid
);
localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD);
localparam AV_MAX_SYMBOL_BURST = flog2(pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : AV_SYMBOLS_PER_WORD));
localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0;
localparam UAV_BURSTCOUNT_H_OR_31 = (UAV_BURSTCOUNT_W > 32) ? 31 : UAV_BURSTCOUNT_W - 1;
localparam UAV_ADDRESS_H_OR_31 = (UAV_ADDRESS_W > 32) ? 31 : UAV_ADDRESS_W - 1;
localparam BITS_PER_WORD_BURSTCOUNT = (UAV_BURSTCOUNT_W == 1) ? 0 : BITS_PER_WORD;
localparam BITS_PER_WORD_ADDRESS = (UAV_ADDRESS_W == 1) ? 0 : BITS_PER_WORD;
localparam ADDRESS_LOW = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS;
localparam BURSTCOUNT_LOW = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT;
localparam ADDRESS_HIGH = (UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW) ? AV_ADDRESS_W : (UAV_ADDRESS_W - ADDRESS_LOW);
localparam BURSTCOUNT_HIGH = (UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW) ? AV_BURSTCOUNT_W : (UAV_BURSTCOUNT_W - BURSTCOUNT_LOW);
function integer flog2;
input [31:0] depth;
integer i;
begin
i = depth;
if ( i <= 0 ) flog2 = 0;
else begin
for (flog2 = -1; i > 0; flog2 = flog2 + 1)
i = i >> 1;
end
end
endfunction // flog2
// ------------------------------------------------------------
// Calculates the ceil(log2()) of the input val.
//
// Limited to a positive 32-bit input value.
// ------------------------------------------------------------
function integer clog2;
input[31:0] val;
reg[31:0] i;
begin
i = 1;
clog2 = 0;
while (i < val) begin
clog2 = clog2 + 1;
i = i[30:0] << 1;
end
end
endfunction
function integer pow2;
input [31:0] toShift;
begin
pow2 = 1;
pow2 = pow2 << toShift;
end
endfunction // pow2
// -------------------------------------------------
// Assign some constants to appropriately-sized signals to
// avoid synthesis warnings. This also helps some simulators
// with their inferred sensitivity lists.
//
// The symbols per word calculation here rounds non-power of two
// symbols to the next highest power of two, which is what we want
// when calculating the decrementing byte count.
// -------------------------------------------------
wire [31 : 0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_H_OR_31 : 0]));
wire [UAV_BURSTCOUNT_H_OR_31 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_H_OR_31 : 0];
reg internal_beginbursttransfer;
reg internal_begintransfer;
reg [UAV_ADDRESS_W -1 : 0] uav_address_pre;
reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount_pre;
reg uav_read_pre;
reg uav_write_pre;
reg read_accepted;
// -------------------------------------------------
// Pass through signals that we don't touch
// -------------------------------------------------
assign uav_writedata = av_writedata;
assign uav_byteenable = av_byteenable;
assign uav_lock = av_lock;
assign uav_debugaccess = av_debugaccess;
assign uav_clken = av_clken;
assign av_readdata = uav_readdata;
assign av_readdatavalid = uav_readdatavalid;
// -------------------------------------------------
// Response signals
// -------------------------------------------------
always_comb begin
if (!USE_READRESPONSE && !USE_WRITERESPONSE)
av_response = '0;
else
av_response = uav_response;
if (USE_WRITERESPONSE) begin
av_writeresponsevalid = uav_writeresponsevalid;
end else begin
av_writeresponsevalid = '0;
end
end
// -------------------------------------------------
// Convert byte and word addresses into byte addresses
// -------------------------------------------------
always_comb begin
uav_address_pre = {UAV_ADDRESS_W{1'b0}};
if (AV_ADDRESS_SYMBOLS)
uav_address_pre[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
else begin
uav_address_pre[ADDRESS_LOW + ADDRESS_HIGH - 1 : ADDRESS_LOW] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
end
end
// -------------------------------------------------
// Convert burstcount into symbol units
// -------------------------------------------------
always_comb begin
uav_burstcount_pre = symbols_per_word; // default to a single transfer
if (USE_BURSTCOUNT) begin
uav_burstcount_pre = {UAV_BURSTCOUNT_W{1'b0}};
if (AV_BURSTCOUNT_SYMBOLS)
uav_burstcount_pre[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) :0] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
else begin
uav_burstcount_pre[UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
end
end
end
// -------------------------------------------------
// This is where we perform the per-transfer address and burstcount
// calculations that are required by downstream modules.
// -------------------------------------------------
reg [UAV_ADDRESS_W -1 : 0] address_register;
wire [UAV_BURSTCOUNT_W -1 : 0] burstcount_register;
reg [UAV_BURSTCOUNT_W : 0] burstcount_register_lint;
assign burstcount_register = burstcount_register_lint[UAV_BURSTCOUNT_W -1 : 0];
always_comb begin
uav_address = uav_address_pre;
uav_burstcount = uav_burstcount_pre;
if (AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin
uav_address = address_register;
uav_burstcount = burstcount_register;
end
end
reg first_burst_stalled;
reg burst_stalled;
wire [UAV_ADDRESS_W -1 : 0] combi_burst_addr_reg;
wire [UAV_ADDRESS_W -1 : 0] combi_addr_reg;
generate
if (AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST != 0) begin
if (AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin
assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
end
else begin
assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
end
end
else begin
assign combi_burst_addr_reg = uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
assign combi_addr_reg = address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
end
endgenerate
always @(posedge clk, posedge reset) begin
if (reset) begin
address_register <= '0;
burstcount_register_lint <= '0;
end else begin
address_register <= address_register;
burstcount_register_lint <= burstcount_register_lint;
if (internal_beginbursttransfer || first_burst_stalled) begin
if (av_waitrequest) begin
address_register <= uav_address_pre;
burstcount_register_lint[UAV_BURSTCOUNT_W - 1 : 0] <= uav_burstcount_pre;
end else begin
address_register <= combi_burst_addr_reg;
burstcount_register_lint <= uav_burstcount_pre - symbols_per_word;
end
end else if (internal_begintransfer || burst_stalled) begin
if (~av_waitrequest) begin
address_register <= combi_addr_reg;
burstcount_register_lint <= burstcount_register - symbols_per_word;
end
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
first_burst_stalled <= 1'b0;
burst_stalled <= 1'b0;
end else begin
if (internal_beginbursttransfer || first_burst_stalled) begin
if (av_waitrequest) begin
first_burst_stalled <= 1'b1;
end else begin
first_burst_stalled <= 1'b0;
end
end else if (internal_begintransfer || burst_stalled) begin
if (~av_waitrequest) begin
burst_stalled <= 1'b0;
end else begin
burst_stalled <= 1'b1;
end
end
end
end
// -------------------------------------------------
// Waitrequest translation
// -------------------------------------------------
always @(posedge clk, posedge reset) begin
if (reset)
read_accepted <= 1'b0;
else begin
read_accepted <= read_accepted;
if (read_accepted == 0)
read_accepted <= av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0;
else if (read_accepted == 1 && uav_readdatavalid == 1) // reset acceptance only when rdv arrives
read_accepted <= 1'b0;
end
end
reg write_accepted = 0;
generate if (AV_REGISTERINCOMINGSIGNALS) begin
always @(posedge clk, posedge reset) begin
if (reset)
write_accepted <= 1'b0;
else begin
write_accepted <=
~av_waitrequest ? 1'b0 :
uav_write & ~uav_waitrequest? 1'b1 :
write_accepted;
end
end
end endgenerate
always_comb begin
av_waitrequest = uav_waitrequest;
if (USE_READDATAVALID == 0) begin
av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest;
end
if (AV_REGISTERINCOMINGSIGNALS) begin
av_waitrequest =
uav_read_pre ? ~uav_readdatavalid :
uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted :
1'b1;
end
if (USE_WAITREQUEST == 0) begin
av_waitrequest = 0;
end
end
// -------------------------------------------------
// Determine the output read and write signals from
// the read/write/chipselect input signals.
// -------------------------------------------------
always_comb begin
uav_write = 1'b0;
uav_write_pre = 1'b0;
uav_read = 1'b0;
uav_read_pre = 1'b0;
if (!USE_CHIPSELECT) begin
if (USE_READ) begin
uav_read_pre = av_read;
end
if (USE_WRITE) begin
uav_write_pre = av_write;
end
end else begin
if (!USE_WRITE && USE_READ) begin
uav_write_pre = av_chipselect & ~av_read;
uav_read_pre = av_read;
end else if (!USE_READ && USE_WRITE) begin
uav_write_pre = av_write;
uav_read_pre = av_chipselect & ~av_write;
end else if (USE_READ && USE_WRITE) begin
uav_write_pre = av_write;
uav_read_pre = av_read;
end
end
if (USE_READDATAVALID == 0)
uav_read = uav_read_pre & ~read_accepted;
else
uav_read = uav_read_pre;
if (AV_REGISTERINCOMINGSIGNALS == 0)
uav_write = uav_write_pre;
else
uav_write = uav_write_pre & ~write_accepted;
end
// -------------------------------------------------
// Begintransfer assignment
// -------------------------------------------------
reg end_begintransfer;
always_comb begin
if (USE_BEGINTRANSFER) begin
internal_begintransfer = av_begintransfer;
end else begin
internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
end_begintransfer <= 1'b0;
end else begin
if (internal_begintransfer == 1 && uav_waitrequest)
end_begintransfer <= 1'b1;
else if (uav_waitrequest)
end_begintransfer <= end_begintransfer;
else
end_begintransfer <= 1'b0;
end
end
// -------------------------------------------------
// Beginbursttransfer assignment
// -------------------------------------------------
reg end_beginbursttransfer;
wire last_burst_transfer_pre;
wire last_burst_transfer_reg;
wire last_burst_transfer;
// compare values before the mux to shorten critical path; benchmark before changing
assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word);
assign last_burst_transfer_reg = (burstcount_register == symbols_per_word);
assign last_burst_transfer = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg;
always_comb begin
if (USE_BEGINBURSTTRANSFER) begin
internal_beginbursttransfer = av_beginbursttransfer;
end else begin
internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
end_beginbursttransfer <= 1'b0;
end else begin
end_beginbursttransfer <= end_beginbursttransfer;
if (last_burst_transfer && internal_begintransfer || uav_read) begin
end_beginbursttransfer <= 1'b0;
end
else if (uav_write && internal_begintransfer) begin
end_beginbursttransfer <= 1'b1;
end
end
end
// synthesis translate_off
// ------------------------------------------------
// check_1 : for waitrequest signal violation
// Ensure that when waitreqeust is asserted, the master is not allowed to change its controls
// Exception : begintransfer / beginbursttransfer
// : previously not in any transaction (idle)
// Note : Not checking clken which is not exactly part of Avalon controls/inputs
// : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE
// ------------------------------------------------
reg av_waitrequest_r;
reg av_write_r, av_read_r, av_lock_r, av_chipselect_r, av_debugaccess_r;
reg [AV_ADDRESS_W-1:0] av_address_r;
reg [AV_BYTEENABLE_W-1:0] av_byteenable_r;
reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r;
reg [AV_DATA_W-1:0] av_writedata_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
av_waitrequest_r <= '0;
av_write_r <= '0;
av_read_r <= '0;
av_lock_r <= '0;
av_chipselect_r <= '0;
av_debugaccess_r <= '0;
av_address_r <= '0;
av_byteenable_r <= '0;
av_burstcount_r <= '0;
av_writedata_r <= '0;
end else begin
av_waitrequest_r <= av_waitrequest;
av_write_r <= av_write;
av_read_r <= av_read;
av_lock_r <= av_lock;
av_chipselect_r <= av_chipselect;
av_debugaccess_r <= av_debugaccess;
av_address_r <= av_address;
av_byteenable_r <= av_byteenable;
av_burstcount_r <= av_burstcount;
av_writedata_r <= av_writedata;
if (
av_waitrequest_r && // When waitrequest is asserted
(
(av_write != av_write_r) || // Checks that : Input controls/data does not change
(av_read != av_read_r) ||
(av_lock != av_lock_r) ||
(av_debugaccess != av_debugaccess_r) ||
(av_address != av_address_r) ||
(av_byteenable != av_byteenable_r) ||
(av_burstcount != av_burstcount_r)
) &&
(av_write_r | av_read_r) && // Check only when : previously initiated a write/read
(!USE_CHIPSELECT | av_chipselect_r) // and chipselect was asserted (or unused)
) begin
$display( "%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.", $time());
$display("av_address %x --> %x", av_address_r , av_address );
$display("av_byteenable %x --> %x", av_byteenable_r , av_byteenable );
$display("av_burstcount %x --> %x", av_burstcount_r , av_burstcount );
$display("av_writedata %x --> %x", av_writedata_r , av_writedata );
$display("av_write %x --> %x", av_write_r , av_write );
$display("av_read %x --> %x", av_read_r , av_read );
$display("av_lock %x --> %x", av_lock_r , av_lock );
$display("av_chipselect %x --> %x", av_chipselect_r , av_chipselect );
$display("av_debugaccess %x --> %x", av_debugaccess_r , av_debugaccess );
end
end
// end check_1
end
// synthesis translate_on
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
`timescale 1 ns / 1 ns
module altera_merlin_slave_agent
#(
// Packet parameters
parameter PKT_BEGIN_BURST = 81,
parameter PKT_DATA_H = 31,
parameter PKT_DATA_L = 0,
parameter PKT_SYMBOL_W = 8,
parameter PKT_BYTEEN_H = 71,
parameter PKT_BYTEEN_L = 68,
parameter PKT_ADDR_H = 63,
parameter PKT_ADDR_L = 32,
parameter PKT_TRANS_LOCK = 87,
parameter PKT_TRANS_COMPRESSED_READ = 67,
parameter PKT_TRANS_POSTED = 66,
parameter PKT_TRANS_WRITE = 65,
parameter PKT_TRANS_READ = 64,
parameter PKT_SRC_ID_H = 74,
parameter PKT_SRC_ID_L = 72,
parameter PKT_DEST_ID_H = 77,
parameter PKT_DEST_ID_L = 75,
parameter PKT_BURSTWRAP_H = 85,
parameter PKT_BURSTWRAP_L = 82,
parameter PKT_BYTE_CNT_H = 81,
parameter PKT_BYTE_CNT_L = 78,
parameter PKT_PROTECTION_H = 86,
parameter PKT_PROTECTION_L = 86,
parameter PKT_RESPONSE_STATUS_H = 89,
parameter PKT_RESPONSE_STATUS_L = 88,
parameter PKT_BURST_SIZE_H = 92,
parameter PKT_BURST_SIZE_L = 90,
parameter PKT_ORI_BURST_SIZE_L = 93,
parameter PKT_ORI_BURST_SIZE_H = 95,
parameter ST_DATA_W = 96,
parameter ST_CHANNEL_W = 32,
// Slave parameters
parameter ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1,
parameter AVS_DATA_W = PKT_DATA_H - PKT_DATA_L + 1,
parameter AVS_BURSTCOUNT_W = 4,
parameter PKT_SYMBOLS = AVS_DATA_W / PKT_SYMBOL_W,
// Slave agent parameters
parameter PREVENT_FIFO_OVERFLOW = 0,
parameter SUPPRESS_0_BYTEEN_CMD = 1,
parameter USE_READRESPONSE = 0,
parameter USE_WRITERESPONSE = 0,
// Derived slave parameters
parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
parameter BURST_SIZE_W = 3,
// Derived FIFO width
parameter FIFO_DATA_W = ST_DATA_W + 1,
// ECC parameter
parameter ECC_ENABLE = 0
) (
input clk,
input reset,
// Universal-Avalon anti-slave
output [ADDR_W-1:0] m0_address,
output [AVS_BURSTCOUNT_W-1:0] m0_burstcount,
output [AVS_BE_W-1:0] m0_byteenable,
output m0_read,
input [AVS_DATA_W-1:0] m0_readdata,
input m0_waitrequest,
output m0_write,
output [AVS_DATA_W-1:0] m0_writedata,
input m0_readdatavalid,
output m0_debugaccess,
output m0_lock,
input [1:0] m0_response,
input m0_writeresponsevalid,
// Avalon-ST FIFO interfaces.
// Note: there's no need to include the "data" field here, at least for
// reads, since readdata is filled in from slave info. To keep life
// simple, have a data field, but fill it with 0s.
// Av-st response fifo source interface
output reg [FIFO_DATA_W-1:0] rf_source_data,
output rf_source_valid,
output rf_source_startofpacket,
output rf_source_endofpacket,
input rf_source_ready,
// Av-st response fifo sink interface
input [FIFO_DATA_W-1:0] rf_sink_data,
input rf_sink_valid,
input rf_sink_startofpacket,
input rf_sink_endofpacket,
output rf_sink_ready,
// Av-st readdata fifo src interface, data and response
// extra 2 bits for storing RESPONSE STATUS
output [AVS_DATA_W+1:0] rdata_fifo_src_data,
output rdata_fifo_src_valid,
input rdata_fifo_src_ready,
// Av-st readdata fifo sink interface
input [AVS_DATA_W+1:0] rdata_fifo_sink_data,
input rdata_fifo_sink_valid,
output rdata_fifo_sink_ready,
input rdata_fifo_sink_error,
// Av-st sink command packet interface
output cp_ready,
input cp_valid,
input [ST_DATA_W-1:0] cp_data,
input [ST_CHANNEL_W-1:0] cp_channel,
input cp_startofpacket,
input cp_endofpacket,
// Av-st source response packet interface
input rp_ready,
output reg rp_valid,
output reg [ST_DATA_W-1:0] rp_data,
output rp_startofpacket,
output rp_endofpacket
);
// --------------------------------------------------
// Ceil(log2()) function log2ceil of 4 = 2
// --------------------------------------------------
function integer log2ceil;
input reg[63:0] val;
reg [63:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
// ------------------------------------------------
// Local Parameters
// ------------------------------------------------
localparam DATA_W = PKT_DATA_H - PKT_DATA_L + 1;
localparam BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
localparam MID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1;
localparam SID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1;
localparam BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1;
localparam BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1;
localparam BURSTSIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1;
localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS);
localparam MAX_BURST = 1 << (AVS_BURSTCOUNT_W - 1);
localparam BURSTING = (MAX_BURST > PKT_SYMBOLS);
// ------------------------------------------------
// Signals
// ------------------------------------------------
wire [DATA_W-1:0] cmd_data;
wire [BE_W-1:0] cmd_byteen;
wire [ADDR_W-1:0] cmd_addr;
wire [MID_W-1:0] cmd_mid;
wire [SID_W-1:0] cmd_sid;
wire cmd_read;
wire cmd_write;
wire cmd_compressed;
wire cmd_posted;
wire [BYTE_CNT_W-1:0] cmd_byte_cnt;
wire [BURSTWRAP_W-1:0] cmd_burstwrap;
wire [BURSTSIZE_W-1:0] cmd_burstsize;
wire cmd_debugaccess;
wire suppress_cmd;
wire byteen_asserted;
wire suppress_read;
wire suppress_write;
wire needs_response_synthesis;
wire generate_response;
// Assign command fields
assign cmd_data = cp_data[PKT_DATA_H :PKT_DATA_L ];
assign cmd_byteen = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L];
assign cmd_addr = cp_data[PKT_ADDR_H :PKT_ADDR_L ];
assign cmd_compressed = cp_data[PKT_TRANS_COMPRESSED_READ];
assign cmd_posted = cp_data[PKT_TRANS_POSTED];
assign cmd_write = cp_data[PKT_TRANS_WRITE];
assign cmd_read = cp_data[PKT_TRANS_READ];
assign cmd_mid = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L];
assign cmd_sid = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L];
assign cmd_byte_cnt = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
assign cmd_burstwrap = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
assign cmd_burstsize = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
assign cmd_debugaccess = cp_data[PKT_PROTECTION_L];
// Local "ready_for_command" signal: deasserted when the agent is unable to accept
// another command, e.g. rdv FIFO is full, (local readdata storage is full &&
// ~rp_ready), ...
// Say, this could depend on the type of command, for example, even if the
// rdv FIFO is full, a write request can be accepted. For later.
wire ready_for_command;
wire local_lock = cp_valid & cp_data[PKT_TRANS_LOCK];
wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE];
wire local_read = cp_valid & cp_data[PKT_TRANS_READ];
wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ];
wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket;
// num_symbols is PKT_SYMBOLS, appropriately sized.
wire [31:0] int_num_symbols = PKT_SYMBOLS;
wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
generate
if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow_block
// ---------------------------------------------------
// Backpressure if the slave says to, or if FIFO overflow may occur.
//
// All commands are backpressured once the FIFO is full
// even if they don't need storage. This breaks a long
// combinatorial path from the master read/write through
// this logic and back to the master via the backpressure
// path.
//
// To avoid a loss of throughput the FIFO will be parameterized
// one slot deeper. The extra slot should never be used in normal
// operation, but should a slave misbehave and accept one more
// read than it should then backpressure will kick in.
//
// An example: assume a slave with MPRT = 2. It can accept a
// command sequence RRWW without backpressuring. If the FIFO is
// only 2 deep, we'd backpressure the writes leading to loss of
// throughput. If the FIFO is 3 deep, we'll only backpressure when
// RRR... which is an illegal condition anyway.
// ---------------------------------------------------
assign ready_for_command = rf_source_ready;
assign cp_ready = (~m0_waitrequest | suppress_cmd) && ready_for_command;
end else begin : no_prevent_fifo_overflow_block
// Do not suppress the command or the slave will
// not be able to waitrequest
assign ready_for_command = 1'b1;
// Backpressure only if the slave says to.
assign cp_ready = ~m0_waitrequest | suppress_cmd;
end
endgenerate
generate if (SUPPRESS_0_BYTEEN_CMD && !BURSTING) begin : suppress_0_byteen_cmd_non_bursting
assign byteen_asserted = |cmd_byteen;
assign suppress_read = ~byteen_asserted;
assign suppress_write = ~byteen_asserted;
assign suppress_cmd = ~byteen_asserted;
end else if (SUPPRESS_0_BYTEEN_CMD && BURSTING) begin: suppress_0_byteen_cmd_bursting
assign byteen_asserted = |cmd_byteen;
assign suppress_read = ~byteen_asserted;
assign suppress_write = 1'b0;
assign suppress_cmd = ~byteen_asserted && cmd_read;
end else begin : no_suppress_0_byteen_cmd
assign suppress_read = 1'b0;
assign suppress_write = 1'b0;
assign suppress_cmd = 1'b0;
end
endgenerate
// -------------------------------------------------------------------
// Extract avalon signals from command packet.
// -------------------------------------------------------------------
// Mask off the lower bits of address.
// The burst adapter before this component will break narrow sized packets
// into sub-bursts of length 1. However, the packet addresses are preserved,
// which means this component may see size-aligned addresses.
//
// Masking ensures that the addresses seen by an Avalon slave are aligned to
// the full data width instead of the size.
//
// Example:
// output from burst adapter (datawidth=4, size=2 bytes):
// subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6
// expected output from slave agent:
// subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4
generate
if (BITS_TO_MASK > 0) begin : mask_address
assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} };
end else begin : no_mask_address
assign m0_address = cmd_addr;
end
endgenerate
assign m0_byteenable = cmd_byteen;
assign m0_writedata = cmd_data;
// Note: no Avalon-MM slave in existence accepts uncompressed read bursts -
// this sort of burst exists only in merlin fabric ST packets. What to do
// if we see such a burst? All beats in that burst need to be transmitted
// to the slave so we have enough space-time for byteenable expression.
//
// There can be multiple bursts in a packet, but only one beat per burst
// in <most> cases. The exception is when we've decided not to insert a
// burst adapter for efficiency reasons, in which case this agent is also
// responsible for driving burstcount to 1 on each beat of an uncompressed
// read burst.
assign m0_read = ready_for_command & !suppress_read & (local_compressed_read | local_read);
generate
// AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal. Assign m0_burstcount
// from a sub-range, or 0-pad, as appropriate.
if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin : m0_burstcount_zero_pad
wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}};
assign m0_burstcount = (local_read & ~local_compressed_read) ?
{zero_pad, num_symbols} :
{zero_pad, cmd_byte_cnt};
end
else begin : m0_burstcount_no_pad
assign m0_burstcount = (local_read & ~local_compressed_read) ?
num_symbols[AVS_BURSTCOUNT_W-1:0] :
cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0];
end
endgenerate
assign m0_write = ready_for_command & local_write & !suppress_write;
assign m0_lock = ready_for_command & local_lock & (m0_read | m0_write);
assign m0_debugaccess = cmd_debugaccess;
// -------------------------------------------------------------------
// Indirection layer for response packet values. Some may always wire
// directly from the slave translator; others will no doubt emerge from
// various FIFOs.
// What to put in resp_data when a write occured? Answer: it does not
// matter, because only response status is needed for non-posted writes,
// and the packet already has a field for that.
//
// We use the rdata_fifo to store write responses as well. This allows us
// to handle backpressure on the response path, and allows write response
// merging.
assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid;
assign rdata_fifo_src_data = {m0_response, m0_readdata};
// ------------------------------------------------------------------
// Generate a token when read commands are suppressed. The token
// is stored in the response FIFO, and will be used to synthesize
// a read response. The same token is used for non-posted write
// response synthesis.
//
// Note: this token is not generated for suppressed uncompressed read cycles;
// the burst uncompression logic at the read side of the response FIFO
// generates the correct number of responses.
//
// When the slave can return the response, let it do its job. Don't
// synthesize a response in that case, unless we've suppressed the
// the last transfer in a write sub-burst.
// ------------------------------------------------------------------
wire write_end_of_subburst;
assign needs_response_synthesis = ((local_read | local_compressed_read) & suppress_read) ||
(!USE_WRITERESPONSE && nonposted_write_endofpacket) ||
(USE_WRITERESPONSE && write_end_of_subburst && suppress_write);
// Avalon-ST interfaces to external response FIFO.
//
// For efficiency, when synthesizing a write response we only store a non-posted write
// transaction at its endofpacket, even if it was split into multiple sub-bursts.
//
// When not synthesizing write responses, we store each sub-burst in the FIFO.
// Each sub-burst to the slave will return a response, which corresponds to one
// entry in the FIFO. We merge all the sub-burst responses on the final
// sub-burst and send it on the response channel.
wire internal_cp_endofburst;
wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning
wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount;
assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0];
assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount);
assign write_end_of_subburst = local_write & internal_cp_endofburst;
assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && internal_cp_endofburst && local_write))
& ready_for_command & cp_ready;
assign rf_source_startofpacket = cp_startofpacket;
assign rf_source_endofpacket = cp_endofpacket;
always @* begin
// default: assign every command packet field to the response FIFO...
rf_source_data = {1'b0, cp_data};
// ... and override select fields as needed.
rf_source_data[FIFO_DATA_W-1] = needs_response_synthesis;
rf_source_data[PKT_DATA_H :PKT_DATA_L] = {DATA_W {1'b0}};
rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = cmd_byteen;
rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = cmd_addr;
rf_source_data[PKT_TRANS_COMPRESSED_READ] = cmd_compressed;
rf_source_data[PKT_TRANS_POSTED] = cmd_posted;
rf_source_data[PKT_TRANS_WRITE] = cmd_write;
rf_source_data[PKT_TRANS_READ] = cmd_read;
rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = cmd_mid;
rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = cmd_sid;
rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = cmd_byte_cnt;
rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = cmd_burstwrap;
rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = cmd_burstsize;
rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = '0;
rf_source_data[PKT_PROTECTION_L] = cmd_debugaccess;
end
wire uncompressor_source_valid;
wire [BURSTSIZE_W-1:0] uncompressor_burstsize;
wire last_write_response;
// last_write_response indicates the last response of the broken-up write burst (sub-bursts).
// At this time, the final merged response is sent, and rp_valid is only asserted
// once for the whole burst.
generate
if (USE_WRITERESPONSE) begin
assign last_write_response = rf_sink_data[PKT_TRANS_WRITE] & rf_sink_endofpacket;
always @* begin
if (rf_sink_data[PKT_TRANS_WRITE] == 1)
rp_valid = (rdata_fifo_sink_valid | generate_response) & last_write_response & !rf_sink_data[PKT_TRANS_POSTED];
else
rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid;
end
end else begin
assign last_write_response = 1'b0;
always @* begin
rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid;
end
end
endgenerate
// ------------------------------------------------------------------
// Response merging
// ------------------------------------------------------------------
reg [1:0] current_response;
reg [1:0] response_merged;
generate
if (USE_WRITERESPONSE) begin : response_merging_all
reg first_write_response;
reg reset_merged_output;
reg [1:0] previous_response_in;
reg [1:0] previous_response;
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
first_write_response <= 1'b1;
end
else begin // Merging work for write response, for read: previous_response_in = current_response
if (rf_sink_valid & (rdata_fifo_sink_valid | generate_response) & rf_sink_data[PKT_TRANS_WRITE]) begin
first_write_response <= 1'b0;
if (rf_sink_endofpacket)
first_write_response <= 1'b1;
end
end
end
always_comb begin
current_response = generate_response ? 2'b00 : rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | {2{rdata_fifo_sink_error}};
reset_merged_output = first_write_response && (rdata_fifo_sink_valid || generate_response);
previous_response_in = reset_merged_output ? current_response : previous_response;
response_merged = current_response >= previous_response ? current_response: previous_response_in;
end
always_ff @(posedge clk or posedge reset) begin
if (reset) begin
previous_response <= 2'b00;
end
else begin
if (rf_sink_valid & (rdata_fifo_sink_valid || generate_response)) begin
previous_response <= response_merged;
end
end
end
end else begin : response_merging_read_only
always @* begin
current_response = generate_response ? 2'b00: rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] |
{2{rdata_fifo_sink_error}};
response_merged = current_response;
end
end
endgenerate
assign generate_response = rf_sink_data[FIFO_DATA_W-1];
wire [BYTE_CNT_W-1:0] rf_sink_byte_cnt = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
wire rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ];
wire [BURSTWRAP_W-1:0] rf_sink_burstwrap = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
wire [BURSTSIZE_W-1:0] rf_sink_burstsize = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
wire [ADDR_W-1:0] rf_sink_addr = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L];
// a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo
wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket;
wire [BYTE_CNT_W-1:0] burst_byte_cnt;
wire [BURSTWRAP_W-1:0] rp_burstwrap;
wire [ADDR_W-1:0] rp_address;
wire rp_is_compressed;
wire ready_for_response;
// ------------------------------------------------------------------
// We're typically ready for a response if the network is ready. There
// is one exception:
//
// If the slave issues write responses, we only issue a merged response on
// the final sub-burst. As a result, we only care about response channel
// availability on the final burst when we send out the merged response.
// ------------------------------------------------------------------
assign ready_for_response = (USE_WRITERESPONSE) ?
rp_ready || (rf_sink_data[PKT_TRANS_WRITE] && !last_write_response) || rf_sink_data[PKT_TRANS_POSTED]:
rp_ready;
// ------------------------------------------------------------------
// Backpressure the readdata fifo if we're supposed to synthesize a response.
// This may be a read response (for suppressed reads) or a write response
// (for non-posted writes).
// ------------------------------------------------------------------
assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & ready_for_response & ~(rf_sink_valid & generate_response);
always @* begin
// By default, return all fields...
rp_data = rf_sink_data[ST_DATA_W - 1 : 0];
// ... and override specific fields.
rp_data[PKT_DATA_H :PKT_DATA_L] = rdata_fifo_sink_data[AVS_DATA_W-1:0];
// Assignments directly from the response fifo.
rp_data[PKT_TRANS_POSTED] = rf_sink_data[PKT_TRANS_POSTED];
rp_data[PKT_TRANS_WRITE] = rf_sink_data[PKT_TRANS_WRITE];
rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L];
rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L];
rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L];
// Burst uncompressor assignments
rp_data[PKT_ADDR_H :PKT_ADDR_L] = rp_address;
rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = rp_burstwrap;
rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = burst_byte_cnt;
rp_data[PKT_TRANS_READ] = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ];
rp_data[PKT_TRANS_COMPRESSED_READ] = rp_is_compressed;
rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = response_merged;
rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = uncompressor_burstsize;
// bounce the original size back to the master untouched
rp_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L] = rf_sink_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L];
end
// ------------------------------------------------------------------
// Note: the burst uncompressor may be asked to generate responses for
// write packets; these are treated the same as single-cycle uncompressed
// reads.
// ------------------------------------------------------------------
altera_merlin_burst_uncompressor #(
.ADDR_W (ADDR_W),
.BURSTWRAP_W (BURSTWRAP_W),
.BYTE_CNT_W (BYTE_CNT_W),
.PKT_SYMBOLS (PKT_SYMBOLS),
.BURST_SIZE_W (BURSTSIZE_W)
) uncompressor (
.clk (clk),
.reset (reset),
.sink_startofpacket (rf_sink_startofpacket_wire),
.sink_endofpacket (rf_sink_endofpacket),
.sink_valid (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)),
.sink_ready (rf_sink_ready),
.sink_addr (rf_sink_addr),
.sink_burstwrap (rf_sink_burstwrap),
.sink_byte_cnt (rf_sink_byte_cnt),
.sink_is_compressed (rf_sink_compressed),
.sink_burstsize (rf_sink_burstsize),
.source_startofpacket (rp_startofpacket),
.source_endofpacket (rp_endofpacket),
.source_valid (uncompressor_source_valid),
.source_ready (ready_for_response),
.source_addr (rp_address),
.source_burstwrap (rp_burstwrap),
.source_byte_cnt (burst_byte_cnt),
.source_is_compressed (rp_is_compressed),
.source_burstsize (uncompressor_burstsize)
);
//--------------------------------------
// Assertion: In case slave support response. The slave needs return response in order
// Ex: non-posted write followed by a read: write response must complete before read data
//--------------------------------------
// synthesis translate_off
ERROR_write_response_and_read_response_cannot_happen_same_time:
assert property ( @(posedge clk)
disable iff (reset) !(m0_writeresponsevalid && m0_readdatavalid)
);
// synthesis translate_on
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -------------------------------------
// Merlin Slave Translator
//
// Translates Universal Avalon MM Slave
// to any Avalon MM Slave
// -------------------------------------
//
//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
//The key feature here is that no same cycle turnaround data is processed through the fabric.
//import avalon_utilities_pkg::*;
`timescale 1 ns / 1 ns
module altera_merlin_slave_translator #(
parameter
//Widths
AV_ADDRESS_W = 32,
AV_DATA_W = 32,
AV_BURSTCOUNT_W = 4,
AV_BYTEENABLE_W = 4,
UAV_BYTEENABLE_W = 4,
//Read Latency
AV_READLATENCY = 1,
//Timing
AV_READ_WAIT_CYCLES = 0,
AV_WRITE_WAIT_CYCLES = 0,
AV_SETUP_WAIT_CYCLES = 0,
AV_DATA_HOLD_CYCLES = 0,
//Optional Port Declarations
USE_READDATAVALID = 1,
USE_WAITREQUEST = 1,
USE_READRESPONSE = 0,
USE_WRITERESPONSE = 0,
//Variable Addressing
AV_SYMBOLS_PER_WORD = 4,
AV_ADDRESS_SYMBOLS = 0,
AV_BURSTCOUNT_SYMBOLS = 0,
BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1),
UAV_ADDRESS_W = 38,
UAV_BURSTCOUNT_W = 10,
UAV_DATA_W = 32,
AV_CONSTANT_BURST_BEHAVIOR = 0,
UAV_CONSTANT_BURST_BEHAVIOR = 0,
CHIPSELECT_THROUGH_READLATENCY = 0,
// Tightly-Coupled Options
USE_UAV_CLKEN = 0,
AV_REQUIRE_UNALIGNED_ADDRESSES = 0
) (
// -------------------
// Clock & Reset
// -------------------
input wire clk,
input wire reset,
// -------------------
// Universal Avalon Slave
// -------------------
input wire [UAV_ADDRESS_W - 1 : 0] uav_address,
input wire [UAV_DATA_W - 1 : 0] uav_writedata,
input wire uav_write,
input wire uav_read,
input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount,
input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable,
input wire uav_lock,
input wire uav_debugaccess,
input wire uav_clken,
output logic uav_readdatavalid,
output logic uav_waitrequest,
output logic [UAV_DATA_W - 1 : 0] uav_readdata,
output logic [1:0] uav_response,
// input wire uav_writeresponserequest,
output logic uav_writeresponsevalid,
// -------------------
// Customizable Avalon Master
// -------------------
output logic [AV_ADDRESS_W - 1 : 0] av_address,
output logic [AV_DATA_W - 1 : 0] av_writedata,
output logic av_write,
output logic av_read,
output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable,
output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
output logic av_begintransfer,
output wire av_chipselect,
output logic av_beginbursttransfer,
output logic av_lock,
output wire av_clken,
output wire av_debugaccess,
output wire av_outputenable,
input logic [AV_DATA_W - 1 : 0] av_readdata,
input logic av_readdatavalid,
input logic av_waitrequest,
input logic [1:0] av_response,
// output logic av_writeresponserequest,
input wire av_writeresponsevalid
);
function integer clog2_plusone;
input [31:0] Depth;
integer i;
begin
i = Depth;
for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1)
i = i >> 1;
end
endfunction
function integer max;
//returns the larger of two passed arguments
input [31:0] one;
input [31:0] two;
if(one > two)
max=one;
else
max=two;
endfunction // int
localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1));
localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
AV_ADDRESS_W :
UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
AV_BURSTCOUNT_W :
UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1;
// Calculate the symbols per word as the power of 2 extended symbols per word
wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0];
// +--------------------------------
// |Backwards Compatibility Signals
// +--------------------------------
assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
assign av_debugaccess = uav_debugaccess;
// +-------------------
// |Passthru Signals
// +-------------------
reg [1 : 0] av_response_delayed;
always @(posedge clk, posedge reset) begin
if (reset) begin
av_response_delayed <= 2'b0;
end else begin
av_response_delayed <= av_response;
end
end
always_comb
begin
if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin
uav_response = '0;
end else begin
if (AV_READLATENCY != 0 || USE_READDATAVALID) begin
uav_response = av_response;
end else begin
uav_response = av_response_delayed;
end
end
end
// assign av_writeresponserequest = uav_writeresponserequest;
assign uav_writeresponsevalid = av_writeresponsevalid;
//-------------------------
//Writedata and Byteenable
//-------------------------
always@* begin
av_byteenable = '0;
av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
end
always@* begin
av_writedata = '0;
av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
end
// +-------------------
// |Calculated Signals
// +-------------------
logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
if(byteenable[i] == 1) begin
return i;
end
end
return '0;
endfunction
reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
reg [AV_ADDRESS_W - 1 : 0] address_reg;
always@(posedge clk, posedge reset) begin
if(reset) begin
burstcount_reg <= '0;
address_reg <= '0;
end else begin
burstcount_reg <= burstcount_reg;
address_reg <= address_reg;
if(av_beginbursttransfer) begin
burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
end
end
end
logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
always@* begin
if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
temp_wire = decode_byteenable(uav_byteenable);
real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
end else begin
real_uav_address = uav_address;
end
av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
av_address = address_reg;
end
always@* begin
av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
av_burstcount = burstcount_reg;
end
always@* begin
av_lock = uav_lock;
end
// -------------------
// Writebyteenable Assignment
// -------------------
always@* begin
av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
end
// -------------------
// Waitrequest Assignment
// -------------------
reg av_waitrequest_generated;
reg av_waitrequest_generated_read;
reg av_waitrequest_generated_write;
reg waitrequest_reset_override;
reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
always@(posedge reset, posedge clk) begin
if(reset) begin
wait_latency_counter <= '0;
waitrequest_reset_override <= 1'h1;
end else begin
waitrequest_reset_override <= 1'h0;
wait_latency_counter <= '0;
if( ~uav_waitrequest | waitrequest_reset_override )
wait_latency_counter <= '0;
else if( uav_read | uav_write )
wait_latency_counter <= wait_latency_counter + 1'h1;
end
end
always @* begin
av_read = uav_read;
av_write = uav_write;
av_waitrequest_generated = 1'h1;
av_waitrequest_generated_read = 1'h1;
av_waitrequest_generated_write = 1'h1;
if(LOG2_OF_LATENCY_SUM == 1)
av_waitrequest_generated = 0;
if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
if(uav_write)
av_waitrequest_generated = av_waitrequest_generated_write;
else
av_waitrequest_generated = av_waitrequest_generated_read;
end
if(USE_WAITREQUEST) begin
uav_waitrequest = av_waitrequest;
end else begin
uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
end
end
// --------------
// Readdata Assignment
// --------------
reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
always@(posedge clk, posedge reset) begin
if(reset)
av_readdata_pre <= 'b0;
else
av_readdata_pre <= av_readdata;
end
always@* begin
uav_readdata = {UAV_DATA_W{1'b0}};
if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin
uav_readdata[AV_DATA_W-1:0] = av_readdata;
end else begin
uav_readdata[AV_DATA_W-1:0] = av_readdata_pre;
end
end
// -------------------
// Readdatavalid Assigment
// -------------------
reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
reg top_read_latency_shift_reg;
always@* begin
uav_readdatavalid=top_read_latency_shift_reg;
if(USE_READDATAVALID) begin
uav_readdatavalid = av_readdatavalid;
end
end
always@* begin
top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
top_read_latency_shift_reg=read_latency_shift_reg;
end
if (AV_READLATENCY > 1) begin
top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
end
end
always@(posedge reset, posedge clk) begin
if (reset) begin
read_latency_shift_reg <= '0;
end else if (av_clken) begin
read_latency_shift_reg[0] <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override;
for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
end
end
end
// ------------
// Chipselect and OutputEnable
// ------------
reg av_chipselect_pre;
wire cs_extension;
reg av_outputenable_pre;
assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
always@(posedge reset, posedge clk) begin
if(reset)
av_outputenable_pre <= 1'b0;
else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 )
av_outputenable_pre <= 0;
else
av_outputenable_pre <= cs_extension | uav_read;
end
always@(posedge reset, posedge clk) begin
if(reset) begin
av_chipselect_pre <= 1'b0;
end else begin
av_chipselect_pre <= 1'b0;
if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
//The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
//There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
if(uav_read) begin
av_chipselect_pre <= 1'b1;
end else if(cs_extension == 1) begin
av_chipselect_pre <= 1'b1;
end
end
end
end
// -------------------
// Begintransfer Assigment
// -------------------
reg end_begintransfer;
always@* begin
av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
end
always@ ( posedge clk or posedge reset ) begin
if(reset) begin
end_begintransfer <= 1'b0;
end else begin
if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
end_begintransfer <= 1'b1;
else if(uav_waitrequest)
end_begintransfer <= end_begintransfer;
else
end_begintransfer <= 1'b0;
end
end
// -------------------
// Beginbursttransfer Assigment
// -------------------
reg end_beginbursttransfer;
reg in_transfer;
always@* begin
av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
end
always@ ( posedge clk or posedge reset ) begin
if(reset) begin
end_beginbursttransfer <= 1'b0;
in_transfer <= 1'b0;
end else begin
end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
if(uav_write && uav_burstcount == symbols_per_word)
in_transfer <=1'b0;
else if(uav_write)
in_transfer <=1'b1;
end
end
endmodule

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# (C) 2001-2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions and other
# software and tools, and its AMPP partner logic functions, and any output
# files from any of the foregoing (including device programming or simulation
# files), and any associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License Subscription
# Agreement, Intel FPGA IP License Agreement, or other applicable
# license agreement, including, without limitation, that your use is for the
# sole purpose of programming logic devices manufactured by Intel and sold by
# Intel or its authorized distributors. Please refer to the applicable
# agreement for further details.
# +---------------------------------------------------
# | Cut the async clear paths
# +---------------------------------------------------
set aclr_counter 0
set clrn_counter 0
set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
set aclr_counter [get_collection_size $aclr_collection]
set clrn_counter [get_collection_size $clrn_collection]
if {$aclr_counter > 0} {
set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
}
if {$clrn_counter > 0} {
set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
}

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule

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module dec
#(m = 8)
(
//clock and reset
input logic clk, clrn,
//control slave
input logic ctl_wr, ctl_rd,
input logic ctl_addr,
input logic [31:0] ctl_wrdata,
output logic [31:0] ctl_rddata,
//memory slave
input logic ram_wr,
input logic [1:0] ram_addr,
input logic [31:0] ram_wrdata,
//external ports
input logic train,
output logic red, yellow, green
);
logic run;
logic [1:0] divider;
logic [m-1:0] divisor;
logic [1:0] contr;
logic [2:0] colors;
logic [m-1:0] cntdiv;
logic enacnt;
//control slave logic
always_ff @ (posedge clk or negedge clrn)
begin
if (!clrn)
begin
run <= 0;
divider <= 0;
end
else
begin
if (ctl_wr)
begin
case (ctl_addr)
1'b0: run <= ctl_wrdata[0];
1'b1: divider <= ctl_wrdata[1:0];
endcase
end
end
end
always_comb
begin
case (ctl_addr)
1'b0: ctl_rddata = {31'b0,run};
1'b1: ctl_rddata = {30'b0,divider};
default: ctl_rddata = 'bx;
endcase
end
//semaphore logic
always_ff @ (posedge clk or negedge clrn)
begin
if (!clrn) cntdiv<=0;
else
begin
if (train | ~run) cntdiv<=0;
else
begin
if (enacnt) cntdiv<=0;
else cntdiv<=cntdiv+1;
end
end
end
always_comb
begin
enacnt=(cntdiv==divisor);
end
always_ff @ (posedge clk or negedge clrn)
begin
if (!clrn)
begin
colors <= 3'b100;
end
else
begin
if (train | ~run)
begin
colors <= 3'b100;
end
else
begin
if (enacnt)
begin
case (colors)
3'b100: colors <= 3'b010;
3'b010: colors <= 3'b011;
3'b011: colors <= 3'b001;
3'b001: colors <= 3'b001;
default: colors <= 3'b100;
endcase
end
end
end
end
always_comb
begin
case (colors)
3'b100: contr = 2'b00;
3'b010: contr = 2'b01;
3'b011: contr = 2'b10;
3'b001: contr = 2'b11;
default : contr = 2'b00;
endcase
end
assign red = colors[2];
assign yellow = colors[1];
assign green = colors[0];
periodram b2v_inst3(
.clock(clk),
.data (ram_wrdata),
.wraddress (ram_addr),
.wren (ram_wr),
.rdaddress({divider,contr}),
.q(divisor)
);
endmodule

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// niosII_cpu.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 18.1 625
`timescale 1 ps / 1 ps
module niosII_cpu (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [17:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [17:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
niosII_cpu_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule

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# Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
# use of Altera Corporation's design tools, logic functions and other
# software and tools, and its AMPP partner logic functions, and any
# output files any of the foregoing (including device programming or
# simulation files), and any associated documentation or information are
# expressly subject to the terms and conditions of the Altera Program
# License Subscription Agreement or other applicable license agreement,
# including, without limitation, that your use is for the sole purpose
# of programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
#**************************************************************
# Timequest JTAG clock definition
# Uncommenting the following lines will define the JTAG
# clock in TimeQuest Timing Analyzer
#**************************************************************
#create_clock -period 10MHz {altera_reserved_tck}
#set_clock_groups -asynchronous -group {altera_reserved_tck}
#**************************************************************
# Set TCL Path Variables
#**************************************************************
set niosII_cpu_cpu niosII_cpu_cpu:*
set niosII_cpu_cpu_oci niosII_cpu_cpu_nios2_oci:the_niosII_cpu_cpu_nios2_oci
set niosII_cpu_cpu_oci_break niosII_cpu_cpu_nios2_oci_break:the_niosII_cpu_cpu_nios2_oci_break
set niosII_cpu_cpu_ocimem niosII_cpu_cpu_nios2_ocimem:the_niosII_cpu_cpu_nios2_ocimem
set niosII_cpu_cpu_oci_debug niosII_cpu_cpu_nios2_oci_debug:the_niosII_cpu_cpu_nios2_oci_debug
set niosII_cpu_cpu_wrapper niosII_cpu_cpu_debug_slave_wrapper:the_niosII_cpu_cpu_debug_slave_wrapper
set niosII_cpu_cpu_jtag_tck niosII_cpu_cpu_debug_slave_tck:the_niosII_cpu_cpu_debug_slave_tck
set niosII_cpu_cpu_jtag_sysclk niosII_cpu_cpu_debug_slave_sysclk:the_niosII_cpu_cpu_debug_slave_sysclk
set niosII_cpu_cpu_oci_path [format "%s|%s" $niosII_cpu_cpu $niosII_cpu_cpu_oci]
set niosII_cpu_cpu_oci_break_path [format "%s|%s" $niosII_cpu_cpu_oci_path $niosII_cpu_cpu_oci_break]
set niosII_cpu_cpu_ocimem_path [format "%s|%s" $niosII_cpu_cpu_oci_path $niosII_cpu_cpu_ocimem]
set niosII_cpu_cpu_oci_debug_path [format "%s|%s" $niosII_cpu_cpu_oci_path $niosII_cpu_cpu_oci_debug]
set niosII_cpu_cpu_jtag_tck_path [format "%s|%s|%s" $niosII_cpu_cpu_oci_path $niosII_cpu_cpu_wrapper $niosII_cpu_cpu_jtag_tck]
set niosII_cpu_cpu_jtag_sysclk_path [format "%s|%s|%s" $niosII_cpu_cpu_oci_path $niosII_cpu_cpu_wrapper $niosII_cpu_cpu_jtag_sysclk]
set niosII_cpu_cpu_jtag_sr [format "%s|*sr" $niosII_cpu_cpu_jtag_tck_path]
#**************************************************************
# Set False Paths
#**************************************************************
set_false_path -from [get_keepers *$niosII_cpu_cpu_oci_break_path|break_readreg*] -to [get_keepers *$niosII_cpu_cpu_jtag_sr*]
set_false_path -from [get_keepers *$niosII_cpu_cpu_oci_debug_path|*resetlatch] -to [get_keepers *$niosII_cpu_cpu_jtag_sr[33]]
set_false_path -from [get_keepers *$niosII_cpu_cpu_oci_debug_path|monitor_ready] -to [get_keepers *$niosII_cpu_cpu_jtag_sr[0]]
set_false_path -from [get_keepers *$niosII_cpu_cpu_oci_debug_path|monitor_error] -to [get_keepers *$niosII_cpu_cpu_jtag_sr[34]]
set_false_path -from [get_keepers *$niosII_cpu_cpu_ocimem_path|*MonDReg*] -to [get_keepers *$niosII_cpu_cpu_jtag_sr*]
set_false_path -from *$niosII_cpu_cpu_jtag_sr* -to *$niosII_cpu_cpu_jtag_sysclk_path|*jdo*
set_false_path -from sld_hub:*|irf_reg* -to *$niosII_cpu_cpu_jtag_sysclk_path|ir*
set_false_path -from sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1] -to *$niosII_cpu_cpu_oci_debug_path|monitor_go

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//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_cpu_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule

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//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_cpu_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule

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//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_cpu_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
niosII_cpu_cpu_debug_slave_tck the_niosII_cpu_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
niosII_cpu_cpu_debug_slave_sysclk the_niosII_cpu_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic niosII_cpu_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam niosII_cpu_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// niosII_cpu_cpu_debug_slave_phy.sld_instance_index = 0,
// niosII_cpu_cpu_debug_slave_phy.sld_ir_width = 2,
// niosII_cpu_cpu_debug_slave_phy.sld_mfg_id = 70,
// niosII_cpu_cpu_debug_slave_phy.sld_sim_action = "",
// niosII_cpu_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// niosII_cpu_cpu_debug_slave_phy.sld_sim_total_length = 0,
// niosII_cpu_cpu_debug_slave_phy.sld_type_id = 34,
// niosII_cpu_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule

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-- Contents are randomly generated during RTL generation.
WIDTH=32;
DEPTH=256;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
00 : 88997af9;
01 : abaae595;
02 : 32fd14d1;
03 : b66193c4;
04 : c6a6aa09;
05 : 0b43de5b;
06 : d1d93028;
07 : bcd08e2a;
08 : 1c8bae85;
09 : b11dad63;
0a : 864ddf62;
0b : 68301486;
0c : 51a3d8d0;
0d : 7af7d39e;
0e : 4761b503;
0f : 2a976e14;
10 : 98141041;
11 : 4c1f6471;
12 : 41dc0a35;
13 : 7d484ae3;
14 : 2a1329f3;
15 : 44ecf499;
16 : dccdd125;
17 : 240142e9;
18 : 3b7e4b05;
19 : bb92e762;
1a : 4594a3c5;
1b : ea0d940f;
1c : 66525d7c;
1d : 0f552242;
1e : 452bd52d;
1f : d1f4ed11;
20 : 5d590422;
21 : c8016b5f;
22 : 9ab94f07;
23 : 16bac9b4;
24 : fe569ae3;
25 : c6e1e6e7;
26 : 2ff19932;
27 : feb058ad;
28 : 1dcce651;
29 : e18b9bfb;
2a : e2f4fc64;
2b : 05d34847;
2c : 077a8143;
2d : 2ce4207f;
2e : 3f3e5113;
2f : c24d2803;
30 : e289b503;
31 : d16bcd4e;
32 : 57a841cf;
33 : 1194f754;
34 : 5c925a31;
35 : 40fd6946;
36 : e397e5d7;
37 : eada7553;
38 : eba8ec01;
39 : f5b39d0b;
3a : 88af39a3;
3b : 5b7f243e;
3c : 4f2bb4ba;
3d : 9451a234;
3e : 10fd984d;
3f : ad4ef4f7;
40 : 7fe97f8b;
41 : 08ea614d;
42 : 9f2c5cf4;
43 : 3f90b7a2;
44 : 8c2bc774;
45 : 45dd63a5;
46 : 3204329c;
47 : 9909be0d;
48 : be65c97b;
49 : 78f3d4a4;
4a : 3ee8b71c;
4b : 9e9a0de4;
4c : 56db426b;
4d : e6869d81;
4e : 20ab0652;
4f : 05d247ed;
50 : 1edccf12;
51 : 1e483b5a;
52 : 8e48ef1e;
53 : f19aefbf;
54 : 98335d23;
55 : 954ac923;
56 : 4679ced6;
57 : ae18d9b8;
58 : be57db48;
59 : 2af933e3;
5a : 3f04e244;
5b : 5d11c958;
5c : 65bda8cb;
5d : c53fe664;
5e : 797ceac8;
5f : aaa406e5;
60 : f785e24e;
61 : 95510077;
62 : 5b6f55a3;
63 : 2a3c749a;
64 : a92e6ae6;
65 : b2117fb0;
66 : 262a254e;
67 : b8c4da74;
68 : f69070ee;
69 : 9e7f80b8;
6a : 834528b4;
6b : 4aaf6d98;
6c : 96023372;
6d : d11663ed;
6e : 33a3c007;
6f : 0e7f06ee;
70 : 34385787;
71 : 2edfd7b0;
72 : 00d60e4b;
73 : 49535c30;
74 : e83f5c14;
75 : 5e0c4c59;
76 : 1d7b944a;
77 : 6ae69731;
78 : bf8414e4;
79 : 7451c212;
7a : 74ede6d2;
7b : 080eafa5;
7c : f21052d8;
7d : cc0819fb;
7e : 8993e5b6;
7f : e20f2df6;
80 : 0f267a65;
81 : 7a8e8407;
82 : e7be656d;
83 : 01ba4ca3;
84 : 7f998e44;
85 : 29d83420;
86 : 149f9a73;
87 : 643ae51e;
88 : 125714d3;
89 : 6e49dc21;
8a : 0b227946;
8b : 360a837d;
8c : b2187074;
8d : 17b0bdbd;
8e : 938fc73d;
8f : e73f501e;
90 : 70b5b87e;
91 : 2a2aed8a;
92 : f96cc881;
93 : 021b49e1;
94 : 8691600d;
95 : b45e1d12;
96 : 64d9644e;
97 : 486cbaf9;
98 : 386acf20;
99 : 0d1384d4;
9a : 62455f77;
9b : 866fde20;
9c : 006fecec;
9d : 94e84514;
9e : 7babc333;
9f : afaa8445;
a0 : b1175e3a;
a1 : e08de629;
a2 : 7f12a52d;
a3 : 0e322909;
a4 : 18784dc6;
a5 : b23bcc20;
a6 : 266c9e34;
a7 : c857eaf3;
a8 : 2ae3b164;
a9 : 038acf2a;
aa : c1abc60d;
ab : 8af787bd;
ac : 043723a9;
ad : c37c952d;
ae : 693a361f;
af : da4b8e99;
b0 : fb8fdb10;
b1 : 4d6365f2;
b2 : 712358e9;
b3 : 85dae0fa;
b4 : 7e82a418;
b5 : d3493768;
b6 : 739c65ec;
b7 : 73b66b19;
b8 : 22142816;
b9 : ff498322;
ba : 3266495e;
bb : e26e8214;
bc : c8c47131;
bd : 660793d8;
be : 689f8d69;
bf : faae340b;
c0 : 37518ba7;
c1 : f2865fe5;
c2 : 1bb44f3d;
c3 : 3bce44c5;
c4 : aff2d188;
c5 : 985442da;
c6 : 85bb58bd;
c7 : 0c53135d;
c8 : 495f80bc;
c9 : 853c95dc;
ca : dde937f1;
cb : 418f9452;
cc : 7669641c;
cd : 0e752434;
ce : b0fe17a7;
cf : d1be9b88;
d0 : cfbfeb76;
d1 : 80b48a11;
d2 : 9327c69e;
d3 : beca5a88;
d4 : e71d428f;
d5 : b318d275;
d6 : 56fea35e;
d7 : 140cd6bd;
d8 : b8c937ce;
d9 : 540eea36;
da : ee58fc7f;
db : 5615c389;
dc : 46692ad0;
dd : 5c713e51;
de : 6ba95f60;
df : 0e166732;
e0 : ac0e49f5;
e1 : c9a5ea76;
e2 : 05b04d86;
e3 : b29ac712;
e4 : 4e344493;
e5 : d45ede48;
e6 : 3da7e426;
e7 : 4d6a8937;
e8 : 99b59bd4;
e9 : 1f8a5751;
ea : 8b07e64e;
eb : b4dcd496;
ec : 42f84fe6;
ed : f1d5952f;
ee : a2e5a42d;
ef : 15b1af16;
f0 : 168012bc;
f1 : 2e276612;
f2 : 89913eaa;
f3 : c607a1a2;
f4 : fd8b544d;
f5 : aec31a53;
f6 : 25f958ad;
f7 : 365903ec;
f8 : 14761865;
f9 : 568cc23b;
fa : b0386305;
fb : fb9ebd8a;
fc : a25911d4;
fd : 806e3fbb;
fe : 9df35264;
ff : d62b3814;
END;

42
Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_a.mif Normal file
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@ -0,0 +1,42 @@
WIDTH=32;
DEPTH=32;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
00 : deadbeef;
01 : deadbeef;
02 : deadbeef;
03 : deadbeef;
04 : deadbeef;
05 : deadbeef;
06 : deadbeef;
07 : deadbeef;
08 : deadbeef;
09 : deadbeef;
0a : deadbeef;
0b : deadbeef;
0c : deadbeef;
0d : deadbeef;
0e : deadbeef;
0f : deadbeef;
10 : deadbeef;
11 : deadbeef;
12 : deadbeef;
13 : deadbeef;
14 : deadbeef;
15 : deadbeef;
16 : deadbeef;
17 : deadbeef;
18 : deadbeef;
19 : deadbeef;
1a : deadbeef;
1b : deadbeef;
1c : deadbeef;
1d : deadbeef;
1e : deadbeef;
1f : deadbeef;
END;

42
Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_b.mif Normal file
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@ -0,0 +1,42 @@
WIDTH=32;
DEPTH=32;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
00 : deadbeef;
01 : deadbeef;
02 : deadbeef;
03 : deadbeef;
04 : deadbeef;
05 : deadbeef;
06 : deadbeef;
07 : deadbeef;
08 : deadbeef;
09 : deadbeef;
0a : deadbeef;
0b : deadbeef;
0c : deadbeef;
0d : deadbeef;
0e : deadbeef;
0f : deadbeef;
10 : deadbeef;
11 : deadbeef;
12 : deadbeef;
13 : deadbeef;
14 : deadbeef;
15 : deadbeef;
16 : deadbeef;
17 : deadbeef;
18 : deadbeef;
19 : deadbeef;
1a : deadbeef;
1b : deadbeef;
1c : deadbeef;
1d : deadbeef;
1e : deadbeef;
1f : deadbeef;
END;

656
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@ -0,0 +1,656 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_cpu_cpu_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_valid,
F_pcb,
F_valid,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input E_valid;
input [ 17: 0] F_pcb;
input F_valid;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_valid;
input [ 71: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 17: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 17: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_is_opx_inst;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_op_rsv02;
wire D_op_op_rsv09;
wire D_op_op_rsv10;
wire D_op_op_rsv17;
wire D_op_op_rsv18;
wire D_op_op_rsv25;
wire D_op_op_rsv26;
wire D_op_op_rsv33;
wire D_op_op_rsv34;
wire D_op_op_rsv41;
wire D_op_op_rsv42;
wire D_op_op_rsv49;
wire D_op_op_rsv57;
wire D_op_op_rsv61;
wire D_op_op_rsv62;
wire D_op_op_rsv63;
wire D_op_opx_rsv00;
wire D_op_opx_rsv10;
wire D_op_opx_rsv15;
wire D_op_opx_rsv17;
wire D_op_opx_rsv21;
wire D_op_opx_rsv25;
wire D_op_opx_rsv33;
wire D_op_opx_rsv34;
wire D_op_opx_rsv35;
wire D_op_opx_rsv42;
wire D_op_opx_rsv43;
wire D_op_opx_rsv44;
wire D_op_opx_rsv47;
wire D_op_opx_rsv50;
wire D_op_opx_rsv51;
wire D_op_opx_rsv55;
wire D_op_opx_rsv56;
wire D_op_opx_rsv60;
wire D_op_opx_rsv63;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_op_rsv02 = D_iw_op == 2;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_op_rsv09 = D_iw_op == 9;
assign D_op_op_rsv10 = D_iw_op == 10;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_op_rsv17 = D_iw_op == 17;
assign D_op_op_rsv18 = D_iw_op == 18;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_op_rsv25 = D_iw_op == 25;
assign D_op_op_rsv26 = D_iw_op == 26;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_op_rsv33 = D_iw_op == 33;
assign D_op_op_rsv34 = D_iw_op == 34;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_op_rsv41 = D_iw_op == 41;
assign D_op_op_rsv42 = D_iw_op == 42;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_op_rsv49 = D_iw_op == 49;
assign D_op_custom = D_iw_op == 50;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_op_rsv57 = D_iw_op == 57;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_op_rsv61 = D_iw_op == 61;
assign D_op_op_rsv62 = D_iw_op == 62;
assign D_op_op_rsv63 = D_iw_op == 63;
assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
assign D_is_opx_inst = D_iw_op == 58;
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: niosII_cpu_cpu_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: niosII_cpu_cpu_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: niosII_cpu_cpu_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: niosII_cpu_cpu_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: niosII_cpu_cpu_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: niosII_cpu_cpu_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: niosII_cpu_cpu_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: niosII_cpu_cpu_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: niosII_cpu_cpu_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: niosII_cpu_cpu_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: niosII_cpu_cpu_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: niosII_cpu_cpu_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: niosII_cpu_cpu_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: niosII_cpu_cpu_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: niosII_cpu_cpu_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: niosII_cpu_cpu_test_bench/W_wr_data is 'x'\n", $time);
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -------------------------------------------------------
// Altera IRQ Mapper
//
// Parameters
// NUM_RCVRS : 2
// SENDER_IRW_WIDTH : 32
// IRQ_MAP : 0:0,1:1
//
// -------------------------------------------------------
`timescale 1 ns / 1 ns
module niosII_irq_mapper
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// IRQ Receivers
// -------------------
input receiver0_irq,
input receiver1_irq,
// -------------------
// Command Source (Output)
// -------------------
output reg [31 : 0] sender_irq
);
always @* begin
sender_irq = 0;
sender_irq[0] = receiver0_irq;
sender_irq[1] = receiver1_irq;
end
endmodule

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//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosII_jtag_uart_sim_scfifo_w the_niosII_jtag_uart_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosII_jtag_uart_sim_scfifo_r the_niosII_jtag_uart_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_jtag_uart (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
niosII_jtag_uart_scfifo_w the_niosII_jtag_uart_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
niosII_jtag_uart_scfifo_r the_niosII_jtag_uart_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic niosII_jtag_uart_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam niosII_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
// niosII_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// niosII_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// niosII_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule

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//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_mem (
// inputs:
address,
address2,
byteenable,
byteenable2,
chipselect,
chipselect2,
clk,
clken,
clken2,
freeze,
reset,
reset_req,
write,
write2,
writedata,
writedata2,
// outputs:
readdata,
readdata2
)
;
parameter INIT_FILE = "niosII_mem.hex";
output [ 31: 0] readdata;
output [ 31: 0] readdata2;
input [ 14: 0] address;
input [ 14: 0] address2;
input [ 3: 0] byteenable;
input [ 3: 0] byteenable2;
input chipselect;
input chipselect2;
input clk;
input clken;
input clken2;
input freeze;
input reset;
input reset_req;
input write;
input write2;
input [ 31: 0] writedata;
input [ 31: 0] writedata2;
wire clocken0;
wire not_clken;
wire not_clken2;
wire [ 31: 0] readdata;
wire [ 31: 0] readdata2;
wire wren;
wire wren2;
assign wren = chipselect & write & clken;
assign not_clken = ~clken;
assign not_clken2 = ~clken2;
assign clocken0 = ~reset_req;
assign wren2 = chipselect2 & write2 & clken2;
altsyncram the_altsyncram
(
.address_a (address),
.address_b (address2),
.addressstall_a (not_clken),
.addressstall_b (not_clken2),
.byteena_a (byteenable),
.byteena_b (byteenable2),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.data_b (writedata2),
.q_a (readdata),
.q_b (readdata2),
.wren_a (wren),
.wren_b (wren2)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.byte_size = 8,
the_altsyncram.byteena_reg_b = "CLOCK0",
the_altsyncram.indata_reg_b = "CLOCK0",
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 32768,
the_altsyncram.numwords_a = 32768,
the_altsyncram.numwords_b = 32768,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.width_byteena_b = 4,
the_altsyncram.widthad_a = 15,
the_altsyncram.widthad_b = 15,
the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK0";
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule

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// niosII_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 18.1 625
`timescale 1 ps / 1 ps
module niosII_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
// $Revision: #1 $
// $Date: 2013/09/09 $
// $Author: dmunday $
// --------------------------------------------------------------------------------
//| Avalon Streaming Error Adapter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
// ------------------------------------------
// Generation parameters:
// output_name: niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
// use_ready: true
// use_packets: false
// use_empty: 0
// empty_width: 0
// data_width: 34
// channel_width: 0
// in_error_width: 0
// out_error_width: 1
// in_errors_list
// in_errors_indices 0
// out_errors_list
// has_in_error_desc: FALSE
// has_out_error_desc: FALSE
// out_has_other: FALSE
// out_other_index: -1
// dumpVar:
// inString: in_error[
// closeString: ] |
// ------------------------------------------
module niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
(
// Interface: in
output reg in_ready,
input in_valid,
input [34-1: 0] in_data,
// Interface: out
input out_ready,
output reg out_valid,
output reg [34-1: 0] out_data,
output reg [0:0] out_error,
// Interface: clk
input clk,
// Interface: reset
input reset_n
/*AUTOARG*/);
reg in_error = 0;
initial in_error = 0;
// ---------------------------------------------------------------------
//| Pass-through Mapping
// ---------------------------------------------------------------------
always_comb begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
end
// ---------------------------------------------------------------------
//| Error Mapping
// ---------------------------------------------------------------------
always_comb begin
out_error = 0;
out_error = in_error;
end //always @*
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -------------------------------------
// Merlin Demultiplexer
//
// Asserts valid on the appropriate output
// given a one-hot channel signal.
// -------------------------------------
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// output_name: niosII_mm_interconnect_0_cmd_demux
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// NUM_OUTPUTS: 6
// VALID_WIDTH: 1
// ------------------------------------------
//------------------------------------------
// Message Supression Used
// QIS Warnings
// 15610 - Warning: Design contains x input pin(s) that do not drive logic
//------------------------------------------
module niosII_mm_interconnect_0_cmd_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [94-1 : 0] sink_data, // ST_DATA_W=94
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [94-1 : 0] src0_data, // ST_DATA_W=94
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [94-1 : 0] src1_data, // ST_DATA_W=94
output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [94-1 : 0] src2_data, // ST_DATA_W=94
output reg [7-1 : 0] src2_channel, // ST_CHANNEL_W=7
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
output reg src3_valid,
output reg [94-1 : 0] src3_data, // ST_DATA_W=94
output reg [7-1 : 0] src3_channel, // ST_CHANNEL_W=7
output reg src3_startofpacket,
output reg src3_endofpacket,
input src3_ready,
output reg src4_valid,
output reg [94-1 : 0] src4_data, // ST_DATA_W=94
output reg [7-1 : 0] src4_channel, // ST_CHANNEL_W=7
output reg src4_startofpacket,
output reg src4_endofpacket,
input src4_ready,
output reg src5_valid,
output reg [94-1 : 0] src5_data, // ST_DATA_W=94
output reg [7-1 : 0] src5_channel, // ST_CHANNEL_W=7
output reg src5_startofpacket,
output reg src5_endofpacket,
input src5_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 6;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
src2_data = sink_data;
src2_startofpacket = sink_startofpacket;
src2_endofpacket = sink_endofpacket;
src2_channel = sink_channel >> NUM_OUTPUTS;
src2_valid = sink_channel[2] && sink_valid;
src3_data = sink_data;
src3_startofpacket = sink_startofpacket;
src3_endofpacket = sink_endofpacket;
src3_channel = sink_channel >> NUM_OUTPUTS;
src3_valid = sink_channel[3] && sink_valid;
src4_data = sink_data;
src4_startofpacket = sink_startofpacket;
src4_endofpacket = sink_endofpacket;
src4_channel = sink_channel >> NUM_OUTPUTS;
src4_valid = sink_channel[4] && sink_valid;
src5_data = sink_data;
src5_startofpacket = sink_startofpacket;
src5_endofpacket = sink_endofpacket;
src5_channel = sink_channel >> NUM_OUTPUTS;
src5_valid = sink_channel[5] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign ready_vector[2] = src2_ready;
assign ready_vector[3] = src3_ready;
assign ready_vector[4] = src4_ready;
assign ready_vector[5] = src5_ready;
assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -------------------------------------
// Merlin Demultiplexer
//
// Asserts valid on the appropriate output
// given a one-hot channel signal.
// -------------------------------------
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// output_name: niosII_mm_interconnect_0_cmd_demux_001
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// NUM_OUTPUTS: 2
// VALID_WIDTH: 1
// ------------------------------------------
//------------------------------------------
// Message Supression Used
// QIS Warnings
// 15610 - Warning: Design contains x input pin(s) that do not drive logic
//------------------------------------------
module niosII_mm_interconnect_0_cmd_demux_001
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [94-1 : 0] sink_data, // ST_DATA_W=94
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [94-1 : 0] src0_data, // ST_DATA_W=94
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [94-1 : 0] src1_data, // ST_DATA_W=94
output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & {{5{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// ------------------------------------------
// Merlin Multiplexer
// ------------------------------------------
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// output_name: niosII_mm_interconnect_0_cmd_mux
// NUM_INPUTS: 1
// ARBITRATION_SHARES: 1
// ARBITRATION_SCHEME "round-robin"
// PIPELINE_ARB: 1
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// ------------------------------------------
module niosII_mm_interconnect_0_cmd_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [94-1 : 0] sink0_data,
input [7-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [94-1 : 0] src_data,
output [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 94 + 7 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam PKT_TRANS_LOCK = 58;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// ------------------------------------------
// Merlin Multiplexer
// ------------------------------------------
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// output_name: niosII_mm_interconnect_0_cmd_mux_002
// NUM_INPUTS: 2
// ARBITRATION_SHARES: 1 1
// ARBITRATION_SCHEME "round-robin"
// PIPELINE_ARB: 1
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// ------------------------------------------
module niosII_mm_interconnect_0_cmd_mux_002
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [94-1 : 0] sink0_data,
input [7-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [94-1 : 0] sink1_data,
input [7-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [94-1 : 0] src_data,
output [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 94 + 7 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam PKT_TRANS_LOCK = 58;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
wire [NUM_INPUTS - 1 : 0] eop;
assign eop[0] = sink0_endofpacket;
assign eop[1] = sink1_endofpacket;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[58];
lock[1] = sink1_data[58];
end
reg [NUM_INPUTS - 1 : 0] locked = '0;
always @(posedge clk or posedge reset) begin
if (reset) begin
locked <= '0;
end
else begin
locked <= next_grant & lock;
end
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (update_grant) begin
share_count <= next_grant_share;
share_count_zero_flag <= (next_grant_share == '0);
end
else if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
always @* begin
update_grant = 0;
// ------------------------------------------
// The pipeline delays grant by one cycle, so
// we have to calculate the update_grant signal
// one cycle ahead of time.
//
// Possible optimization: omit the first clause
// "if (!packet_in_progress & ~src_valid) ..."
// cost: one idle cycle at the the beginning of each
// grant cycle.
// benefit: save a small amount of logic.
// ------------------------------------------
if (!packet_in_progress & !src_valid)
update_grant = 1;
if (last_cycle && share_count_zero_flag)
update_grant = 1;
end
wire save_grant;
assign save_grant = update_grant;
assign grant = saved_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] prev_request;
always @(posedge clk, posedge reset) begin
if (reset)
prev_request <= '0;
else
prev_request <= request & ~(valid & eop);
end
assign request = (PIPELINE_ARB == 1) ? valid | locked :
prev_request | valid | locked;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("round-robin"),
.PIPELINE (1)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -------------------------------------------------------
// Merlin Router
//
// Asserts the appropriate one-hot encoded channel based on
// either (a) the address or (b) the dest id. The DECODER_TYPE
// parameter controls this behaviour. 0 means address decoder,
// 1 means dest id decoder.
//
// In the case of (a), it also sets the destination id.
// -------------------------------------------------------
`timescale 1 ns / 1 ns
module niosII_mm_interconnect_0_router_default_decode
#(
parameter DEFAULT_CHANNEL = 5,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 3
)
(output [80 - 78 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[80 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
module niosII_mm_interconnect_0_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [94-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [94-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 53;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 80;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 84;
localparam PKT_PROTECTION_L = 82;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 56;
localparam PKT_TRANS_READ = 57;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h20000 - 64'h0);
localparam PAD1 = log2ceil(64'h21000 - 64'h20800);
localparam PAD2 = log2ceil(64'h21020 - 64'h21000);
localparam PAD3 = log2ceil(64'h21030 - 64'h21020);
localparam PAD4 = log2ceil(64'h21038 - 64'h21030);
localparam PAD5 = log2ceil(64'h21040 - 64'h21038);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h21040;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [7-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire write_transaction;
assign write_transaction = sink_data[PKT_TRANS_WRITE];
niosII_mm_interconnect_0_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x0 .. 0x20000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0 ) begin
src_channel = 7'b100000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x20800 .. 0x21000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800 ) begin
src_channel = 7'b000100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// ( 0x21000 .. 0x21020 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h21000 ) begin
src_channel = 7'b010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
end
// ( 0x21020 .. 0x21030 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h21020 && write_transaction ) begin
src_channel = 7'b001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x21030 .. 0x21038 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h21030 ) begin
src_channel = 7'b000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
// ( 0x21038 .. 0x21040 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 18'h21038 ) begin
src_channel = 7'b000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -------------------------------------------------------
// Merlin Router
//
// Asserts the appropriate one-hot encoded channel based on
// either (a) the address or (b) the dest id. The DECODER_TYPE
// parameter controls this behaviour. 0 means address decoder,
// 1 means dest id decoder.
//
// In the case of (a), it also sets the destination id.
// -------------------------------------------------------
`timescale 1 ns / 1 ns
module niosII_mm_interconnect_0_router_001_default_decode
#(
parameter DEFAULT_CHANNEL = 1,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 2
)
(output [80 - 78 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[80 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
module niosII_mm_interconnect_0_router_001
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [94-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [94-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 53;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 80;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 84;
localparam PKT_PROTECTION_L = 82;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 56;
localparam PKT_TRANS_READ = 57;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h20000 - 64'h0);
localparam PAD1 = log2ceil(64'h21000 - 64'h20800);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h21000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [7-1 : 0] default_src_channel;
niosII_mm_interconnect_0_router_001_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x0 .. 0x20000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0 ) begin
src_channel = 7'b10;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x20800 .. 0x21000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800 ) begin
src_channel = 7'b01;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -------------------------------------------------------
// Merlin Router
//
// Asserts the appropriate one-hot encoded channel based on
// either (a) the address or (b) the dest id. The DECODER_TYPE
// parameter controls this behaviour. 0 means address decoder,
// 1 means dest id decoder.
//
// In the case of (a), it also sets the destination id.
// -------------------------------------------------------
`timescale 1 ns / 1 ns
module niosII_mm_interconnect_0_router_002_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [80 - 78 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[80 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
module niosII_mm_interconnect_0_router_002
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [94-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [94-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 53;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 80;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 84;
localparam PKT_PROTECTION_L = 82;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 56;
localparam PKT_TRANS_READ = 57;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [7-1 : 0] default_src_channel;
niosII_mm_interconnect_0_router_002_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 7'b1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -------------------------------------------------------
// Merlin Router
//
// Asserts the appropriate one-hot encoded channel based on
// either (a) the address or (b) the dest id. The DECODER_TYPE
// parameter controls this behaviour. 0 means address decoder,
// 1 means dest id decoder.
//
// In the case of (a), it also sets the destination id.
// -------------------------------------------------------
`timescale 1 ns / 1 ns
module niosII_mm_interconnect_0_router_004_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [80 - 78 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[80 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
module niosII_mm_interconnect_0_router_004
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [94-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [94-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 53;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 80;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 84;
localparam PKT_PROTECTION_L = 82;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 56;
localparam PKT_TRANS_READ = 57;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [7-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
niosII_mm_interconnect_0_router_004_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 7'b01;
end
if (destid == 1 && read_transaction) begin
src_channel = 7'b10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -------------------------------------------------------
// Merlin Router
//
// Asserts the appropriate one-hot encoded channel based on
// either (a) the address or (b) the dest id. The DECODER_TYPE
// parameter controls this behaviour. 0 means address decoder,
// 1 means dest id decoder.
//
// In the case of (a), it also sets the destination id.
// -------------------------------------------------------
`timescale 1 ns / 1 ns
module niosII_mm_interconnect_0_router_008_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 1
)
(output [80 - 78 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[80 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
module niosII_mm_interconnect_0_router_008
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [94-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [94-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 53;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 80;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 84;
localparam PKT_PROTECTION_L = 82;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 56;
localparam PKT_TRANS_READ = 57;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [7-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
niosII_mm_interconnect_0_router_008_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 1 && read_transaction) begin
src_channel = 7'b1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -------------------------------------
// Merlin Demultiplexer
//
// Asserts valid on the appropriate output
// given a one-hot channel signal.
// -------------------------------------
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// output_name: niosII_mm_interconnect_0_rsp_demux
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// NUM_OUTPUTS: 1
// VALID_WIDTH: 1
// ------------------------------------------
//------------------------------------------
// Message Supression Used
// QIS Warnings
// 15610 - Warning: Design contains x input pin(s) that do not drive logic
//------------------------------------------
module niosII_mm_interconnect_0_rsp_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [94-1 : 0] sink_data, // ST_DATA_W=94
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [94-1 : 0] src0_data, // ST_DATA_W=94
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{6{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// ------------------------------------------
// Merlin Multiplexer
// ------------------------------------------
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// output_name: niosII_mm_interconnect_0_rsp_mux
// NUM_INPUTS: 6
// ARBITRATION_SHARES: 1 1 1 1 1 1
// ARBITRATION_SCHEME "no-arb"
// PIPELINE_ARB: 0
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// ------------------------------------------
module niosII_mm_interconnect_0_rsp_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [94-1 : 0] sink0_data,
input [7-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [94-1 : 0] sink1_data,
input [7-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
input sink2_valid,
input [94-1 : 0] sink2_data,
input [7-1: 0] sink2_channel,
input sink2_startofpacket,
input sink2_endofpacket,
output sink2_ready,
input sink3_valid,
input [94-1 : 0] sink3_data,
input [7-1: 0] sink3_channel,
input sink3_startofpacket,
input sink3_endofpacket,
output sink3_ready,
input sink4_valid,
input [94-1 : 0] sink4_data,
input [7-1: 0] sink4_channel,
input sink4_startofpacket,
input sink4_endofpacket,
output sink4_ready,
input sink5_valid,
input [94-1 : 0] sink5_data,
input [7-1: 0] sink5_channel,
input sink5_startofpacket,
input sink5_endofpacket,
output sink5_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [94-1 : 0] src_data,
output [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 94 + 7 + 2;
localparam NUM_INPUTS = 6;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam PKT_TRANS_LOCK = 58;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
wire [PAYLOAD_W - 1 : 0] sink2_payload;
wire [PAYLOAD_W - 1 : 0] sink3_payload;
wire [PAYLOAD_W - 1 : 0] sink4_payload;
wire [PAYLOAD_W - 1 : 0] sink5_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
assign valid[2] = sink2_valid;
assign valid[3] = sink3_valid;
assign valid[4] = sink4_valid;
assign valid[5] = sink5_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[58];
lock[1] = sink1_data[58];
lock[2] = sink2_data[58];
lock[3] = sink3_data[58];
lock[4] = sink4_data[58];
lock[5] = sink5_data[58];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
// 2 | 1 | 0
// 3 | 1 | 0
// 4 | 1 | 0
// 5 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
share_5 & { SHARE_COUNTER_W {next_grant[5]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
wire final_packet_2 = 1'b1;
wire final_packet_3 = 1'b1;
wire final_packet_4 = 1'b1;
wire final_packet_5 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_5,
final_packet_4,
final_packet_3,
final_packet_2,
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign sink2_ready = src_ready && grant[2];
assign sink3_ready = src_ready && grant[3];
assign sink4_ready = src_ready && grant[4];
assign sink5_ready = src_ready && grant[5];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} } |
sink2_payload & {PAYLOAD_W {grant[2]} } |
sink3_payload & {PAYLOAD_W {grant[3]} } |
sink4_payload & {PAYLOAD_W {grant[4]} } |
sink5_payload & {PAYLOAD_W {grant[5]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign sink2_payload = {sink2_channel,sink2_data,
sink2_startofpacket,sink2_endofpacket};
assign sink3_payload = {sink3_channel,sink3_data,
sink3_startofpacket,sink3_endofpacket};
assign sink4_payload = {sink4_channel,sink4_data,
sink4_startofpacket,sink4_endofpacket};
assign sink5_payload = {sink5_channel,sink5_data,
sink5_startofpacket,sink5_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule

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// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// ------------------------------------------
// Merlin Multiplexer
// ------------------------------------------
`timescale 1 ns / 1 ns
// ------------------------------------------
// Generation parameters:
// output_name: niosII_mm_interconnect_0_rsp_mux_001
// NUM_INPUTS: 2
// ARBITRATION_SHARES: 1 1
// ARBITRATION_SCHEME "no-arb"
// PIPELINE_ARB: 0
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// ------------------------------------------
module niosII_mm_interconnect_0_rsp_mux_001
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [94-1 : 0] sink0_data,
input [7-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [94-1 : 0] sink1_data,
input [7-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [94-1 : 0] src_data,
output [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 94 + 7 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam PKT_TRANS_LOCK = 58;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[58];
lock[1] = sink1_data[58];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule

211
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@ -0,0 +1,211 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_sys_clk_timer (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'hC34F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 49999;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register[0];
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule

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// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: periodram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.2 Build 209 09/17/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module periodram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [3:0] rdaddress;
input [1:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4,
altsyncram_component.numwords_b = 16,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 2,
altsyncram_component.widthad_b = 4,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "128"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]"
// Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL "wraddress[1..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

9
Top/semafor.qsf
View File

@ -38,7 +38,7 @@
set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7 set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY semafor set_global_assignment -name TOP_LEVEL_ENTITY niosII
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:34:55 OCTOBER 18, 2022" set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:34:55 OCTOBER 18, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
@ -50,3 +50,10 @@ set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)" set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name QSYS_FILE niosII.qsys
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top