pt2.2 nios new project, clk renaming
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<?xml version="1.0" encoding="UTF-8"?>
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<system name="$${FILENAME}">
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<component
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name="$${FILENAME}"
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displayName="$${FILENAME}"
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version="1.0"
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description=""
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tags=""
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categories="" />
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<parameter name="bonusData"><![CDATA[bonusData
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{
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element clk
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
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<parameter name="device" value="EP4CE115F29C7" />
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<parameter name="deviceFamily" value="Cyclone IV E" />
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<parameter name="deviceSpeedGrade" value="7" />
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<parameter name="fabricMode" value="QSYS" />
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<parameter name="generateLegacySim" value="false" />
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<parameter name="generationId" value="0" />
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<parameter name="globalResetBus" value="false" />
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<parameter name="hdlLanguage" value="VERILOG" />
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<parameter name="hideFromIPCatalog" value="false" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="1" />
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<parameter name="projectName" value="" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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<parameter name="timeStamp" value="0" />
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface name="clk" internal="clk.clk_in" type="clock" dir="end" />
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<interface name="reset" internal="clk.clk_in_reset" type="reset" dir="end" />
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<module name="clk" kind="clock_source" version="18.1" enabled="1">
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<parameter name="clockFrequency" value="50000000" />
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<parameter name="clockFrequencyKnown" value="true" />
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<parameter name="inputClockFrequency" value="0" />
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<parameter name="resetSynchronousEdges" value="NONE" />
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</module>
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<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
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<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
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</system>
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 0 0 224 144)
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(text "niosII" (rect 98 -1 118 11)(font "Arial" (font_size 10)))
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(text "inst" (rect 8 128 20 140)(font "Arial" ))
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(port
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(pt 0 72)
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(input)
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(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
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(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
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(line (pt 0 72)(pt 80 72)(line_width 1))
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)
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(port
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(pt 0 112)
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(input)
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(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
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(text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8)))
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(line (pt 0 112)(pt 80 112)(line_width 1))
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)
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(drawing
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(text "clk" (rect 65 43 148 99)(font "Arial" (color 128 0 0)(font_size 9)))
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(text "clk" (rect 85 67 188 144)(font "Arial" (color 0 0 0)))
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(text "reset" (rect 51 83 132 179)(font "Arial" (color 128 0 0)(font_size 9)))
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(text "reset_n" (rect 85 107 212 224)(font "Arial" (color 0 0 0)))
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(text " system " (rect 189 128 426 266)(font "Arial" ))
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(line (pt 80 32)(pt 144 32)(line_width 1))
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(line (pt 144 32)(pt 144 128)(line_width 1))
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(line (pt 80 128)(pt 144 128)(line_width 1))
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(line (pt 80 32)(pt 80 128)(line_width 1))
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(line (pt 81 52)(pt 81 76)(line_width 1))
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(line (pt 82 52)(pt 82 76)(line_width 1))
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(line (pt 81 92)(pt 81 116)(line_width 1))
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(line (pt 82 92)(pt 82 116)(line_width 1))
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(line (pt 0 0)(pt 224 0)(line_width 1))
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(line (pt 224 0)(pt 224 144)(line_width 1))
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(line (pt 0 144)(pt 224 144)(line_width 1))
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(line (pt 0 0)(pt 0 144)(line_width 1))
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)
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)
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component niosII is
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port (
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clk_clk : in std_logic := 'X'; -- clk
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reset_reset_n : in std_logic := 'X' -- reset_n
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);
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end component niosII;
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@ -0,0 +1,8 @@
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module niosII (
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clk_clk,
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reset_reset_n);
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input clk_clk;
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input reset_reset_n;
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endmodule
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@ -0,0 +1,5 @@
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niosII u0 (
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.clk_clk (<connected-to-clk_clk>), // clk.clk
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.reset_reset_n (<connected-to-reset_reset_n>) // reset.reset_n
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);
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@ -0,0 +1,13 @@
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component niosII is
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port (
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clk_clk : in std_logic := 'X'; -- clk
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reset_reset_n : in std_logic := 'X' -- reset_n
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);
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end component niosII;
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u0 : component niosII
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port map (
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clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
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reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
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);
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