This website requires JavaScript.
Explore
Help
Register
Sign In
ivan-igorevich
/
fpga-lab-2
Watch
0
Star
0
Fork
You've already forked fpga-lab-2
0
Code
Issues
Pull Requests
Packages
Projects
Releases
Wiki
Activity
bf8ac6bb98
fpga-lab-2
/
Top
/
niosII
/
niosII_bb.v
9 lines
96 B
Verilog
Raw
Blame
History
module
niosII
(
clk_clk
,
reset_reset_n
)
;
input
clk_clk
;
input
reset_reset_n
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink