ivan-igorevich
/
fpga-lab-2
0
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

pt2.2 nios new project, clk renaming

This commit is contained in:
Ivan I. Ovchinnikov 2022-10-18 16:52:06 +03:00
parent a42e284fff
commit bf8ac6bb98
6 changed files with 145 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
Top/niosII.qsys Normal file
View File

@ -0,0 +1,53 @@
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="" />
<parameter name="bonusData"><![CDATA[bonusData
{
element clk
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="EP4CE115F29C7" />
<parameter name="deviceFamily" value="Cyclone IV E" />
<parameter name="deviceSpeedGrade" value="7" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk.clk_in" type="clock" dir="end" />
<interface name="reset" internal="clk.clk_in_reset" type="reset" dir="end" />
<module name="clk" kind="clock_source" version="18.1" enabled="1">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>

59
Top/niosII/niosII.bsf Normal file
View File

@ -0,0 +1,59 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 224 144)
(text "niosII" (rect 98 -1 118 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 128 20 140)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 80 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
(text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 80 112)(line_width 1))
)
(drawing
(text "clk" (rect 65 43 148 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 85 67 188 144)(font "Arial" (color 0 0 0)))
(text "reset" (rect 51 83 132 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 85 107 212 224)(font "Arial" (color 0 0 0)))
(text " system " (rect 189 128 426 266)(font "Arial" ))
(line (pt 80 32)(pt 144 32)(line_width 1))
(line (pt 144 32)(pt 144 128)(line_width 1))
(line (pt 80 128)(pt 144 128)(line_width 1))
(line (pt 80 32)(pt 80 128)(line_width 1))
(line (pt 81 52)(pt 81 76)(line_width 1))
(line (pt 82 52)(pt 82 76)(line_width 1))
(line (pt 81 92)(pt 81 116)(line_width 1))
(line (pt 82 92)(pt 82 116)(line_width 1))
(line (pt 0 0)(pt 224 0)(line_width 1))
(line (pt 224 0)(pt 224 144)(line_width 1))
(line (pt 0 144)(pt 224 144)(line_width 1))
(line (pt 0 0)(pt 0 144)(line_width 1))
)
)

7
Top/niosII/niosII.cmp Normal file
View File

@ -0,0 +1,7 @@
component niosII is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component niosII;

8
Top/niosII/niosII_bb.v Normal file
View File

@ -0,0 +1,8 @@
module niosII (
clk_clk,
reset_reset_n);
input clk_clk;
input reset_reset_n;
endmodule

5
Top/niosII/niosII_inst.v Normal file
View File

@ -0,0 +1,5 @@
niosII u0 (
.clk_clk (<connected-to-clk_clk>), // clk.clk
.reset_reset_n (<connected-to-reset_reset_n>) // reset.reset_n
);

13
Top/niosII/niosII_inst.vhd Normal file
View File

@ -0,0 +1,13 @@
component niosII is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component niosII;
u0 : component niosII
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
);