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ivan-igorevich:simulation
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compare: ivan-igorevich:f6d43e003a7f726eb7e62c72f07769613a81abdc
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ivan-igorevich:simulation
ivan-igorevich:lab3
ivan-igorevich:master

3 Commits
56257bbcaf ... f6d43e003a

Author SHA1 Message Date
Ivan I. Ovchinnikov f6d43e003a pt3.12 modelled 2022-10-24 22:35:24 +03:00
Ivan I. Ovchinnikov a5eddcc776 pt3.1-7 software project creation, branching for hardware and simulation settings 2022-10-19 15:03:52 +03:00
Ivan I. Ovchinnikov 01f41dbf51 pt2 sopcinfo compile changed 2022-10-19 13:31:51 +03:00
54 changed files with 34812 additions and 124 deletions
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15
.gitignore vendored
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@ -9,6 +9,20 @@
/simulation /simulation
/.qsys* /.qsys*
# /atom_netlists # /atom_netlists
greybox_tmp/
.qsys_edit/
synthesis/
*output_files/
simulation/
obj/
drivers/
HAL/
Part_test/
.metadata/
RemoteSystemsTempFiles/
aldec/
cadence/
synopsys/
/testbenches/*.bak /testbenches/*.bak
@ -17,3 +31,4 @@
/build/* /build/*
!/build/*.pdf !/build/*.pdf
!/build/tikz*.sty !/build/tikz*.sty

15
Top/.gitignore vendored
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@ -9,6 +9,20 @@
/simulation /simulation
/.qsys* /.qsys*
# /atom_netlists # /atom_netlists
/greybox_tmp/
/.qsys_edit/
/synthesis/
/*output_files/
/simulation/
/obj/
/drivers/
/HAL/
/Part_test/
/.metadata/
/RemoteSystemsTempFiles/
/aldec/
/cadence/
/synopsys/
/testbenches/*.bak /testbenches/*.bak
@ -17,3 +31,4 @@
/build/* /build/*
!/build/*.pdf !/build/*.pdf
!/build/tikz*.sty !/build/tikz*.sty

18
Top/Semafor_hw.tcl
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@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 18.1 # TCL File Generated by Component Editor 18.1
# Wed Oct 19 14:12:17 MSK 2022 # Mon Oct 24 17:47:36 MSK 2022
# DO NOT MODIFY # DO NOT MODIFY
# #
# Semafor "Semafor" v1.0 # sem "Semafor" v1.0
# 2022.10.19.14:12:17 # 2022.10.24.17:47:36
# #
# #
@ -16,10 +16,10 @@ package require -exact qsys 16.1
# #
# module Semafor # module sem
# #
set_module_property DESCRIPTION "" set_module_property DESCRIPTION ""
set_module_property NAME Semafor set_module_property NAME sem
set_module_property VERSION 1.0 set_module_property VERSION 1.0
set_module_property INTERNAL false set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true set_module_property OPAQUE_ADDRESS_MAP true
@ -43,6 +43,13 @@ set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv TOP_LEVEL_FILE add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv TOP_LEVEL_FILE
add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL dec
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv
add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
# #
# parameters # parameters
@ -52,6 +59,7 @@ set_parameter_property m DEFAULT_VALUE 8
set_parameter_property m DISPLAY_NAME m set_parameter_property m DISPLAY_NAME m
set_parameter_property m TYPE INTEGER set_parameter_property m TYPE INTEGER
set_parameter_property m UNITS None set_parameter_property m UNITS None
set_parameter_property m ALLOWED_RANGES -2147483648:2147483647
set_parameter_property m HDL_PARAMETER true set_parameter_property m HDL_PARAMETER true

189
Top/Semafor_hw.tcl~ Normal file
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@ -0,0 +1,189 @@
# TCL File Generated by Component Editor 18.1
# Mon Oct 24 14:36:52 MSK 2022
# DO NOT MODIFY
#
# sem "Semafor" v1.0
# 2022.10.24.14:36:52
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module sem
#
set_module_property DESCRIPTION ""
set_module_property NAME sem
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "User Logic"
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME Semafor
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL dec
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv TOP_LEVEL_FILE
add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL dec
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv
add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
#
# parameters
#
add_parameter m INTEGER 8
set_parameter_property m DEFAULT_VALUE 8
set_parameter_property m DISPLAY_NAME m
set_parameter_property m TYPE INTEGER
set_parameter_property m UNITS None
set_parameter_property m ALLOWED_RANGES -2147483648:2147483647
set_parameter_property m HDL_PARAMETER true
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point ctl_slave
#
add_interface ctl_slave avalon end
set_interface_property ctl_slave addressUnits WORDS
set_interface_property ctl_slave associatedClock clock
set_interface_property ctl_slave associatedReset reset_n
set_interface_property ctl_slave bitsPerSymbol 8
set_interface_property ctl_slave burstOnBurstBoundariesOnly false
set_interface_property ctl_slave burstcountUnits WORDS
set_interface_property ctl_slave explicitAddressSpan 0
set_interface_property ctl_slave holdTime 0
set_interface_property ctl_slave linewrapBursts false
set_interface_property ctl_slave maximumPendingReadTransactions 0
set_interface_property ctl_slave maximumPendingWriteTransactions 0
set_interface_property ctl_slave readLatency 0
set_interface_property ctl_slave readWaitStates 0
set_interface_property ctl_slave readWaitTime 0
set_interface_property ctl_slave setupTime 0
set_interface_property ctl_slave timingUnits Cycles
set_interface_property ctl_slave writeWaitTime 0
set_interface_property ctl_slave ENABLED true
set_interface_property ctl_slave EXPORT_OF ""
set_interface_property ctl_slave PORT_NAME_MAP ""
set_interface_property ctl_slave CMSIS_SVD_VARIABLES ""
set_interface_property ctl_slave SVD_ADDRESS_GROUP ""
add_interface_port ctl_slave ctl_wr write Input 1
add_interface_port ctl_slave ctl_rd read Input 1
add_interface_port ctl_slave ctl_addr address Input 1
add_interface_port ctl_slave ctl_wrdata writedata Input 32
add_interface_port ctl_slave ctl_rddata readdata Output 32
set_interface_assignment ctl_slave embeddedsw.configuration.isFlash 0
set_interface_assignment ctl_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment ctl_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment ctl_slave embeddedsw.configuration.isPrintableDevice 0
#
# connection point reset_n
#
add_interface reset_n reset end
set_interface_property reset_n associatedClock clock
set_interface_property reset_n synchronousEdges DEASSERT
set_interface_property reset_n ENABLED true
set_interface_property reset_n EXPORT_OF ""
set_interface_property reset_n PORT_NAME_MAP ""
set_interface_property reset_n CMSIS_SVD_VARIABLES ""
set_interface_property reset_n SVD_ADDRESS_GROUP ""
add_interface_port reset_n clrn reset_n Input 1
#
# connection point ram_slave
#
add_interface ram_slave avalon end
set_interface_property ram_slave addressUnits WORDS
set_interface_property ram_slave associatedClock clock
set_interface_property ram_slave associatedReset reset_n
set_interface_property ram_slave bitsPerSymbol 8
set_interface_property ram_slave burstOnBurstBoundariesOnly false
set_interface_property ram_slave burstcountUnits WORDS
set_interface_property ram_slave explicitAddressSpan 0
set_interface_property ram_slave holdTime 0
set_interface_property ram_slave linewrapBursts false
set_interface_property ram_slave maximumPendingReadTransactions 0
set_interface_property ram_slave maximumPendingWriteTransactions 0
set_interface_property ram_slave readLatency 0
set_interface_property ram_slave readWaitTime 1
set_interface_property ram_slave setupTime 0
set_interface_property ram_slave timingUnits Cycles
set_interface_property ram_slave writeWaitTime 0
set_interface_property ram_slave ENABLED true
set_interface_property ram_slave EXPORT_OF ""
set_interface_property ram_slave PORT_NAME_MAP ""
set_interface_property ram_slave CMSIS_SVD_VARIABLES ""
set_interface_property ram_slave SVD_ADDRESS_GROUP ""
add_interface_port ram_slave ram_wr write Input 1
add_interface_port ram_slave ram_addr address Input 2
add_interface_port ram_slave ram_wrdata writedata Input 32
set_interface_assignment ram_slave embeddedsw.configuration.isFlash 0
set_interface_assignment ram_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment ram_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment ram_slave embeddedsw.configuration.isPrintableDevice 0
#
# connection point sem
#
add_interface sem conduit end
set_interface_property sem associatedClock ""
set_interface_property sem associatedReset reset_n
set_interface_property sem ENABLED true
set_interface_property sem EXPORT_OF ""
set_interface_property sem PORT_NAME_MAP ""
set_interface_property sem CMSIS_SVD_VARIABLES ""
set_interface_property sem SVD_ADDRESS_GROUP ""
add_interface_port sem train train Input 1
add_interface_port sem red red Output 1
add_interface_port sem yellow yellow Output 1
add_interface_port sem green green Output 1

12
Top/niosII.qsys
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@ -73,6 +73,14 @@
type = "String"; type = "String";
} }
} }
element niosII
{
datum _originalDeviceFamily
{
value = "Cyclone IV E";
type = "String";
}
}
element sem element sem
{ {
datum _sortIndex datum _sortIndex
@ -163,7 +171,7 @@
<parameter name="dataAddrWidth" value="18" /> <parameter name="dataAddrWidth" value="18" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" /> <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" /> <parameter name="dataMasterHighPerformanceMapParam" value="" />
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='Semafor.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='Semafor.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter> <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" /> <parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" /> <parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" /> <parameter name="data_master_paddr_base" value="0" />
@ -372,7 +380,7 @@
<parameter name="useShallowMemBlocks" value="false" /> <parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" /> <parameter name="writable" value="true" />
</module> </module>
<module name="sem" kind="Semafor" version="1.0" enabled="1"> <module name="sem" kind="sem" version="1.0" enabled="1">
<parameter name="m" value="8" /> <parameter name="m" value="8" />
</module> </module>
<module <module

10
Top/niosII.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS"> <EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) --> <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2022.10.19.14:20:53 --> <!-- 2022.10.24.18:25:23 -->
<!-- A collection of modules and connections --> <!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID"> <parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type> <type>java.lang.Integer</type>
<value>1666174853</value> <value>1666621523</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -2034,7 +2034,7 @@ the requested settings for a module instance. -->
</parameter> </parameter>
<parameter name="dataSlaveMapParam"> <parameter name="dataSlaveMapParam">
<type>java.lang.String</type> <type>java.lang.String</type>
<value><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='Semafor.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='Semafor.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></value> <value><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -5652,7 +5652,7 @@ parameters are a RESULT of the module parameters. -->
</port> </port>
</interface> </interface>
</module> </module>
<module name="sem" kind="Semafor" version="1.0" path="sem"> <module name="sem" kind="sem" version="1.0" path="sem">
<!-- Describes a single module. Module parameters are <!-- Describes a single module. Module parameters are
the requested settings for a module instance. --> the requested settings for a module instance. -->
<parameter name="m"> <parameter name="m">
@ -8346,7 +8346,7 @@ parameters are a RESULT of the module parameters. -->
</plugin> </plugin>
<plugin> <plugin>
<instanceCount>1</instanceCount> <instanceCount>1</instanceCount>
<name>Semafor</name> <name>sem</name>
<type>com.altera.entityinterfaces.IElementClass</type> <type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype> <subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Semafor</displayName> <displayName>Semafor</displayName>

10
Top/niosII/niosII.html
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@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table> </table>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">2022.10.19.14:20:53</td> <td class="l">2022.10.24.17:48:01</td>
<td class="r">Datasheet</td> <td class="r">Datasheet</td>
</tr> </tr>
</table> </table>
@ -101,7 +101,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</a> altera_avalon_onchip_memory2 18.1 </a> altera_avalon_onchip_memory2 18.1
<br/>&#160;&#160; <br/>&#160;&#160;
<a href="#module_sem"><b>sem</b> <a href="#module_sem"><b>sem</b>
</a> Semafor 1.0 </a> sem 1.0
<br/>&#160;&#160; <br/>&#160;&#160;
<a href="#module_sys_clk_timer"><b>sys_clk_timer</b> <a href="#module_sys_clk_timer"><b>sys_clk_timer</b>
</a> altera_avalon_timer 18.1</span> </a> altera_avalon_timer 18.1</span>
@ -1107,7 +1107,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">dataSlaveMapParam</td> <td class="parametername">dataSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ram_slave' start='0x21020' end='0x21030' type='Semafor.ram_slave' /&gt;&lt;slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='Semafor.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td> <td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /&gt;&lt;slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">tightlyCoupledDataMaster0MapParam</td> <td class="parametername">tightlyCoupledDataMaster0MapParam</td>
@ -1766,7 +1766,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<a name="module_sem"> </a> <a name="module_sem"> </a>
<div> <div>
<hr/> <hr/>
<h2>sem</h2>Semafor v1.0 <h2>sem</h2>sem v1.0
<br/> <br/>
<div class="greydiv"> <div class="greydiv">
<table class="connectionboxes"> <table class="connectionboxes">
@ -2039,7 +2039,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">generation took 0,01 seconds</td> <td class="l">generation took 0,01 seconds</td>
<td class="r">rendering took 0,11 seconds</td> <td class="r">rendering took 0,04 seconds</td>
</tr> </tr>
</table> </table>
</body> </body>

190
Top/niosII/niosII.xml
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12
Top/niosII/synthesis/niosII.debuginfo
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@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="niosII" kind="system" version="18.1" fabric="QSYS"> <EnsembleReport name="niosII" kind="system" version="18.1" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) --> <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2022.10.19.14:21:25 --> <!-- 2022.10.24.17:48:33 -->
<!-- A collection of modules and connections --> <!-- A collection of modules and connections -->
<parameter name="clockCrossingAdapter"> <parameter name="clockCrossingAdapter">
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type> <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@ -53,7 +53,7 @@
</parameter> </parameter>
<parameter name="generationId"> <parameter name="generationId">
<type>int</type> <type>int</type>
<value>1666174853</value> <value>1666619281</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>
@ -2110,7 +2110,7 @@ the requested settings for a module instance. -->
</parameter> </parameter>
<parameter name="dataSlaveMapParam"> <parameter name="dataSlaveMapParam">
<type>java.lang.String</type> <type>java.lang.String</type>
<value><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='Semafor.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='Semafor.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></value> <value><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -5673,7 +5673,7 @@ parameters are a RESULT of the module parameters. -->
</port> </port>
</interface> </interface>
</module> </module>
<module name="sem" kind="Semafor" version="1.0" path="sem"> <module name="sem" kind="sem" version="1.0" path="sem">
<!-- Describes a single module. Module parameters are <!-- Describes a single module. Module parameters are
the requested settings for a module instance. --> the requested settings for a module instance. -->
<parameter name="m"> <parameter name="m">
@ -12830,7 +12830,7 @@ parameters are a RESULT of the module parameters. -->
</plugin> </plugin>
<plugin> <plugin>
<instanceCount>1</instanceCount> <instanceCount>1</instanceCount>
<name>Semafor</name> <name>sem</name>
<type>com.altera.entityinterfaces.IElementClass</type> <type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype> <subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Semafor</displayName> <displayName>Semafor</displayName>
@ -12925,5 +12925,5 @@ parameters are a RESULT of the module parameters. -->
<version>18.1</version> <version>18.1</version>
</plugin> </plugin>
<reportVersion>18.1 625</reportVersion> <reportVersion>18.1 625</reportVersion>
<uniqueIdentifier>7831C1D0809000000183EFC2B97A</uniqueIdentifier> <uniqueIdentifier>7A31C1D08890000001840A4024CB</uniqueIdentifier>
</EnsembleReport> </EnsembleReport>

8
Top/niosII/synthesis/niosII.qip
View File

@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1" set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1"
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys" set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"] set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"]
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1666174853" set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1666619281"
set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"] set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"]
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"] set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"]
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"] set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"]
@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY2NjE3NDg1Mw==::QXV0byBHRU5FUkFUSU9OX0lE" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY2NjYxOTI4MQ==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U=" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U="
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@ -859,7 +859,7 @@ set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0=" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdTZW1hZm9yLnJhbV9zbGF2ZScgLz48c2xhdmUgbmFtZT0nc2VtLmN0bF9zbGF2ZScgc3RhcnQ9JzB4MjEwMzAnIGVuZD0nMHgyMTAzOCcgdHlwZT0nU2VtYWZvci5jdGxfc2xhdmUnIC8+PHNsYXZlIG5hbWU9J2p0YWdfdWFydC5hdmFsb25fanRhZ19zbGF2ZScgc3RhcnQ9JzB4MjEwMzgnIGVuZD0nMHgyMTA0MCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9qdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIC8+PC9hZGRyZXNzLW1hcD4=::ZGF0YVNsYXZlTWFwUGFyYW0=" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTAzMCcgZW5kPScweDIxMDM4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDM4JyBlbmQ9JzB4MjEwNDAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k=" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ==" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ=="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="
@ -1042,7 +1042,7 @@ set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPON
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0=" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdTZW1hZm9yLnJhbV9zbGF2ZScgLz48c2xhdmUgbmFtZT0nc2VtLmN0bF9zbGF2ZScgc3RhcnQ9JzB4MjEwMzAnIGVuZD0nMHgyMTAzOCcgdHlwZT0nU2VtYWZvci5jdGxfc2xhdmUnIC8+PHNsYXZlIG5hbWU9J2p0YWdfdWFydC5hdmFsb25fanRhZ19zbGF2ZScgc3RhcnQ9JzB4MjEwMzgnIGVuZD0nMHgyMTA0MCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9qdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIC8+PC9hZGRyZXNzLW1hcD4=::ZGF0YVNsYXZlTWFwUGFyYW0=" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTAzMCcgZW5kPScweDIxMDM4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDM4JyBlbmQ9JzB4MjEwNDAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k=" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ==" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ=="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="

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# (C) 2001-2022 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ----------------------------------------
# Auto-generated simulation script msim_setup.tcl
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# niosII_tb
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level script that compiles Altera simulation libraries and
# the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "mentor.do", and modify the text as directed.
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# set QSYS_SIMDIR <script generation output directory>
# #
# # Source the generated IP simulation script.
# source $QSYS_SIMDIR/mentor/msim_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
# #
# # Call command to compile the Quartus EDA simulation library.
# dev_com
# #
# # Call command to compile the Quartus-generated IP simulation files.
# com
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
# vlog <compilation options> <design and testbench files>
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
# set TOP_LEVEL_NAME <simulation top>
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
# elab
# #
# # Run the simulation.
# run -a
# #
# # Report success to the shell.
# exit -code 0
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If niosII_tb is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 win32 2022.10.24.18:26:02
# ----------------------------------------
# Initialize variables
if ![info exists SYSTEM_INSTANCE_NAME] {
set SYSTEM_INSTANCE_NAME ""
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
}
if ![info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME "niosII_tb"
}
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "C:/software/intelfpga_lite/18.1/quartus/"
}
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
set USER_DEFINED_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
set USER_DEFINED_ELAB_OPTIONS ""
}
# ----------------------------------------
# Initialize simulation properties - DO NOT MODIFY!
set ELAB_OPTIONS ""
set SIM_OPTIONS ""
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
} else {
}
# ----------------------------------------
# Copy ROM/RAM files to simulation directory
alias file_copy {
echo "\[exec\] file_copy"
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
}
# ----------------------------------------
# Create compilation libraries
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
ensure_lib ./libraries/
ensure_lib ./libraries/work/
vmap work ./libraries/work/
vmap work_lib ./libraries/work/
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
ensure_lib ./libraries/altera_ver/
vmap altera_ver ./libraries/altera_ver/
ensure_lib ./libraries/lpm_ver/
vmap lpm_ver ./libraries/lpm_ver/
ensure_lib ./libraries/sgate_ver/
vmap sgate_ver ./libraries/sgate_ver/
ensure_lib ./libraries/altera_mf_ver/
vmap altera_mf_ver ./libraries/altera_mf_ver/
ensure_lib ./libraries/altera_lnsim_ver/
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
ensure_lib ./libraries/cycloneive_ver/
vmap cycloneive_ver ./libraries/cycloneive_ver/
}
ensure_lib ./libraries/altera_common_sv_packages/
vmap altera_common_sv_packages ./libraries/altera_common_sv_packages/
ensure_lib ./libraries/error_adapter_0/
vmap error_adapter_0 ./libraries/error_adapter_0/
ensure_lib ./libraries/avalon_st_adapter/
vmap avalon_st_adapter ./libraries/avalon_st_adapter/
ensure_lib ./libraries/rsp_mux_001/
vmap rsp_mux_001 ./libraries/rsp_mux_001/
ensure_lib ./libraries/rsp_mux/
vmap rsp_mux ./libraries/rsp_mux/
ensure_lib ./libraries/rsp_demux/
vmap rsp_demux ./libraries/rsp_demux/
ensure_lib ./libraries/cmd_mux_002/
vmap cmd_mux_002 ./libraries/cmd_mux_002/
ensure_lib ./libraries/cmd_mux/
vmap cmd_mux ./libraries/cmd_mux/
ensure_lib ./libraries/cmd_demux_001/
vmap cmd_demux_001 ./libraries/cmd_demux_001/
ensure_lib ./libraries/cmd_demux/
vmap cmd_demux ./libraries/cmd_demux/
ensure_lib ./libraries/router_008/
vmap router_008 ./libraries/router_008/
ensure_lib ./libraries/router_004/
vmap router_004 ./libraries/router_004/
ensure_lib ./libraries/router_002/
vmap router_002 ./libraries/router_002/
ensure_lib ./libraries/router_001/
vmap router_001 ./libraries/router_001/
ensure_lib ./libraries/router/
vmap router ./libraries/router/
ensure_lib ./libraries/jtag_uart_avalon_jtag_slave_agent_rsp_fifo/
vmap jtag_uart_avalon_jtag_slave_agent_rsp_fifo ./libraries/jtag_uart_avalon_jtag_slave_agent_rsp_fifo/
ensure_lib ./libraries/jtag_uart_avalon_jtag_slave_agent/
vmap jtag_uart_avalon_jtag_slave_agent ./libraries/jtag_uart_avalon_jtag_slave_agent/
ensure_lib ./libraries/cpu_data_master_agent/
vmap cpu_data_master_agent ./libraries/cpu_data_master_agent/
ensure_lib ./libraries/jtag_uart_avalon_jtag_slave_translator/
vmap jtag_uart_avalon_jtag_slave_translator ./libraries/jtag_uart_avalon_jtag_slave_translator/
ensure_lib ./libraries/cpu_data_master_translator/
vmap cpu_data_master_translator ./libraries/cpu_data_master_translator/
ensure_lib ./libraries/cpu/
vmap cpu ./libraries/cpu/
ensure_lib ./libraries/rst_controller/
vmap rst_controller ./libraries/rst_controller/
ensure_lib ./libraries/irq_mapper/
vmap irq_mapper ./libraries/irq_mapper/
ensure_lib ./libraries/mm_interconnect_0/
vmap mm_interconnect_0 ./libraries/mm_interconnect_0/
ensure_lib ./libraries/sys_clk_timer/
vmap sys_clk_timer ./libraries/sys_clk_timer/
ensure_lib ./libraries/sem/
vmap sem ./libraries/sem/
ensure_lib ./libraries/mem/
vmap mem ./libraries/mem/
ensure_lib ./libraries/jtag_uart/
vmap jtag_uart ./libraries/jtag_uart/
ensure_lib ./libraries/niosII_inst_reset_bfm/
vmap niosII_inst_reset_bfm ./libraries/niosII_inst_reset_bfm/
ensure_lib ./libraries/niosII_inst_clk_bfm/
vmap niosII_inst_clk_bfm ./libraries/niosII_inst_clk_bfm/
ensure_lib ./libraries/niosII_inst/
vmap niosII_inst ./libraries/niosII_inst/
# ----------------------------------------
# Compile device library files
alias dev_com {
echo "\[exec\] dev_com"
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v" -work cycloneive_ver
}
}
# ----------------------------------------
# Compile the design files in correct order
alias com {
echo "\[exec\] com"
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/verbosity_pkg.sv" -work altera_common_sv_packages
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" -L altera_common_sv_packages -work error_adapter_0
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v" -work avalon_st_adapter
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv" -L altera_common_sv_packages -work rsp_mux_001
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -L altera_common_sv_packages -work rsp_mux_001
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv" -L altera_common_sv_packages -work rsp_mux
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -L altera_common_sv_packages -work rsp_mux
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv" -L altera_common_sv_packages -work rsp_demux
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv" -L altera_common_sv_packages -work cmd_mux_002
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -L altera_common_sv_packages -work cmd_mux_002
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv" -L altera_common_sv_packages -work cmd_mux
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -L altera_common_sv_packages -work cmd_mux
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv" -L altera_common_sv_packages -work cmd_demux_001
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv" -L altera_common_sv_packages -work cmd_demux
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv" -L altera_common_sv_packages -work router_008
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv" -L altera_common_sv_packages -work router_004
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv" -L altera_common_sv_packages -work router_002
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv" -L altera_common_sv_packages -work router_001
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv" -L altera_common_sv_packages -work router
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v" -work jtag_uart_avalon_jtag_slave_agent_rsp_fifo
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv" -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_agent
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv" -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_agent
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv" -L altera_common_sv_packages -work cpu_data_master_agent
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv" -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_translator
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv" -L altera_common_sv_packages -work cpu_data_master_translator
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v" -work rst_controller
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_synchronizer.v" -work rst_controller
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_irq_mapper.sv" -L altera_common_sv_packages -work irq_mapper
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v" -work mm_interconnect_0
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v" -work sys_clk_timer
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/dec.sv" -L altera_common_sv_packages -work sem
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/periodram.v" -work sem
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.v" -work mem
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_jtag_uart.v" -work jtag_uart
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu.v" -work cpu
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv" -L altera_common_sv_packages -work niosII_inst_reset_bfm
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv" -L altera_common_sv_packages -work niosII_inst_clk_bfm
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII.v" -work niosII_inst
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/niosII_tb.v"
}
# ----------------------------------------
# Elaborate top level design
alias elab {
echo "\[exec\] elab"
eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_common_sv_packages -L error_adapter_0 -L avalon_st_adapter -L rsp_mux_001 -L rsp_mux -L rsp_demux -L cmd_mux_002 -L cmd_mux -L cmd_demux_001 -L cmd_demux -L router_008 -L router_004 -L router_002 -L router_001 -L router -L jtag_uart_avalon_jtag_slave_agent_rsp_fifo -L jtag_uart_avalon_jtag_slave_agent -L cpu_data_master_agent -L jtag_uart_avalon_jtag_slave_translator -L cpu_data_master_translator -L cpu -L rst_controller -L irq_mapper -L mm_interconnect_0 -L sys_clk_timer -L sem -L mem -L jtag_uart -L niosII_inst_reset_bfm -L niosII_inst_clk_bfm -L niosII_inst -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver $TOP_LEVEL_NAME
}
# ----------------------------------------
# Elaborate the top level design with novopt option
alias elab_debug {
echo "\[exec\] elab_debug"
eval vsim -novopt -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_common_sv_packages -L error_adapter_0 -L avalon_st_adapter -L rsp_mux_001 -L rsp_mux -L rsp_demux -L cmd_mux_002 -L cmd_mux -L cmd_demux_001 -L cmd_demux -L router_008 -L router_004 -L router_002 -L router_001 -L router -L jtag_uart_avalon_jtag_slave_agent_rsp_fifo -L jtag_uart_avalon_jtag_slave_agent -L cpu_data_master_agent -L jtag_uart_avalon_jtag_slave_translator -L cpu_data_master_translator -L cpu -L rst_controller -L irq_mapper -L mm_interconnect_0 -L sys_clk_timer -L sem -L mem -L jtag_uart -L niosII_inst_reset_bfm -L niosII_inst_clk_bfm -L niosII_inst -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver $TOP_LEVEL_NAME
}
# ----------------------------------------
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"
# ----------------------------------------
# Compile all the design files and elaborate the top level design with -novopt
alias ld_debug "
dev_com
com
elab_debug
"
# ----------------------------------------
# Print out user commmand line aliases
alias h {
echo "List Of Command Line Aliases"
echo
echo "file_copy -- Copy ROM/RAM files to simulation directory"
echo
echo "dev_com -- Compile device library files"
echo
echo "com -- Compile the design files in correct order"
echo
echo "elab -- Elaborate top level design"
echo
echo "elab_debug -- Elaborate the top level design with novopt option"
echo
echo "ld -- Compile all the design files and elaborate the top level design"
echo
echo "ld_debug -- Compile all the design files and elaborate the top level design with -novopt"
echo
echo
echo
echo "List Of Variables"
echo
echo "TOP_LEVEL_NAME -- Top level module name."
echo " For most designs, this should be overridden"
echo " to enable the elab/elab_debug aliases."
echo
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
echo
echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
echo
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
echo
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
echo
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
}
file_copy
h

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<library>
<!-- Include the system-under-test, and project-local components. -->
<path path="../../*" >
<tag2 key="COMPONENT_IN_PROJECT" value="true" />
</path>
<path path="../../ip/**/*" >
<tag2 key="COMPONENT_IN_PROJECT" value="true" />
</path>
<path path="../../*/*" >
<tag2 key="COMPONENT_IN_PROJECT" value="true" />
</path>
</library>

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<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="" />
<parameter name="bonusData"><![CDATA[bonusData
{
element niosII_inst
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element niosII_inst_clk_bfm
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element niosII_inst_reset_bfm
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="EP4CE115F29C7" />
<parameter name="deviceFamily" value="Cyclone IV E" />
<parameter name="deviceSpeedGrade" value="7" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="semafor.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="niosII" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="true" />
<instanceScript></instanceScript>
<module name="niosII_inst" kind="niosII" version="1.0" enabled="1">
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
<parameter name="AUTO_DEVICE" value="EP4CE115F29C7" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
<parameter name="AUTO_GENERATION_ID" value="0" />
<parameter name="AUTO_UNIQUE_ID" value="niosII" />
</module>
<module
name="niosII_inst_clk_bfm"
kind="altera_avalon_clock_source"
version="18.1"
enabled="1">
<parameter name="CLOCK_RATE" value="50000000" />
<parameter name="CLOCK_UNIT" value="1" />
</module>
<module
name="niosII_inst_reset_bfm"
kind="altera_avalon_reset_source"
version="18.1"
enabled="1">
<parameter name="ASSERT_HIGH_RESET" value="0" />
<parameter name="INITIAL_RESET_CYCLES" value="50" />
</module>
<connection
kind="clock"
version="18.1"
start="niosII_inst_clk_bfm.clk"
end="niosII_inst.clk" />
<connection
kind="clock"
version="18.1"
start="niosII_inst_clk_bfm.clk"
end="niosII_inst_reset_bfm.clk" />
<connection
kind="reset"
version="18.1"
start="niosII_inst_reset_bfm.reset"
end="niosII_inst.reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>

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# (C) 2001-2022 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 18.1 625 win32 2022.10.24.18:26:02
# ----------------------------------------
# vcs - auto-generated simulation script
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# niosII_tb
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level shell script that compiles Altera simulation libraries
# and the Quartus-generated IP in your project, along with your design and
# testbench files, follow the guidelines below.
#
# 1) Copy the shell script text from the TOP-LEVEL TEMPLATE section
# below into a new file, e.g. named "vcs_sim.sh".
#
# 2) Copy the text from the DESIGN FILE LIST & OPTIONS TEMPLATE section into
# a separate file, e.g. named "filelist.f".
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # TOP_LEVEL_NAME is used in the Quartus-generated IP simulation script to
# # set the top-level simulation or testbench module/entity name.
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# # Source the Quartus-generated IP simulation script and do the following:
# # - Compile the Quartus EDA simulation library and IP simulation files.
# # - Specify TOP_LEVEL_NAME and QSYS_SIMDIR.
# # - Compile the design and top-level simulation module/entity using
# # information specified in "filelist.f".
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
# # - Run the simulation.
# #
# source <script generation output directory>/synopsys/vcs/vcs_setup.sh \
# TOP_LEVEL_NAME=<simulation top> \
# QSYS_SIMDIR=<script generation output directory> \
# USER_DEFINED_ELAB_OPTIONS="\"-f filelist.f\"" \
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# ----------------------------------------
# # DESIGN FILE LIST & OPTIONS TEMPLATE - BEGIN
# #
# # Compile all design files and testbench files, including the top level.
# # (These are all the files required for simulation other than the files
# # compiled by the Quartus-generated IP simulation script)
# #
# +systemverilogext+.sv
# <design and testbench files, compile-time options, elaboration options>
# #
# # DESIGN FILE LIST & OPTIONS TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If niosII_tb is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 win32 2022.10.24.18:26:02
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="niosII_tb"
QSYS_SIMDIR="./../../"
QUARTUS_INSTALL_DIR="C:/software/intelfpga_lite/18.1/quartus/"
SKIP_FILE_COPY=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `vcs -platform` != *"amd64"* ]]; then
:
else
:
fi
# ----------------------------------------
# copy RAM/ROM files to simulation directory
if [ $SKIP_FILE_COPY -eq 0 ]; then
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
fi
vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/verbosity_pkg.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_synchronizer.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_irq_mapper.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/dec.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/periodram.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_jtag_uart.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII.v \
$QSYS_SIMDIR/niosII_tb/simulation/niosII_tb.v \
-top $TOP_LEVEL_NAME
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
fi

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@ -0,0 +1,41 @@
WORK > DEFAULT
DEFAULT: ./libraries/work/
work: ./libraries/work/
altera_common_sv_packages: ./libraries/altera_common_sv_packages/
error_adapter_0: ./libraries/error_adapter_0/
avalon_st_adapter: ./libraries/avalon_st_adapter/
rsp_mux_001: ./libraries/rsp_mux_001/
rsp_mux: ./libraries/rsp_mux/
rsp_demux: ./libraries/rsp_demux/
cmd_mux_002: ./libraries/cmd_mux_002/
cmd_mux: ./libraries/cmd_mux/
cmd_demux_001: ./libraries/cmd_demux_001/
cmd_demux: ./libraries/cmd_demux/
router_008: ./libraries/router_008/
router_004: ./libraries/router_004/
router_002: ./libraries/router_002/
router_001: ./libraries/router_001/
router: ./libraries/router/
jtag_uart_avalon_jtag_slave_agent_rsp_fifo: ./libraries/jtag_uart_avalon_jtag_slave_agent_rsp_fifo/
jtag_uart_avalon_jtag_slave_agent: ./libraries/jtag_uart_avalon_jtag_slave_agent/
cpu_data_master_agent: ./libraries/cpu_data_master_agent/
jtag_uart_avalon_jtag_slave_translator: ./libraries/jtag_uart_avalon_jtag_slave_translator/
cpu_data_master_translator: ./libraries/cpu_data_master_translator/
cpu: ./libraries/cpu/
rst_controller: ./libraries/rst_controller/
irq_mapper: ./libraries/irq_mapper/
mm_interconnect_0: ./libraries/mm_interconnect_0/
sys_clk_timer: ./libraries/sys_clk_timer/
sem: ./libraries/sem/
mem: ./libraries/mem/
jtag_uart: ./libraries/jtag_uart/
niosII_inst_reset_bfm: ./libraries/niosII_inst_reset_bfm/
niosII_inst_clk_bfm: ./libraries/niosII_inst_clk_bfm/
niosII_inst: ./libraries/niosII_inst/
altera_ver: ./libraries/altera_ver/
lpm_ver: ./libraries/lpm_ver/
sgate_ver: ./libraries/sgate_ver/
altera_mf_ver: ./libraries/altera_mf_ver/
altera_lnsim_ver: ./libraries/altera_lnsim_ver/
cycloneive_ver: ./libraries/cycloneive_ver/

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# (C) 2001-2022 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 18.1 625 win32 2022.10.24.18:26:03
# ----------------------------------------
# vcsmx - auto-generated simulation script
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# niosII_tb
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level shell script that compiles Altera simulation libraries
# and the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
#
# You can also modify the simulation flow to suit your needs. Set the
# following variables to 1 to disable their corresponding processes:
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator. In this case, you must also copy the generated library
# # setup "synopsys_sim.setup" into the location from which you launch the
# # simulator, or incorporate into any existing library setup.
# #
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
# # simulation libraries and Quartus-generated IP simulation files, and copy
# # any ROM/RAM initialization files to the simulation directory.
# #
# # - If necessary, specify any compilation options:
# # USER_DEFINED_COMPILE_OPTIONS
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
# #
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
# SKIP_ELAB=1 \
# SKIP_SIM=1 \
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
# QSYS_SIMDIR=<script generation output directory>
# #
# # Compile all design files and testbench files, including the top level.
# # (These are all the files required for simulation other than the files
# # compiled by the IP script)
# #
# vlogan <compilation options> <design and testbench files>
# #
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
# # testbench module/entity name.
# #
# # Run the IP script again to elaborate and simulate the top level:
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
# #
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
# SKIP_FILE_COPY=1 \
# SKIP_DEV_COM=1 \
# SKIP_COM=1 \
# TOP_LEVEL_NAME="'-top <simulation top>'" \
# QSYS_SIMDIR=<script generation output directory> \
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If niosII_tb is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 win32 2022.10.24.18:26:03
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="niosII_tb"
QSYS_SIMDIR="./../../"
QUARTUS_INSTALL_DIR="C:/software/intelfpga_lite/18.1/quartus/"
SKIP_FILE_COPY=0
SKIP_DEV_COM=0
SKIP_COM=0
SKIP_ELAB=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `vcs -platform` != *"amd64"* ]]; then
:
else
:
fi
# ----------------------------------------
# create compilation libraries
mkdir -p ./libraries/work/
mkdir -p ./libraries/altera_common_sv_packages/
mkdir -p ./libraries/error_adapter_0/
mkdir -p ./libraries/avalon_st_adapter/
mkdir -p ./libraries/rsp_mux_001/
mkdir -p ./libraries/rsp_mux/
mkdir -p ./libraries/rsp_demux/
mkdir -p ./libraries/cmd_mux_002/
mkdir -p ./libraries/cmd_mux/
mkdir -p ./libraries/cmd_demux_001/
mkdir -p ./libraries/cmd_demux/
mkdir -p ./libraries/router_008/
mkdir -p ./libraries/router_004/
mkdir -p ./libraries/router_002/
mkdir -p ./libraries/router_001/
mkdir -p ./libraries/router/
mkdir -p ./libraries/jtag_uart_avalon_jtag_slave_agent_rsp_fifo/
mkdir -p ./libraries/jtag_uart_avalon_jtag_slave_agent/
mkdir -p ./libraries/cpu_data_master_agent/
mkdir -p ./libraries/jtag_uart_avalon_jtag_slave_translator/
mkdir -p ./libraries/cpu_data_master_translator/
mkdir -p ./libraries/cpu/
mkdir -p ./libraries/rst_controller/
mkdir -p ./libraries/irq_mapper/
mkdir -p ./libraries/mm_interconnect_0/
mkdir -p ./libraries/sys_clk_timer/
mkdir -p ./libraries/sem/
mkdir -p ./libraries/mem/
mkdir -p ./libraries/jtag_uart/
mkdir -p ./libraries/niosII_inst_reset_bfm/
mkdir -p ./libraries/niosII_inst_clk_bfm/
mkdir -p ./libraries/niosII_inst/
mkdir -p ./libraries/altera_ver/
mkdir -p ./libraries/lpm_ver/
mkdir -p ./libraries/sgate_ver/
mkdir -p ./libraries/altera_mf_ver/
mkdir -p ./libraries/altera_lnsim_ver/
mkdir -p ./libraries/cycloneive_ver/
# ----------------------------------------
# copy RAM/ROM files to simulation directory
if [ $SKIP_FILE_COPY -eq 0 ]; then
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
fi
# ----------------------------------------
# compile device library files
if [ $SKIP_DEV_COM -eq 0 ]; then
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v" -work cycloneive_ver
fi
# ----------------------------------------
# compile design files in correct order
if [ $SKIP_COM -eq 0 ]; then
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/verbosity_pkg.sv" -work altera_common_sv_packages
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" -work error_adapter_0
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v" -work avalon_st_adapter
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv" -work rsp_mux_001
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -work rsp_mux_001
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv" -work rsp_mux
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -work rsp_mux
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv" -work rsp_demux
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv" -work cmd_mux_002
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -work cmd_mux_002
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv" -work cmd_mux
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -work cmd_mux
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv" -work cmd_demux_001
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv" -work cmd_demux
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv" -work router_008
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv" -work router_004
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv" -work router_002
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv" -work router_001
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv" -work router
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v" -work jtag_uart_avalon_jtag_slave_agent_rsp_fifo
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv" -work jtag_uart_avalon_jtag_slave_agent
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv" -work jtag_uart_avalon_jtag_slave_agent
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv" -work cpu_data_master_agent
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv" -work jtag_uart_avalon_jtag_slave_translator
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv" -work cpu_data_master_translator
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v" -work rst_controller
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_synchronizer.v" -work rst_controller
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_irq_mapper.sv" -work irq_mapper
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v" -work mm_interconnect_0
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v" -work sys_clk_timer
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/dec.sv" -work sem
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/periodram.v" -work sem
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.v" -work mem
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_jtag_uart.v" -work jtag_uart
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu.v" -work cpu
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv" -work niosII_inst_reset_bfm
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv" -work niosII_inst_clk_bfm
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII.v" -work niosII_inst
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/niosII_tb.v"
fi
# ----------------------------------------
# elaborate top level design
if [ $SKIP_ELAB -eq 0 ]; then
vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
fi
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
fi

151
Top/niosII_tb.csv Normal file
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@ -0,0 +1,151 @@
# system info niosII_tb on 2022.10.24.18:26:01
system_info:
name,value
DEVICE,EP4CE115F29C7
DEVICE_FAMILY,Cyclone IV E
GENERATION_ID,1666621532
#
#
# Files generated for niosII_tb on 2022.10.24.18:26:01
files:
filepath,kind,attributes,module,is_top
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
niosII/testbench/niosII_tb/simulation/submodules/niosII.v,VERILOG,,niosII,false
niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_clock_source,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv,SYSTEM_VERILOG,,altera_avalon_clock_source,false
niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_reset_source,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv,SYSTEM_VERILOG,,altera_avalon_reset_source,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v,VERILOG,,niosII_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false
niosII/testbench/niosII_tb/simulation/submodules/dec.sv,SYSTEM_VERILOG,,dec,false
niosII/testbench/niosII_tb/simulation/submodules/periodram.v,VERILOG,,dec,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v,VERILOG,,niosII_sys_clk_timer,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v,VERILOG,,niosII_mm_interconnect_0,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VERILOG,,niosII_irq_mapper,false
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v,VERILOG,,altera_avalon_sc_fifo,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_001,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_002,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_004,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_008,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux_001,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_demux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v,VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
niosII_tb.niosII_inst,niosII
niosII_tb.niosII_inst.cpu,niosII_cpu
niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu
niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart
niosII_tb.niosII_inst.mem,niosII_mem
niosII_tb.niosII_inst.sem,dec
niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer
niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0
niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_translator,altera_merlin_master_translator
niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_translator,altera_merlin_master_translator
niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_agent,altera_merlin_master_agent
niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_agent,altera_merlin_master_agent
niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.router,niosII_mm_interconnect_0_router
niosII_tb.niosII_inst.mm_interconnect_0.router_001,niosII_mm_interconnect_0_router_001
niosII_tb.niosII_inst.mm_interconnect_0.router_002,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_003,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_005,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_006,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_007,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_004,niosII_mm_interconnect_0_router_004
niosII_tb.niosII_inst.mm_interconnect_0.router_008,niosII_mm_interconnect_0_router_008
niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux,niosII_mm_interconnect_0_cmd_demux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux_001,niosII_mm_interconnect_0_cmd_demux_001
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_002,niosII_mm_interconnect_0_cmd_demux_001
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_001,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_003,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_004,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_005,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_006,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_002,niosII_mm_interconnect_0_cmd_mux_002
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_001,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_003,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_004,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_005,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_006,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux,niosII_mm_interconnect_0_rsp_mux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux_001,niosII_mm_interconnect_0_rsp_mux_001
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.irq_mapper,niosII_irq_mapper
niosII_tb.niosII_inst.rst_controller,altera_reset_controller
niosII_tb.niosII_inst_clk_bfm,altera_avalon_clock_source
niosII_tb.niosII_inst_reset_bfm,altera_avalon_reset_source
1 # system info niosII_tb on 2022.10.24.18:26:01
2 system_info:
3 name,value
4 DEVICE,EP4CE115F29C7
5 DEVICE_FAMILY,Cyclone IV E
6 GENERATION_ID,1666621532
7 #
8 #
9 # Files generated for niosII_tb on 2022.10.24.18:26:01
10 files:
11 filepath,kind,attributes,module,is_top
12 niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
13 niosII/testbench/niosII_tb/simulation/submodules/niosII.v,VERILOG,,niosII,false
14 niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_clock_source,false
15 niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv,SYSTEM_VERILOG,,altera_avalon_clock_source,false
16 niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_reset_source,false
17 niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv,SYSTEM_VERILOG,,altera_avalon_reset_source,false
18 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v,VERILOG,,niosII_cpu,false
19 niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false
20 niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false
21 niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false
22 niosII/testbench/niosII_tb/simulation/submodules/dec.sv,SYSTEM_VERILOG,,dec,false
23 niosII/testbench/niosII_tb/simulation/submodules/periodram.v,VERILOG,,dec,false
24 niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v,VERILOG,,niosII_sys_clk_timer,false
25 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v,VERILOG,,niosII_mm_interconnect_0,false
26 niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VERILOG,,niosII_irq_mapper,false
27 niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
28 niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
29 niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
30 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
31 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
32 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false
33 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
34 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
35 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
36 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false
37 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
38 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
39 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false
40 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false
41 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
42 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false
43 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false
44 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false
45 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false
46 niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
47 niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
48 niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false
49 niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
50 niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
51 niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v,VERILOG,,altera_avalon_sc_fifo,false
52 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router,false
53 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_001,false
54 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_002,false
55 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_004,false
56 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_008,false
57 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux,false
58 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux_001,false
59 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
60 niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
61 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
62 niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
63 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_demux,false
64 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
65 niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
66 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
67 niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
68 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v,VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter,false
69 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0,false
70 #
71 # Map from instance-path to kind of module
72 instances:
73 instancePath,module
74 niosII_tb.niosII_inst,niosII
75 niosII_tb.niosII_inst.cpu,niosII_cpu
76 niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu
77 niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart
78 niosII_tb.niosII_inst.mem,niosII_mem
79 niosII_tb.niosII_inst.sem,dec
80 niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer
81 niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0
82 niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_translator,altera_merlin_master_translator
83 niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_translator,altera_merlin_master_translator
84 niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_translator,altera_merlin_slave_translator
85 niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_translator,altera_merlin_slave_translator
86 niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_translator,altera_merlin_slave_translator
87 niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_translator,altera_merlin_slave_translator
88 niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_translator,altera_merlin_slave_translator
89 niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_translator,altera_merlin_slave_translator
90 niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_translator,altera_merlin_slave_translator
91 niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_agent,altera_merlin_master_agent
92 niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_agent,altera_merlin_master_agent
93 niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent,altera_merlin_slave_agent
94 niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent,altera_merlin_slave_agent
95 niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent,altera_merlin_slave_agent
96 niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent,altera_merlin_slave_agent
97 niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent,altera_merlin_slave_agent
98 niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent,altera_merlin_slave_agent
99 niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent,altera_merlin_slave_agent
100 niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent_rsp_fifo,altera_avalon_sc_fifo
101 niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent_rsp_fifo,altera_avalon_sc_fifo
102 niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent_rsp_fifo,altera_avalon_sc_fifo
103 niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent_rsp_fifo,altera_avalon_sc_fifo
104 niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent_rsp_fifo,altera_avalon_sc_fifo
105 niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent_rsp_fifo,altera_avalon_sc_fifo
106 niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent_rsp_fifo,altera_avalon_sc_fifo
107 niosII_tb.niosII_inst.mm_interconnect_0.router,niosII_mm_interconnect_0_router
108 niosII_tb.niosII_inst.mm_interconnect_0.router_001,niosII_mm_interconnect_0_router_001
109 niosII_tb.niosII_inst.mm_interconnect_0.router_002,niosII_mm_interconnect_0_router_002
110 niosII_tb.niosII_inst.mm_interconnect_0.router_003,niosII_mm_interconnect_0_router_002
111 niosII_tb.niosII_inst.mm_interconnect_0.router_005,niosII_mm_interconnect_0_router_002
112 niosII_tb.niosII_inst.mm_interconnect_0.router_006,niosII_mm_interconnect_0_router_002
113 niosII_tb.niosII_inst.mm_interconnect_0.router_007,niosII_mm_interconnect_0_router_002
114 niosII_tb.niosII_inst.mm_interconnect_0.router_004,niosII_mm_interconnect_0_router_004
115 niosII_tb.niosII_inst.mm_interconnect_0.router_008,niosII_mm_interconnect_0_router_008
116 niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux,niosII_mm_interconnect_0_cmd_demux
117 niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux_001,niosII_mm_interconnect_0_cmd_demux_001
118 niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_002,niosII_mm_interconnect_0_cmd_demux_001
119 niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux,niosII_mm_interconnect_0_cmd_mux
120 niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_001,niosII_mm_interconnect_0_cmd_mux
121 niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_003,niosII_mm_interconnect_0_cmd_mux
122 niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_004,niosII_mm_interconnect_0_cmd_mux
123 niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_005,niosII_mm_interconnect_0_cmd_mux
124 niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_006,niosII_mm_interconnect_0_cmd_mux
125 niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_002,niosII_mm_interconnect_0_cmd_mux_002
126 niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux,niosII_mm_interconnect_0_rsp_demux
127 niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_001,niosII_mm_interconnect_0_rsp_demux
128 niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_003,niosII_mm_interconnect_0_rsp_demux
129 niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_004,niosII_mm_interconnect_0_rsp_demux
130 niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_005,niosII_mm_interconnect_0_rsp_demux
131 niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_006,niosII_mm_interconnect_0_rsp_demux
132 niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux,niosII_mm_interconnect_0_rsp_mux
133 niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux_001,niosII_mm_interconnect_0_rsp_mux_001
134 niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter,niosII_mm_interconnect_0_avalon_st_adapter
135 niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
136 niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001,niosII_mm_interconnect_0_avalon_st_adapter
137 niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
138 niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002,niosII_mm_interconnect_0_avalon_st_adapter
139 niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
140 niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003,niosII_mm_interconnect_0_avalon_st_adapter
141 niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
142 niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004,niosII_mm_interconnect_0_avalon_st_adapter
143 niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
144 niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005,niosII_mm_interconnect_0_avalon_st_adapter
145 niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
146 niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006,niosII_mm_interconnect_0_avalon_st_adapter
147 niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
148 niosII_tb.niosII_inst.irq_mapper,niosII_irq_mapper
149 niosII_tb.niosII_inst.rst_controller,altera_reset_controller
150 niosII_tb.niosII_inst_clk_bfm,altera_avalon_clock_source
151 niosII_tb.niosII_inst_reset_bfm,altera_avalon_reset_source

236
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<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file
path="niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv"
type="SYSTEM_VERILOG"
library="altera_common_sv_packages"
systemVerilogPackageName="avalon_vip_verbosity_pkg" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
type="SYSTEM_VERILOG"
library="error_adapter_0" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v"
type="VERILOG"
library="avalon_st_adapter" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv"
type="SYSTEM_VERILOG"
library="rsp_mux_001" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
library="rsp_mux_001" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv"
type="SYSTEM_VERILOG"
library="rsp_mux" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
library="rsp_mux" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv"
type="SYSTEM_VERILOG"
library="rsp_demux" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv"
type="SYSTEM_VERILOG"
library="cmd_mux_002" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
library="cmd_mux_002" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv"
type="SYSTEM_VERILOG"
library="cmd_mux" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
library="cmd_mux" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv"
type="SYSTEM_VERILOG"
library="cmd_demux_001" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv"
type="SYSTEM_VERILOG"
library="cmd_demux" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv"
type="SYSTEM_VERILOG"
library="router_008" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv"
type="SYSTEM_VERILOG"
library="router_004" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv"
type="SYSTEM_VERILOG"
library="router_002" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv"
type="SYSTEM_VERILOG"
library="router_001" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv"
type="SYSTEM_VERILOG"
library="router" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v"
type="VERILOG"
library="jtag_uart_avalon_jtag_slave_agent_rsp_fifo" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv"
type="SYSTEM_VERILOG"
library="jtag_uart_avalon_jtag_slave_agent" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv"
type="SYSTEM_VERILOG"
library="jtag_uart_avalon_jtag_slave_agent" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv"
type="SYSTEM_VERILOG"
library="cpu_data_master_agent" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv"
type="SYSTEM_VERILOG"
library="jtag_uart_avalon_jtag_slave_translator" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv"
type="SYSTEM_VERILOG"
library="cpu_data_master_translator" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc"
type="SDC"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do"
type="OTHER"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat"
type="DAT"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex"
type="HEX"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif"
type="MIF"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat"
type="DAT"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex"
type="HEX"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif"
type="MIF"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat"
type="DAT"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex"
type="HEX"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif"
type="MIF"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v"
type="VERILOG"
library="rst_controller" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v"
type="VERILOG"
library="rst_controller" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc"
type="SDC"
library="rst_controller" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv"
type="SYSTEM_VERILOG"
library="irq_mapper" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v"
type="VERILOG"
library="mm_interconnect_0" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v"
type="VERILOG"
library="sys_clk_timer" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/dec.sv"
type="SYSTEM_VERILOG"
library="sem" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/periodram.v"
type="VERILOG"
library="sem" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex"
type="HEX"
library="mem" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v"
type="VERILOG"
library="mem" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v"
type="VERILOG"
library="jtag_uart" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv"
type="SYSTEM_VERILOG"
library="niosII_inst_reset_bfm" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv"
type="SYSTEM_VERILOG"
library="niosII_inst_clk_bfm" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII.v"
type="VERILOG"
library="niosII_inst" />
<file
path="niosII/testbench/niosII_tb/simulation/niosII_tb.v"
type="VERILOG" />
<topLevel name="niosII_tb" />
<deviceFamily name="cycloneive" />
<modelMap
controllerPath="niosII_tb.niosII_inst.mem"
modelPath="niosII_tb.niosII_inst.mem" />
</simPackage>

2
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@ -53,7 +53,7 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_
set_global_assignment -name QSYS_FILE niosII.qsys set_global_assignment -name QSYS_FILE niosII.qsys
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672">
<storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" moduleId="org.eclipse.cdt.core.settings"/>
</buildSystem>
<cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672">
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
<folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672." name="/" resourcePath="">
<toolChain id="altera.nios2.mingw.gcc4.1451739338" name="MinGW Nios II GCC4" superClass="altera.nios2.mingw.gcc4">
<targetPlatform id="altera.nios2.mingw.gcc4.1894897402" name="Nios II" superClass="altera.nios2.mingw.gcc4"/>
<builder buildPath="${workspace_loc://semafor}" id="altera.tool.gnu.builder.mingw.1910544022" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder.mingw"/>
<tool id="altera.tool.gnu.c.compiler.mingw.2112423510" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler.mingw">
<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.181439709" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
</tool>
<tool id="altera.tool.gnu.cpp.compiler.mingw.1092618596" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler.mingw">
<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.693221313" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
</tool>
<tool id="altera.tool.gnu.archiver.mingw.1773720286" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver.mingw"/>
<tool id="altera.tool.gnu.c.linker.mingw.544112231" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker.mingw"/>
<tool id="altera.tool.gnu.assembler.mingw.273557530" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler.mingw">
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.327317275" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
</tool>
</toolChain>
</folderInfo>
</configuration>
</storageModule>
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="semafor.null.1915366667" name="semafor"/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672.;altera.tool.gnu.c.compiler.mingw.2112423510;cdt.managedbuild.tool.gnu.c.compiler.input.181439709">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672.;altera.tool.gnu.cpp.compiler.mingw.1092618596;cdt.managedbuild.tool.gnu.cpp.compiler.input.693221313">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets">
<buildTargets>
<target name="mem_init_install" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>mem_init_install</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>false</useDefaultCommand>
<runAllBuilders>false</runAllBuilders>
</target>
<target name="mem_init_generate" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>mem_init_generate</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>false</useDefaultCommand>
<runAllBuilders>false</runAllBuilders>
</target>
<target name="help" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>help</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>false</useDefaultCommand>
<runAllBuilders>false</runAllBuilders>
</target>
</buildTargets>
</storageModule>
</cproject>

40
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@ -0,0 +1,40 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>semafor</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>com.altera.sbtgui.project.makefileBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>com.altera.sbtgui.project.makefileBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>com.altera.sbtgui.project.SBTGUINature</nature>
<nature>com.altera.sbtgui.project.SBTGUIAppNature</nature>
<nature>com.altera.sbtgui.project.SBTGUIManagedNature</nature>
</natures>
</projectDescription>

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@ -0,0 +1,15 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" name="Nios II">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="1089225399946275972" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="altera.tool.Nios2GCCBuildCommandParser" keep-relative-paths="false" name="Nios II GCC Build Output Parser" parameter="(nios2-elf-gcc)|(nios2-elf-g\+\+)" prefer-non-shared="true"/>
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
</extension>
</configuration>
</project>

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Top/software/semafor/altera_avalon_sem_regs.h Normal file
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@ -0,0 +1,42 @@
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#ifndef __ALTERA_AVALON_SEM_REGS_H__
#define __ALTERA_AVALON_SEM_REGS_H__
#include <io.h>
#define IORD_ALTERA_AVALON_SEM_CTL(base) IORD(base, 0)
#define IOWR_ALTERA_AVALON_SEM_CTL(base, data) IOWR(base, 0, data)
#define IORD_ALTERA_AVALON_SEM_DIVSET(base) IORD(base, 1)
#define IOWR_ALTERA_AVALON_SEM_DIVSET(base, data) IOWR(base, 1, data)
#endif /* __ALTERA_AVALON_SEM_REGS_H__ */

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@ -0,0 +1,114 @@
#!/bin/bash
#
# This script creates the blank_project application in this directory.
BSP_DIR=../semafor_bsp
QUARTUS_PROJECT_DIR=../../
NIOS2_APP_GEN_ARGS="--elf-name semafor.elf --no-src --set OBJDUMP_INCLUDE_SOURCE 1"
# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set.
# This variable is required for the command line tools to execute correctly.
if [ -z "${SOPC_KIT_NIOS2}" ]
then
echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set!
exit 1
fi
# Also make sure that the APP has not been created already. Check for
# existence of Makefile in the app directory
if [ -f ./Makefile ]
then
echo Application has already been created! Delete Makefile if you want to create a new application makefile
exit 1
fi
# We are selecting hal_default bsp because it supports this application.
# Check to see if the hal_default has already been generated by checking for
# existence of the public.mk file. If not, we need to run
# create-this-bsp file to generate the bsp.
if [ ! -f ${BSP_DIR}/public.mk ]; then
# Since BSP doesn't exist, create the BSP
# Pass any command line arguments passed to this script to the BSP.
pushd ${BSP_DIR} >> /dev/null
./create-this-bsp "$@" || {
echo "create-this-bsp failed"
exit 1
}
popd >> /dev/null
fi
# Don't run make if create-this-app script is called with --no-make arg
SKIP_MAKE=
while [ $# -gt 0 ]
do
case "$1" in
--no-make)
SKIP_MAKE=1
;;
esac
shift
done
# Now we also need to go copy the sources for this application to the
# local directory.
find "${SOPC_KIT_NIOS2}/examples/software/blank_project/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || {
echo "failed during copying example source files"
exit 1
}
find "${SOPC_KIT_NIOS2}/examples/software/blank_project/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || {
echo "failed copying readme file"
}
if [ -d "${SOPC_KIT_NIOS2}/examples/software/blank_project/system" ]
then
cp -RL "${SOPC_KIT_NIOS2}/examples/software/blank_project/system" . || {
echo "failed during copying project support files"
exit 1
}
fi
chmod -R +w . || {
echo "failed during changing file permissions"
exit 1
}
cmd="nios2-app-generate-makefile --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}"
echo "create-this-app: Running \"${cmd}\""
$cmd || {
echo "nios2-app-generate-makefile failed"
exit 1
}
if [ -z "$SKIP_MAKE" ]; then
cmd="make"
echo "create-this-app: Running \"$cmd\""
$cmd || {
echo "make failed"
exit 1
}
echo
echo "To download and run the application:"
echo " 1. Make sure the board is connected to the system."
echo " 2. Run 'nios2-configure-sof <SOF_FILE_PATH>' to configure the FPGA with the hardware design."
echo " 3. If you have a stdio device, run 'nios2-terminal' in a different shell."
echo " 4. Run 'make download-elf' from the application directory."
echo
echo "To debug the application:"
echo " Import the project into Nios II Software Build Tools for Eclipse."
echo " Refer to Nios II Software Build Tools for Eclipse Documentation for more information."
echo
echo -e ""
fi
exit 0

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00000000 A __alt_mem_mem
00000000 T __reset
00000020 T alt_exception
00000020 T alt_irq_entry
000000fc T alt_irq_handler
000001d0 T alt_instruction_exception_entry
00000230 T _start
00000244 t alt_after_alt_main
00000248 T main
00000330 T _puts_r
000003f0 T puts
00000404 T strlen
0000049c t __fp_unlock
000004a4 T _cleanup_r
000004b0 t __sinit.part.1
0000064c t __fp_lock
00000654 T __sfmoreglue
000006cc T __sfp
000007e4 T _cleanup
000007fc T __sinit
0000080c T __sfp_lock_acquire
00000810 T __sfp_lock_release
00000814 T __sinit_lock_acquire
00000818 T __sinit_lock_release
0000081c T __fp_lock_all
00000834 T __fp_unlock_all
0000084c T __sfvwrite_r
00000d14 T _fwalk
00000dd8 T _fwalk_reent
00000e9c T _malloc_r
000016a8 T memchr
0000178c T memcpy
000018d4 T memmove
00001a30 T memset
00001b58 T _realloc_r
000020bc T _sbrk_r
00002110 T __sread
00002164 T __seofread
0000216c T __swrite
000021e8 T __sseek
00002244 T __sclose
0000224c T _write_r
000022ac T __swsetup_r
00002400 T _close_r
00002454 T _fclose_r
00002544 T fclose
00002558 T __sflush_r
00002774 T _fflush_r
000027d0 T fflush
00002800 T _malloc_trim_r
00002924 T _free_r
00002c34 T _lseek_r
00002c94 T __smakebuf_r
00002e50 T _read_r
00002eb0 T _fstat_r
00002f0c T _isatty_r
00002f60 T __divsi3
00002fe4 T __modsi3
00003058 T __udivsi3
000030bc T __umodsi3
00003114 T __mulsi3
0000313c t alt_get_errno
00003178 T close
00003250 T alt_dcache_flush
00003278 t alt_dev_null_write
000032a4 t alt_get_errno
000032e0 T fstat
00003398 t alt_get_errno
000033d4 T isatty
00003480 t alt_get_errno
000034bc T lseek
00003598 T alt_main
00003614 T __malloc_lock
00003638 T __malloc_unlock
0000365c t alt_get_errno
00003698 T read
0000379c T alt_release_fd
00003820 T sbrk
000038d0 t alt_get_errno
0000390c T write
00003a0c t alt_dev_reg
00003a40 T alt_irq_init
00003a78 T alt_sys_init
00003ad8 T altera_avalon_jtag_uart_read_fd
00003b38 T altera_avalon_jtag_uart_write_fd
00003b98 T altera_avalon_jtag_uart_close_fd
00003be8 T altera_avalon_jtag_uart_ioctl_fd
00003c3c T altera_avalon_jtag_uart_init
00003cfc t altera_avalon_jtag_uart_irq
00003f08 t altera_avalon_jtag_uart_timeout
00003fa8 T altera_avalon_jtag_uart_close
00004010 T altera_avalon_jtag_uart_ioctl
00004100 T altera_avalon_jtag_uart_read
0000431c T altera_avalon_jtag_uart_write
00004540 t alt_avalon_timer_sc_irq
000045b8 T alt_avalon_timer_sc_init
00004634 T alt_alarm_start
00004760 t alt_get_errno
0000479c T alt_dev_llist_insert
00004840 T _do_ctors
000048a0 T _do_dtors
00004900 T alt_ic_isr_register
00004950 T alt_ic_irq_enable
000049d8 T alt_ic_irq_disable
00004a64 T alt_ic_irq_enabled
00004ab0 T alt_iic_isr_register
00004ba0 t alt_open_fd
00004c84 T alt_io_redirect
00004d00 t alt_get_errno
00004d3c t alt_file_locked
00004e28 T open
00004f84 T alt_alarm_stop
00005020 T alt_tick
00005128 T altera_nios2_gen2_irq_init
0000514c T alt_find_dev
000051dc T alt_find_file
000052e4 T alt_get_fd
000053a8 T alt_exception_cause_generated_bad_addr
00005444 T atexit
00005458 T exit
00005490 T memcmp
0000550c T __register_exitproc
00005624 T __call_exitprocs
000057a4 T _exit
000057d8 A __CTOR_END__
000057d8 A __CTOR_LIST__
000057d8 A __DTOR_END__
000057d8 A __DTOR_LIST__
000057d8 R divisors
00005824 g impure_data
00005c48 G __malloc_av_
00006050 G alt_dev_null
00006078 G alt_fd_list
000061f8 g jtag_uart
00007258 G _global_impure_ptr
0000725c G _impure_ptr
00007260 G __malloc_sbrk_base
00007264 G __malloc_trim_threshold
00007268 G alt_fs_list
00007270 G alt_dev_list
00007278 G alt_max_fd
0000727c G alt_errno
00007280 g heap_end
00007284 G alt_priority_mask
00007288 G alt_alarm_list
00007290 A __bss_start
00007290 B __malloc_max_total_mem
00007290 A _edata
00007294 B __malloc_max_sbrked_mem
00007298 B __malloc_top_pad
0000729c B errno
000072a0 B alt_argc
000072a4 B alt_argv
000072a8 B alt_envp
000072ac B alt_irq_active
000072b0 B _alt_tick_rate
000072b4 B _alt_nticks
000072b8 B alt_instruction_exception_handler
000072bc B __malloc_current_mallinfo
000072e4 B alt_irq
000073e4 A __alt_heap_start
000073e4 A __alt_stack_base
000073e4 A __bss_end
000073e4 A _end
000073e4 A end
0000f258 A _gp
00020000 A __alt_data_end
00020000 A __alt_heap_limit
00020000 A __alt_stack_pointer

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set_global_assignment -name SEARCH_PATH $::quartus(qip_path)

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<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file path="hdl_sim/niosII_mem.dat" type="DAT" initParamName="INIT_FILE" memoryPath="mem" />
<file path="niosII_mem.hex" type="HEX" initParamName="INIT_FILE" memoryPath="mem" />
</simPackage>

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This template is starting point for creating a project based on your custom C code.
It will provide you a default project to which you can add your software files. To
add files to a project, manually copy the file into the application directory (e.g.
using Windows Explorer), then right click on your application project and select
refresh.
You can also add files to the project using the Nios II Software Build Tools for Eclipse import function.
Select File -> Import.
Expand General and select File System in the Import Window and click Next.
Identify the appropriate source and destination directories.
Check the files you want to add and click Finish.

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#include <stdio.h>
#include "altera_avalon_sem_regs.h"
#include "alt_types.h"
#include "system.h"
#define TIME_SETS 4
#define TIME_STATES 4
const alt_u8 divisors[TIME_SETS][TIME_STATES] = {
{100,100, 50,10},
{100,200,100,10},
{150,250,200,10},
{250,250,250,10}
};
int main()
{
int i,j;
volatile alt_u32 *p;
alt_u32 tmp;
//program divisors
p = (alt_u32*) SEM_RAM_SLAVE_BASE;
for (i=0; i<TIME_SETS; i++)
{
tmp = 0;
for (j=TIME_STATES; j>0; j--)
{
tmp = (tmp << 8) | divisors[i][j-1];
}
*p=tmp;
p++;
}
//since we use pointers (cached data access) to write divisor RAM,
//and not direct i/o access with IOWR, we need to flush cache
alt_dcache_flush();
//select timeset and run semafor
IOWR_ALTERA_AVALON_SEM_DIVSET(SEM_CTL_SLAVE_BASE,0x00);
IOWR_ALTERA_AVALON_SEM_CTL(SEM_CTL_SLAVE_BASE,0x01);
printf("Ready\n");
while (1)
{
;
}
return 0;
}

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# Reading C:/Software/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529">
<storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" moduleId="org.eclipse.cdt.core.settings"/>
</buildSystem>
<cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529">
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
<folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529." name="/" resourcePath="">
<toolChain id="altera.nios2.mingw.gcc4.1075875993" name="MinGW Nios II GCC4" superClass="altera.nios2.mingw.gcc4">
<targetPlatform id="altera.nios2.mingw.gcc4.199526272" name="Nios II" superClass="altera.nios2.mingw.gcc4"/>
<builder buildPath="${workspace_loc://semafor_bsp}" id="altera.tool.gnu.builder.mingw.739389354" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder.mingw"/>
<tool id="altera.tool.gnu.c.compiler.mingw.1217641548" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler.mingw">
<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.2069582818" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
</tool>
<tool id="altera.tool.gnu.cpp.compiler.mingw.1496541669" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler.mingw">
<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.1563108919" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
</tool>
<tool id="altera.tool.gnu.archiver.mingw.2037617920" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver.mingw"/>
<tool id="altera.tool.gnu.c.linker.mingw.1007181127" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker.mingw"/>
<tool id="altera.tool.gnu.assembler.mingw.1082928765" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler.mingw">
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.2052885548" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
</tool>
</toolChain>
</folderInfo>
</configuration>
</storageModule>
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="semafor_bsp.null.1473022277" name="semafor_bsp"/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529.;altera.tool.gnu.cpp.compiler.mingw.1496541669;cdt.managedbuild.tool.gnu.cpp.compiler.input.1563108919">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529.;altera.tool.gnu.c.compiler.mingw.1217641548;cdt.managedbuild.tool.gnu.c.compiler.input.2069582818">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
</cproject>

0
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Top/software/semafor_bsp/.project Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>semafor_bsp</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>com.altera.sbtgui.project.SBTGUINature</nature>
<nature>com.altera.sbtgui.project.SBTGUIBspNature</nature>
</natures>
</projectDescription>

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" name="Nios II">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="1089225399946275972" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="altera.tool.Nios2GCCBuildCommandParser" keep-relative-paths="false" name="Nios II GCC Build Output Parser" parameter="(nios2-elf-gcc)|(nios2-elf-g\+\+)" prefer-non-shared="true"/>
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
</extension>
</configuration>
</project>

769
Top/software/semafor_bsp/Makefile Normal file
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#------------------------------------------------------------------------------
# BSP MAKEFILE
#
# This makefile was automatically generated by the nios2-bsp-generate-files
# command. Its purpose is to build a custom Board Support Package (BSP)
# targeting a specific Nios II processor in an SOPC Builder-based design.
#
# To create an application or library Makefile which uses this BSP, try the
# nios2-app-generate-makefile or nios2-lib-generate-makefile commands.
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
# TOOLS
#------------------------------------------------------------------------------
MKDIR := mkdir -p
ECHO := echo
SPACE := $(empty) $(empty)
#------------------------------------------------------------------------------
# The adjust-path macro
#
# If COMSPEC is defined, Make is launched from Windows through
# Cygwin. This adjust-path macro will call 'cygpath -u' on all
# paths to ensure they are readable by Make.
#
# If COMSPEC is not defined, Make is launched from *nix, and no adjustment
# is necessary
#------------------------------------------------------------------------------
ifndef COMSPEC
ifdef ComSpec
COMSPEC = $(ComSpec)
endif # ComSpec
endif # !COMSPEC
ifdef COMSPEC
adjust-path = $(subst $(SPACE),\$(SPACE),$(shell cygpath -u "$1"))
adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$(shell cygpath -m "$1"))
else
adjust-path = $(subst $(SPACE),\$(SPACE),$1)
adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$1)
endif
#------------------------------------------------------------------------------
# DEFAULT TARGET
#
# The default target, "all", must appear before any other target in the
# Makefile. Note that extra prerequisites are added to the "all" rule later.
#------------------------------------------------------------------------------
.PHONY: all
all:
@$(ECHO) [BSP build complete]
#------------------------------------------------------------------------------
# PATHS & DIRECTORY NAMES
#
# Explicitly locate absolute path of the BSP root
#------------------------------------------------------------------------------
BSP_ROOT_DIR := .
# Define absolute path to the root of the BSP.
ABS_BSP_ROOT := $(call adjust-path-mixed,$(shell pwd))
# Stash all BSP object files here
OBJ_DIR := ./obj
#------------------------------------------------------------------------------
# MANAGED CONTENT
#
# All content between the lines "START MANAGED" and "END MANAGED" below is
# generated based on variables in the BSP settings file when the
# nios2-bsp-generate-files command is invoked. If you wish to persist any
# information pertaining to the build process, it is recomended that you
# utilize the BSP settings mechanism to do so.
#
# Note that most variable assignments in this section have a corresponding BSP
# setting that can be changed by using the nios2-bsp-create-settings or
# nios2-bsp-update-settings command before nios2-bsp-generate-files; if you
# want any variable set to a specific value when this Makefile is re-generated
# (to prevent hand-edits from being over-written), use the BSP settings
# facilities above.
#------------------------------------------------------------------------------
#START MANAGED
# The following TYPE comment allows tools to identify the 'type' of target this
# makefile is associated with.
# TYPE: BSP_PRIVATE_MAKEFILE
# This following VERSION comment indicates the version of the tool used to
# generate this makefile. A makefile variable is provided for VERSION as well.
# ACDS_VERSION: 18.1
ACDS_VERSION := 18.1
# This following BUILD_NUMBER comment indicates the build number of the tool
# used to generate this makefile.
# BUILD_NUMBER: 625
SETTINGS_FILE := settings.bsp
SOPC_FILE := ../../niosII.sopcinfo
#-------------------------------------------------------------------------------
# TOOL & COMMAND DEFINITIONS
#
# The base command for each build operation are expressed here. Additional
# switches may be expressed here. They will run for all instances of the
# utility.
#-------------------------------------------------------------------------------
# Archiver command. Creates library files.
AR = nios2-elf-ar
# Assembler command. Note that CC is used for .S files.
AS = nios2-elf-gcc
# Custom flags only passed to the archiver. This content of this variable is
# directly passed to the archiver rather than the more standard "ARFLAGS". The
# reason for this is that GNU Make assumes some default content in ARFLAGS.
# This setting defines the value of BSP_ARFLAGS in Makefile.
BSP_ARFLAGS = -src
# Custom flags only passed to the assembler. This setting defines the value of
# BSP_ASFLAGS in Makefile.
BSP_ASFLAGS = -Wa,-gdwarf2
# C/C++ compiler debug level. '-g' provides the default set of debug symbols
# typically required to debug a typical application. Omitting '-g' removes
# debug symbols from the ELF. This setting defines the value of
# BSP_CFLAGS_DEBUG in Makefile.
BSP_CFLAGS_DEBUG = -g
# C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal"
# optimization, etc. "-O0" is recommended for code that you want to debug since
# compiler optimization can remove variables and produce non-sequential
# execution of code while debugging. This setting defines the value of
# BSP_CFLAGS_OPTIMIZATION in Makefile.
BSP_CFLAGS_OPTIMIZATION = -O0
# C/C++ compiler warning level. "-Wall" is commonly used.This setting defines
# the value of BSP_CFLAGS_WARNINGS in Makefile.
BSP_CFLAGS_WARNINGS = -Wall
# C compiler command.
CC = nios2-elf-gcc -xc
# C++ compiler command.
CXX = nios2-elf-gcc -xc++
# Command used to remove files during 'clean' target.
RM = rm -f
#-------------------------------------------------------------------------------
# BUILD PRE & POST PROCESS COMMANDS
#
# The following variables are treated as shell commands in the rule
# definitions for each file-type associated with the BSP build, as well as
# commands run at the beginning and end of the entire BSP build operation.
# Pre-process commands are executed before the relevant command (for example,
# a command defined in the "CC_PRE_PROCESS" variable executes before the C
# compiler for building .c files), while post-process commands are executed
# immediately afterwards.
#
# You can view each pre/post-process command in the "Build Rules: All &
# Clean", "Pattern Rules to Build Objects", and "Library Rules" sections of
# this Makefile.
#-------------------------------------------------------------------------------
#-------------------------------------------------------------------------------
# BSP SOURCE BUILD SETTINGS (FLAG GENERATION)
#
# Software build settings such as compiler optimization, debug level, warning
# flags, etc., may be defined in the following variables. The variables below
# are concatenated together in the 'Flags' section of this Makefile to form
# final variables of flags passed to the build tools.
#
# These settings are considered private to the BSP and apply to all library &
# driver files in it; they do NOT automatically propagate to, for example, the
# build settings for an application.
# # For additional detail and syntax requirements, please refer to GCC help
# (example: "nios2-elf-gcc --help --verbose").
#
# Unless indicated otherwise, multiple entries in each variable should be
# space-separated.
#-------------------------------------------------------------------------------
# Altera HAL alt_sys_init.c generated source file
GENERATED_C_FILES := $(ABS_BSP_ROOT)/alt_sys_init.c
GENERATED_C_LIB_SRCS += alt_sys_init.c
#-------------------------------------------------------------------------------
# BSP SOURCE FILE LISTING
#
# All source files that comprise the BSP are listed here, along with path
# information to each file expressed relative to the BSP root. The precise
# list and location of each file is derived from the driver, operating system,
# or software package source file declarations.
#
# Following specification of the source files for each component, driver, etc.,
# each source file type (C, assembly, etc.) is concatenated together and used
# to construct a list of objects. Pattern rules to build each object are then
# used to build each file.
#-------------------------------------------------------------------------------
# altera_avalon_jtag_uart_driver sources root
altera_avalon_jtag_uart_driver_SRCS_ROOT := drivers
# altera_avalon_jtag_uart_driver sources
altera_avalon_jtag_uart_driver_C_LIB_SRCS := \
$(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_init.c \
$(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_read.c \
$(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_write.c \
$(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_ioctl.c \
$(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_fd.c
# altera_avalon_timer_driver sources root
altera_avalon_timer_driver_SRCS_ROOT := drivers
# altera_avalon_timer_driver sources
altera_avalon_timer_driver_C_LIB_SRCS := \
$(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_sc.c \
$(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_ts.c \
$(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_vars.c
# altera_nios2_gen2_hal_driver sources root
altera_nios2_gen2_hal_driver_SRCS_ROOT := HAL
# altera_nios2_gen2_hal_driver sources
altera_nios2_gen2_hal_driver_C_LIB_SRCS := \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/altera_nios2_gen2_irq.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_usleep.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_busy_sleep.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_irq_vars.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_icache_flush.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_icache_flush_all.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_dcache_flush.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_dcache_flush_all.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_dcache_flush_no_writeback.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_ecc_fatal_exception.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_instruction_exception_entry.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_irq_register.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_iic.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_remap_cached.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_remap_uncached.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_uncached_free.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_uncached_malloc.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_do_ctors.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_do_dtors.c \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_gmon.c
altera_nios2_gen2_hal_driver_ASM_LIB_SRCS := \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_ecc_fatal_entry.S \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_exception_entry.S \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_exception_trap.S \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_exception_muldiv.S \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_irq_entry.S \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_software_exception.S \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_mcount.S \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/alt_log_macro.S \
$(altera_nios2_gen2_hal_driver_SRCS_ROOT)/src/crt0.S
# hal sources root
hal_SRCS_ROOT := HAL
# hal sources
hal_C_LIB_SRCS := \
$(hal_SRCS_ROOT)/src/alt_alarm_start.c \
$(hal_SRCS_ROOT)/src/alt_close.c \
$(hal_SRCS_ROOT)/src/alt_dev.c \
$(hal_SRCS_ROOT)/src/alt_dev_llist_insert.c \
$(hal_SRCS_ROOT)/src/alt_dma_rxchan_open.c \
$(hal_SRCS_ROOT)/src/alt_dma_txchan_open.c \
$(hal_SRCS_ROOT)/src/alt_environ.c \
$(hal_SRCS_ROOT)/src/alt_env_lock.c \
$(hal_SRCS_ROOT)/src/alt_errno.c \
$(hal_SRCS_ROOT)/src/alt_execve.c \
$(hal_SRCS_ROOT)/src/alt_exit.c \
$(hal_SRCS_ROOT)/src/alt_fcntl.c \
$(hal_SRCS_ROOT)/src/alt_fd_lock.c \
$(hal_SRCS_ROOT)/src/alt_fd_unlock.c \
$(hal_SRCS_ROOT)/src/alt_find_dev.c \
$(hal_SRCS_ROOT)/src/alt_find_file.c \
$(hal_SRCS_ROOT)/src/alt_flash_dev.c \
$(hal_SRCS_ROOT)/src/alt_fork.c \
$(hal_SRCS_ROOT)/src/alt_fs_reg.c \
$(hal_SRCS_ROOT)/src/alt_fstat.c \
$(hal_SRCS_ROOT)/src/alt_get_fd.c \
$(hal_SRCS_ROOT)/src/alt_getchar.c \
$(hal_SRCS_ROOT)/src/alt_getpid.c \
$(hal_SRCS_ROOT)/src/alt_gettod.c \
$(hal_SRCS_ROOT)/src/alt_iic_isr_register.c \
$(hal_SRCS_ROOT)/src/alt_instruction_exception_register.c \
$(hal_SRCS_ROOT)/src/alt_ioctl.c \
$(hal_SRCS_ROOT)/src/alt_io_redirect.c \
$(hal_SRCS_ROOT)/src/alt_irq_handler.c \
$(hal_SRCS_ROOT)/src/alt_isatty.c \
$(hal_SRCS_ROOT)/src/alt_kill.c \
$(hal_SRCS_ROOT)/src/alt_link.c \
$(hal_SRCS_ROOT)/src/alt_load.c \
$(hal_SRCS_ROOT)/src/alt_log_printf.c \
$(hal_SRCS_ROOT)/src/alt_lseek.c \
$(hal_SRCS_ROOT)/src/alt_main.c \
$(hal_SRCS_ROOT)/src/alt_malloc_lock.c \
$(hal_SRCS_ROOT)/src/alt_open.c \
$(hal_SRCS_ROOT)/src/alt_printf.c \
$(hal_SRCS_ROOT)/src/alt_putchar.c \
$(hal_SRCS_ROOT)/src/alt_putcharbuf.c \
$(hal_SRCS_ROOT)/src/alt_putstr.c \
$(hal_SRCS_ROOT)/src/alt_read.c \
$(hal_SRCS_ROOT)/src/alt_release_fd.c \
$(hal_SRCS_ROOT)/src/alt_rename.c \
$(hal_SRCS_ROOT)/src/alt_sbrk.c \
$(hal_SRCS_ROOT)/src/alt_settod.c \
$(hal_SRCS_ROOT)/src/alt_stat.c \
$(hal_SRCS_ROOT)/src/alt_tick.c \
$(hal_SRCS_ROOT)/src/alt_times.c \
$(hal_SRCS_ROOT)/src/alt_unlink.c \
$(hal_SRCS_ROOT)/src/alt_wait.c \
$(hal_SRCS_ROOT)/src/alt_write.c
# Assemble all component C source files
COMPONENT_C_LIB_SRCS += \
$(altera_avalon_jtag_uart_driver_C_LIB_SRCS) \
$(altera_avalon_timer_driver_C_LIB_SRCS) \
$(altera_nios2_gen2_hal_driver_C_LIB_SRCS) \
$(hal_C_LIB_SRCS)
# Assemble all component assembly source files
COMPONENT_ASM_LIB_SRCS += \
$(altera_nios2_gen2_hal_driver_ASM_LIB_SRCS)
# Assemble all component C++ source files
COMPONENT_CPP_LIB_SRCS += \
#END MANAGED
#------------------------------------------------------------------------------
# PUBLIC.MK
#
# The generated public.mk file contains BSP information that is shared with
# other external makefiles, such as a Nios II application makefile. System-
# dependent information such as hardware-specific compiler flags and
# simulation file generation are stored here.
#
# In addition, public.mk contains include paths that various software,
# such as a device driver, may need for the C compiler. These paths are
# written to public.mk with respect to the BSP root. In public.mk, each
# path is prefixed with a special variable, $(ALT_LIBRARY_ROOT_DIR). The
# purpose of this variable is to allow an external Makefile to append on
# path information to precisely locate paths expressed in public.mk
# Since this is the BSP Makefile, we set ALT_LIBRARY_ROOT_DIR to point right
# here ("."), at the BSP root.
#
# ALT_LIBRARY_ROOT_DIR must always be set before public.mk is included.
#------------------------------------------------------------------------------
ALT_LIBRARY_ROOT_DIR := .
include public.mk
#------------------------------------------------------------------------------
# FLAGS
#
# Include paths for BSP files are written into the public.mk file and must
# be added to the existing list of pre-processor flags. In addition, "hooks"
# for standard flags left intentionally empty (CFLAGS, CPPFLAGS, ASFLAGS,
# and CXXFLAGS) are provided for conveniently adding to the relevant flags
# on the command-line or via script that calls make.
#------------------------------------------------------------------------------
# Assemble final list of compiler flags from generated content
BSP_CFLAGS += \
$(BSP_CFLAGS_DEFINED_SYMBOLS) \
$(BSP_CFLAGS_UNDEFINED_SYMBOLS) \
$(BSP_CFLAGS_OPTIMIZATION) \
$(BSP_CFLAGS_DEBUG) \
$(BSP_CFLAGS_WARNINGS) \
$(BSP_CFLAGS_USER_FLAGS) \
$(ALT_CFLAGS) \
$(CFLAGS)
# Make ready the final list of include directories and other C pre-processor
# flags. Each include path is made ready by prefixing it with "-I".
BSP_CPPFLAGS += \
$(addprefix -I, $(BSP_INC_DIRS)) \
$(addprefix -I, $(ALT_INCLUDE_DIRS)) \
$(ALT_CPPFLAGS) \
$(CPPFLAGS)
# Finish off assembler flags with any user-provided flags
BSP_ASFLAGS += $(ASFLAGS)
# Finish off C++ flags with any user-provided flags
BSP_CXXFLAGS += $(CXXFLAGS)
# And finally, the ordered list
C_SRCS += $(GENERATED_C_LIB_SRCS) \
$(COMPONENT_C_LIB_SRCS)
CXX_SRCS += $(GENERATED_CPP_LIB_SRCS) \
$(COMPONENT_CPP_LIB_SRCS)
ASM_SRCS += $(GENERATED_ASM_LIB_SRCS) \
$(COMPONENT_ASM_LIB_SRCS)
#------------------------------------------------------------------------------
# LIST OF GENERATED FILES
#
# A Nios II BSP relies on the generation of several source files used
# by both the BSP and any applications referencing the BSP.
#------------------------------------------------------------------------------
GENERATED_H_FILES := $(ABS_BSP_ROOT)/system.h
GENERATED_LINKER_SCRIPT := $(ABS_BSP_ROOT)/linker.x
GENERATED_FILES += $(GENERATED_H_FILES) \
$(GENERATED_LINKER_SCRIPT)
#------------------------------------------------------------------------------
# SETUP TO BUILD OBJECTS
#
# List of object files which are to be built. This is constructed from the input
# list of C source files (C_SRCS), C++ source files (CXX_SRCS), and assembler
# source file (ASM_SRCS). The permitted file extensions are:
#
# .c .C - for C files
# .cxx .cc .cpp .CXX .CC .CPP - for C++ files
# .S .s - for assembly files
#
# Extended description: The list of objects is a sorted list (duplicates
# removed) of all possible objects, placed beneath the ./obj directory,
# including any path information stored in the "*_SRCS" variable. The
# "patsubst" commands are used to concatenate together multiple file suffix
# types for common files (i.e. c++ as .cxx, .cc, .cpp).
#
# File extensions are case-insensitive in build rules with the exception of
# assembly sources. Nios II assembly sources with the ".S" extension are first
# run through the C preprocessor. Sources with the ".s" extension are not.
#------------------------------------------------------------------------------
OBJS = $(sort $(addprefix $(OBJ_DIR)/, \
$(patsubst %.c, %.o, $(patsubst %.C, %.o, $(C_SRCS))) \
$(patsubst %.cxx, %.o, $(patsubst %.CXX, %.o, \
$(patsubst %.cc, %.o, $(patsubst %.CC, %.o, \
$(patsubst %.cpp, %.o, $(patsubst %.CPP, %.o, \
$(CXX_SRCS) )))))) \
$(patsubst %.S, %.o, $(patsubst %.s, %.o, $(ASM_SRCS))) ))
# List of dependancy files for each object file.
DEPS = $(OBJS:.o=.d)
# Rules to force your project to rebuild or relink
# .force_relink file will cause any application that depends on this project to relink
# .force_rebuild file will cause this project to rebuild object files
# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files
FORCE_RELINK_DEP := .force_relink
FORCE_REBUILD_DEP := .force_rebuild
FORCE_REBUILD_ALL_DEP := .force_rebuild_all
FORCE_REBUILD_DEP_LIST := $(FORCE_RELINK_DEP) $(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP)
$(FORCE_REBUILD_DEP_LIST):
$(OBJS): $(wildcard $(FORCE_REBUILD_DEP)) $(wildcard $(FORCE_REBUILD_ALL_DEP))
#------------------------------------------------------------------------------
# BUILD RULES: ALL & CLEAN
#------------------------------------------------------------------------------
.DELETE_ON_ERROR:
.PHONY: all
all: build_pre_process
all: Makefile $(GENERATED_FILES) $(BSP_LIB) $(NEWLIB_DIR)
all: build_post_process
# clean: remove .o/.a/.d
.PHONY: clean
clean:
@$(RM) -r $(BSP_LIB) $(OBJ_DIR) $(FORCE_REBUILD_DEP_LIST)
ifneq ($(wildcard $(NEWLIB_DIR)),)
@$(RM) -r $(NEWLIB_DIR)
endif
@$(ECHO) [BSP clean complete]
#------------------------------------------------------------------------------
# BUILD PRE/POST PROCESS
#------------------------------------------------------------------------------
build_pre_process :
$(BUILD_PRE_PROCESS)
build_post_process :
$(BUILD_POST_PROCESS)
.PHONY: build_pre_process build_post_process
#------------------------------------------------------------------------------
# MAKEFILE UP TO DATE?
#
# Is this very Makefile up to date? Someone may have changed the BSP settings
# file or the associated target hardware.
#------------------------------------------------------------------------------
# Skip this check when clean is the only target
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(wildcard $(SETTINGS_FILE)),$(SETTINGS_FILE))
$(warning Warning: BSP Settings File $(SETTINGS_FILE) could not be found.)
endif
Makefile: $(wildcard $(SETTINGS_FILE))
@$(ECHO) Makefile not up to date.
@$(ECHO) $(SETTINGS_FILE) has been modified since the BSP Makefile was generated.
@$(ECHO)
@$(ECHO) Generate the BSP to update the Makefile, and then build again.
@$(ECHO)
@$(ECHO) To generate from Eclipse:
@$(ECHO) " 1. Right-click the BSP project."
@$(ECHO) " 2. In the Nios II Menu, click Generate BSP."
@$(ECHO)
@$(ECHO) To generate from the command line:
@$(ECHO) " nios2-bsp-generate-files --settings=<settings file> --bsp-dir=<target bsp files directory>"
@$(ECHO)
@exit 1
ifneq ($(wildcard $(SOPC_FILE)),$(SOPC_FILE))
$(warning Warning: SOPC File $(SOPC_FILE) could not be found.)
endif
public.mk: $(wildcard $(SOPC_FILE))
@$(ECHO) Makefile not up to date.
@$(ECHO) $(SOPC_FILE) has been modified since the BSP was generated.
@$(ECHO)
@$(ECHO) Generate the BSP to update the Makefile, and then build again.
@$(ECHO)
@$(ECHO) To generate from Eclipse:
@$(ECHO) " 1. Right-click the BSP project."
@$(ECHO) " 2. In the Nios II Menu, click Generate BSP."
@$(ECHO)
@$(ECHO) To generate from the command line:
@$(ECHO) " nios2-bsp-generate-files --settings=<settings file> --bsp-dir=<target bsp files directory>"
@$(ECHO)
@exit 1
endif # $(MAKECMDGOALS) != clean
#------------------------------------------------------------------------------
# PATTERN RULES TO BUILD OBJECTS
#------------------------------------------------------------------------------
$(OBJ_DIR)/%.o: %.c
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(CC_PRE_PROCESS)
$(CC) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CC_POST_PROCESS)
$(OBJ_DIR)/%.o: %.C
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(CC_PRE_PROCESS)
$(CC) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CC_POST_PROCESS)
$(OBJ_DIR)/%.o: %.cpp
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(CXX_PRE_PROCESS)
$(CXX) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CXXFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CXX_POST_PROCESS)
$(OBJ_DIR)/%.o: %.CPP
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(CXX_PRE_PROCESS)
$(CXX) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CXXFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CXX_POST_PROCESS)
$(OBJ_DIR)/%.o: %.cc
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(CXX_PRE_PROCESS)
$(CXX) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CXXFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CXX_POST_PROCESS)
$(OBJ_DIR)/%.o: %.CC
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(CXX_PRE_PROCESS)
$(CXX) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CXXFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CXX_POST_PROCESS)
$(OBJ_DIR)/%.o: %.cxx
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(CXX_PRE_PROCESS)
$(CXX) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CXXFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CXX_POST_PROCESS)
$(OBJ_DIR)/%.o: %.CXX
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(CXX_PRE_PROCESS)
$(CXX) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CXXFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CXX_POST_PROCESS)
$(OBJ_DIR)/%.o: %.S
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(AS_PRE_PROCESS)
$(AS) -MP -MMD -c $(BSP_CFLAGS) $(BSP_CPPFLAGS) $(BSP_ASFLAGS) -o $@ $<
$(AS_POST_PROCESS)
$(OBJ_DIR)/%.o: %.s
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(AS_PRE_PROCESS)
$(AS) -MP -MMD -c $(BSP_ASFLAGS) $(BSP_CFLAGS) -o $@ $<
$(AS_POST_PROCESS)
# Pattern rules for making useful intermediate files
$(OBJ_DIR)/%.s: %.c
@$(ECHO) Compiling $(<F) to assembler...
@$(MKDIR) $(@D)
$(CC_PRE_PROCESS)
$(CC) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CC_POST_PROCESS)
$(OBJ_DIR)/%.s: %.cpp
@$(ECHO) Compiling $(<F) to assembler...
@$(MKDIR) $(@D)
$(CXX_PRE_PROCESS)
$(CXX) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CXXFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CXX_PRE_PROCESS)
$(OBJ_DIR)/%.s: %.cc
@$(ECHO) Compiling $(<F) to assembler...
@$(MKDIR) $(@D)
$(CXX_PRE_PROCESS)
$(CXX) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CXXFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CXX_PRE_PROCESS)
$(OBJ_DIR)/%.s: %.cxx
@$(ECHO) Compiling $(<F) to assembler...
@$(MKDIR) $(@D)
$(CXX_PRE_PROCESS)
$(CXX) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CXXFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CXX_PRE_PROCESS)
$(OBJ_DIR)/%.i: %.c
@$(ECHO) Compiling $(<F) to assembler...
@$(MKDIR) $(@D)
$(CC_PRE_PROCESS)
$(CC) -E $(CPPFLAGS) $(ALT_CFLAGS) $(CFLAGS) -o $@ $<
$(CC_PRE_PROCESS)
$(OBJ_DIR)/%.i: %.cpp
@$(ECHO) Compiling $(<F) to assembler...
@$(MKDIR) $(@D)
$(CXX_PRE_PROCESS)
$(CXX) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CXXFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CXX_PRE_PROCESS)
$(OBJ_DIR)/%.i: %.cc
@$(ECHO) Compiling $(<F) to assembler...
@$(MKDIR) $(@D)
$(CXX_PRE_PROCESS)
$(CXX) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CXXFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CXX_PRE_PROCESS)
$(OBJ_DIR)/%.i: %.cxx
@$(ECHO) Compiling $(<F) to assembler...
@$(MKDIR) $(@D)
$(CXX_PRE_PROCESS)
$(CXX) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CXXFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CXX_PRE_PROCESS)
# Pattern rules for building other object files.
%.o: %.c
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(CC_PRE_PROCESS)
$(CC) -MP -MMD -c $(CPPFLAGS) $(ALT_CFLAGS) $(CFLAGS) -o $@ $<
$(CC_POST_PROCESS)
%.o: %.cpp
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(CXX_POST_PROCESS)
$(CXX) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CXXFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CXX_POST_PROCESS)
%.o: %.cc
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(CXX_POST_PROCESS)
$(CXX) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CXXFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CXX_POST_PROCESS)
%.o: %.cxx
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(CXX_PRE_PROCESS)
$(CXX) -MP -MMD -c $(BSP_CPPFLAGS) $(BSP_CXXFLAGS) $(BSP_CFLAGS) -o $@ $<
$(CXX_POST_PROCESS)
%.o: %.S
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(AS_PRE_PROCESS)
$(AS) -MP -MMD -c $(BSP_CFLAGS) $(BSP_CPPFLAGS) $(BSP_ASFLAGS) -o $@ $<
$(AS_POST_PROCESS)
%.o: %.s
@$(ECHO) Compiling $(<F)...
@$(MKDIR) $(@D)
$(AS_PRE_PROCESS)
$(AS) -MP -MMD -c $(BSP_ASFLAGS) $(BSP_CFLAGS) -o $@ $<
$(AS_POST_PROCESS)
#------------------------------------------------------------------------------
# NEWLIB RULES
#------------------------------------------------------------------------------
ifneq ($(COMPILE_NEWLIB),)
NEWLIB_FLAGS += $(BSP_CFLAGS)
endif
ifneq ($(NEWLIB_DIR),)
$(NEWLIB_DIR):
@$(ECHO) Creating $(NEWLIB_DIR)...
nios2-newlib-gen --no-multilib $(NEWLIB_DIR)-build-tmp $(NEWLIB_DIR) --custom "$(NEWLIB_FLAGS)"
@$(ECHO) Removing $(NEWLIB_DIR)-build-tmp...
@$(RM) -rf $(NEWLIB_DIR)-build-tmp
endif
#------------------------------------------------------------------------------
# LIBRARY RULES
#------------------------------------------------------------------------------
$(BSP_LIB): $(OBJS)
@$(ECHO) Creating $@...
$(AR_PRE_PROCESS)
$(RM) -f $@
$(AR) $(BSP_ARFLAGS) $@ $^
$(AR_POST_PROCESS)
#------------------------------------------------------------------------------
# DEPENDENCY FILES
#------------------------------------------------------------------------------
ifneq ($(findstring clean, $(MAKECMDGOALS)),clean)
-include $(DEPS)
endif
# End of Makefile

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/*
* alt_sys_init.c - HAL initialization source
*
* Machine generated for CPU 'cpu' in SOPC Builder design 'niosII'
* SOPC Builder design path: ../../niosII.sopcinfo
*
* Generated: Wed Oct 19 15:19:38 MSK 2022
*/
/*
* DO NOT MODIFY THIS FILE
*
* Changing this file will have subtle consequences
* which will almost certainly lead to a nonfunctioning
* system. If you do modify this file, be aware that your
* changes will be overwritten and lost when this file
* is generated again.
*
* DO NOT MODIFY THIS FILE
*/
/*
* License Agreement
*
* Copyright (c) 2008
* Altera Corporation, San Jose, California, USA.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This agreement shall be governed in all respects by the laws of the State
* of California and by the laws of the United States of America.
*/
#include "system.h"
#include "sys/alt_irq.h"
#include "sys/alt_sys_init.h"
#include <stddef.h>
/*
* Device headers
*/
#include "altera_nios2_gen2_irq.h"
#include "altera_avalon_jtag_uart.h"
#include "altera_avalon_timer.h"
/*
* Allocate the device storage
*/
ALTERA_NIOS2_GEN2_IRQ_INSTANCE ( CPU, cpu);
ALTERA_AVALON_JTAG_UART_INSTANCE ( JTAG_UART, jtag_uart);
ALTERA_AVALON_TIMER_INSTANCE ( SYS_CLK_TIMER, sys_clk_timer);
/*
* Initialize the interrupt controller devices
* and then enable interrupts in the CPU.
* Called before alt_sys_init().
* The "base" parameter is ignored and only
* present for backwards-compatibility.
*/
void alt_irq_init ( const void* base )
{
ALTERA_NIOS2_GEN2_IRQ_INIT ( CPU, cpu);
alt_irq_cpu_enable_interrupts();
}
/*
* Initialize the non-interrupt controller devices.
* Called after alt_irq_init().
*/
void alt_sys_init( void )
{
ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer);
ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART, jtag_uart);
}

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#!/bin/bash
#
# This script creates the ucosii_net_zipfs Board Support Package (BSP).
BSP_TYPE=hal
BSP_DIR=.
SOPC_DIR=../../
SOPC_FILE=../../niosII.sopcinfo
NIOS2_BSP_ARGS=""
CPU_NAME=
if [ -n "$CPU_NAME" ]; then
NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS --cpu-name $CPU_NAME"
fi
# Don't run make if create-this-app script is called with --no-make arg
SKIP_MAKE=
while [ $# -gt 0 ]
do
case "$1" in
--no-make)
SKIP_MAKE=1
;;
*)
NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS $1"
;;
esac
shift
done
# Run nios2-bsp utility to create a hal BSP in this directory
# for the system with a .sopc file in $SOPC_FILE.
# Deprecating $SOPC_DIR in 10.1. Multiple .sopcinfo files in a directory may exist.
if [ -z "$SOPC_FILE" ]; then
echo "WARNING: Use of a directory for locating a .sopcinfo file is deprecated in 10.1. Multiple .sopcinfo files may exist. You must specify the full .sopcinfo path."
cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_DIR $NIOS2_BSP_ARGS"
else
cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_FILE $NIOS2_BSP_ARGS"
fi
echo "create-this-bsp: Running \"$cmd\""
$cmd || {
echo "$cmd failed"
exit 1
}
if [ -z "$SKIP_MAKE" ]; then
echo "create-this-bsp: Running make"
make
fi

BIN
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85
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/*
* linker.h - Linker script mapping information
*
* Machine generated for CPU 'cpu' in SOPC Builder design 'niosII'
* SOPC Builder design path: ../../niosII.sopcinfo
*
* Generated: Wed Oct 19 16:14:31 MSK 2022
*/
/*
* DO NOT MODIFY THIS FILE
*
* Changing this file will have subtle consequences
* which will almost certainly lead to a nonfunctioning
* system. If you do modify this file, be aware that your
* changes will be overwritten and lost when this file
* is generated again.
*
* DO NOT MODIFY THIS FILE
*/
/*
* License Agreement
*
* Copyright (c) 2008
* Altera Corporation, San Jose, California, USA.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This agreement shall be governed in all respects by the laws of the State
* of California and by the laws of the United States of America.
*/
#ifndef __LINKER_H_
#define __LINKER_H_
/*
* BSP controls alt_load() behavior in crt0.
*
*/
#define ALT_LOAD_EXPLICITLY_CONTROLLED
/*
* Base address and span (size in bytes) of each linker region
*
*/
#define MEM_REGION_BASE 0x20
#define MEM_REGION_SPAN 131040
#define RESET_REGION_BASE 0x0
#define RESET_REGION_SPAN 32
/*
* Devices associated with code sections
*
*/
#define ALT_EXCEPTIONS_DEVICE MEM
#define ALT_RESET_DEVICE MEM
#define ALT_RODATA_DEVICE MEM
#define ALT_RWDATA_DEVICE MEM
#define ALT_TEXT_DEVICE MEM
#endif /* __LINKER_H_ */

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/*
* linker.x - Linker script
*
* Machine generated for CPU 'cpu' in SOPC Builder design 'niosII'
* SOPC Builder design path: ../../niosII.sopcinfo
*
* Generated: Wed Oct 19 16:14:31 MSK 2022
*/
/*
* DO NOT MODIFY THIS FILE
*
* Changing this file will have subtle consequences
* which will almost certainly lead to a nonfunctioning
* system. If you do modify this file, be aware that your
* changes will be overwritten and lost when this file
* is generated again.
*
* DO NOT MODIFY THIS FILE
*/
/*
* License Agreement
*
* Copyright (c) 2008
* Altera Corporation, San Jose, California, USA.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This agreement shall be governed in all respects by the laws of the State
* of California and by the laws of the United States of America.
*/
MEMORY
{
reset : ORIGIN = 0x0, LENGTH = 32
mem : ORIGIN = 0x20, LENGTH = 131040
}
/* Define symbols for each memory base-address */
__alt_mem_mem = 0x0;
OUTPUT_FORMAT( "elf32-littlenios2",
"elf32-littlenios2",
"elf32-littlenios2" )
OUTPUT_ARCH( nios2 )
ENTRY( _start )
/*
* The alt_load() facility is disabled. This typically happens when an
* external bootloader is provided or the application runs in place.
* The LMA (aka physical address) of each section defaults to its VMA.
*/
SECTIONS
{
/*
* Output sections associated with reset and exceptions (they have to be first)
*/
.entry :
{
KEEP (*(.entry))
} > reset
.exceptions :
{
PROVIDE (__ram_exceptions_start = ABSOLUTE(.));
. = ALIGN(0x20);
KEEP (*(.irq));
KEEP (*(.exceptions.entry.label));
KEEP (*(.exceptions.entry.user));
KEEP (*(.exceptions.entry.ecc_fatal));
KEEP (*(.exceptions.entry));
KEEP (*(.exceptions.irqtest.user));
KEEP (*(.exceptions.irqtest));
KEEP (*(.exceptions.irqhandler.user));
KEEP (*(.exceptions.irqhandler));
KEEP (*(.exceptions.irqreturn.user));
KEEP (*(.exceptions.irqreturn));
KEEP (*(.exceptions.notirq.label));
KEEP (*(.exceptions.notirq.user));
KEEP (*(.exceptions.notirq));
KEEP (*(.exceptions.soft.user));
KEEP (*(.exceptions.soft));
KEEP (*(.exceptions.unknown.user));
KEEP (*(.exceptions.unknown));
KEEP (*(.exceptions.exit.label));
KEEP (*(.exceptions.exit.user));
KEEP (*(.exceptions.exit));
KEEP (*(.exceptions));
PROVIDE (__ram_exceptions_end = ABSOLUTE(.));
} > mem
PROVIDE (__flash_exceptions_start = LOADADDR(.exceptions));
.text :
{
/*
* All code sections are merged into the text output section, along with
* the read only data sections.
*
*/
PROVIDE (stext = ABSOLUTE(.));
*(.interp)
*(.hash)
*(.dynsym)
*(.dynstr)
*(.gnu.version)
*(.gnu.version_d)
*(.gnu.version_r)
*(.rel.init)
*(.rela.init)
*(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
*(.rel.fini)
*(.rela.fini)
*(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
*(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
*(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
*(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
*(.rel.ctors)
*(.rela.ctors)
*(.rel.dtors)
*(.rela.dtors)
*(.rel.got)
*(.rela.got)
*(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
*(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
*(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
*(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
*(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
*(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
*(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
*(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
*(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
*(.rel.plt)
*(.rela.plt)
*(.rel.dyn)
KEEP (*(.init))
*(.plt)
*(.text .stub .text.* .gnu.linkonce.t.*)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning.*)
KEEP (*(.fini))
PROVIDE (__etext = ABSOLUTE(.));
PROVIDE (_etext = ABSOLUTE(.));
PROVIDE (etext = ABSOLUTE(.));
*(.eh_frame_hdr)
/* Ensure the __preinit_array_start label is properly aligned. We
could instead move the label definition inside the section, but
the linker would then create the section even if it turns out to
be empty, which isn't pretty. */
. = ALIGN(4);
PROVIDE (__preinit_array_start = ABSOLUTE(.));
*(.preinit_array)
PROVIDE (__preinit_array_end = ABSOLUTE(.));
PROVIDE (__init_array_start = ABSOLUTE(.));
*(.init_array)
PROVIDE (__init_array_end = ABSOLUTE(.));
PROVIDE (__fini_array_start = ABSOLUTE(.));
*(.fini_array)
PROVIDE (__fini_array_end = ABSOLUTE(.));
SORT(CONSTRUCTORS)
KEEP (*(.eh_frame))
*(.gcc_except_table .gcc_except_table.*)
*(.dynamic)
PROVIDE (__CTOR_LIST__ = ABSOLUTE(.));
KEEP (*(.ctors))
KEEP (*(SORT(.ctors.*)))
PROVIDE (__CTOR_END__ = ABSOLUTE(.));
PROVIDE (__DTOR_LIST__ = ABSOLUTE(.));
KEEP (*(.dtors))
KEEP (*(SORT(.dtors.*)))
PROVIDE (__DTOR_END__ = ABSOLUTE(.));
KEEP (*(.jcr))
. = ALIGN(4);
} > mem = 0x3a880100 /* NOP instruction (always in big-endian byte ordering) */
.rodata :
{
PROVIDE (__ram_rodata_start = ABSOLUTE(.));
. = ALIGN(4);
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
. = ALIGN(4);
PROVIDE (__ram_rodata_end = ABSOLUTE(.));
} > mem
PROVIDE (__flash_rodata_start = LOADADDR(.rodata));
.rwdata :
{
PROVIDE (__ram_rwdata_start = ABSOLUTE(.));
. = ALIGN(4);
*(.got.plt) *(.got)
*(.data1)
*(.data .data.* .gnu.linkonce.d.*)
_gp = ABSOLUTE(. + 0x8000);
PROVIDE(gp = _gp);
*(.rwdata .rwdata.*)
*(.sdata .sdata.* .gnu.linkonce.s.*)
*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
. = ALIGN(4);
_edata = ABSOLUTE(.);
PROVIDE (edata = ABSOLUTE(.));
PROVIDE (__ram_rwdata_end = ABSOLUTE(.));
} > mem
PROVIDE (__flash_rwdata_start = LOADADDR(.rwdata));
.bss :
{
__bss_start = ABSOLUTE(.);
PROVIDE (__sbss_start = ABSOLUTE(.));
PROVIDE (___sbss_start = ABSOLUTE(.));
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
*(.scommon)
PROVIDE (__sbss_end = ABSOLUTE(.));
PROVIDE (___sbss_end = ABSOLUTE(.));
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
__bss_end = ABSOLUTE(.);
} > mem
/*
*
* One output section mapped to the associated memory device for each of
* the available memory devices. These are not used by default, but can
* be used by user applications by using the .section directive.
*
* The output section used for the heap is treated in a special way,
* i.e. the symbols "end" and "_end" are added to point to the heap start.
*
*/
.mem :
{
PROVIDE (_alt_partition_mem_start = ABSOLUTE(.));
*(.mem .mem. mem.*)
. = ALIGN(4);
PROVIDE (_alt_partition_mem_end = ABSOLUTE(.));
_end = ABSOLUTE(.);
end = ABSOLUTE(.);
__alt_stack_base = ABSOLUTE(.);
} > mem
PROVIDE (_alt_partition_mem_load_addr = LOADADDR(.mem));
/*
* Stabs debugging sections.
*
*/
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* Altera debug extensions */
.debug_alt_sim_info 0 : { *(.debug_alt_sim_info) }
}
/* provide a pointer for the stack */
/*
* Don't override this, override the __alt_stack_* symbols instead.
*/
__alt_data_end = 0x20000;
/*
* The next two symbols define the location of the default stack. You can
* override them to move the stack to a different memory.
*/
PROVIDE( __alt_stack_pointer = __alt_data_end );
PROVIDE( __alt_stack_limit = __alt_stack_base );
/*
* This symbol controls where the start of the heap is. If the stack is
* contiguous with the heap then the stack will contract as memory is
* allocated to the heap.
* Override this symbol to put the heap in a different memory.
*/
PROVIDE( __alt_heap_start = end );
PROVIDE( __alt_heap_limit = 0x20000 );

344
Top/software/semafor_bsp/mem_init.mk Normal file
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@ -0,0 +1,344 @@
#########################################################################
####### M E M I N I T M A K E F I L E C O N T E N T ######
#########################################################################
#########################################################################
# This file is intended to be included by public.mk
#
#
# The following variables must be defined before including this file:
# - ELF
#
# The following variables may be defined to override the default behavior:
# - HDL_SIM_DIR
# - HDL_SIM_INSTALL_DIR
# - MEM_INIT_DIR
# - MEM_INIT_INSTALL_DIR
# - QUARTUS_PROJECT_DIR
# - SOPC_NAME
# - SIM_OPTIMIZE
# - RESET_ADDRESS
#
#########################################################################
ifeq ($(MEM_INIT_FILE),)
# MEM_INIT_FILE should be set equal to the working relative path to this
# mem_init.mk makefile fragment
MEM_INIT_FILE := $(wildcard $(word $(words $(MAKEFILE_LIST)),$(MAKEFILE_LIST)))
endif
ifeq ($(ELF2DAT),)
ELF2DAT := elf2dat
endif
ifeq ($(ELF2HEX),)
ELF2HEX := elf2hex
endif
ifeq ($(ELF2FLASH),)
ELF2FLASH := elf2flash
endif
ifeq ($(FLASH2DAT),)
FLASH2DAT := flash2dat
endif
ifeq ($(ALT_FILE_CONVERT),)
ALT_FILE_CONVERT := alt-file-convert
endif
ifeq ($(NM),)
NM := nios2-elf-nm
endif
ifeq ($(MKDIR),)
MKDIR := mkdir -p
endif
ifeq ($(RM),)
RM := rm -f
endif
ifeq ($(CP),)
CP := cp
endif
ifeq ($(ECHO),)
ECHO := echo
endif
MEM_INIT_DIR ?= mem_init
HDL_SIM_DIR ?= $(MEM_INIT_DIR)/hdl_sim
ifdef QUARTUS_PROJECT_DIR
MEM_INIT_INSTALL_DIR ?= $(patsubst %/,%,$(QUARTUS_PROJECT_DIR))
ifdef SOPC_NAME
HDL_SIM_INSTALL_DIR ?= $(patsubst %/,%,$(QUARTUS_PROJECT_DIR))/$(SOPC_NAME)_sim
endif
endif
MEM_INIT_DESCRIPTOR_FILE ?= $(MEM_INIT_DIR)/meminit.spd
MEM_INIT_QIP_FILE ?= $(MEM_INIT_DIR)/meminit.qip
#-------------------------------------
# Default Flash Boot Loaders
#-------------------------------------
BOOT_LOADER_PATH ?= $(SOPC_KIT_NIOS2)/components/altera_nios2
BOOT_LOADER_CFI ?= $(BOOT_LOADER_PATH)/boot_loader_cfi.srec
BOOT_LOADER_CFI_BE ?= $(BOOT_LOADER_PATH)/boot_loader_cfi_be.srec
#-------------------------------------
# Default Target
#-------------------------------------
.PHONY: default_mem_init
ifeq ($(QSYS),1)
default_mem_init: mem_init_generate
else
default_mem_init: mem_init_install
endif
#-------------------------------------
# Runtime Macros
#-------------------------------------
define post-process-info
@echo Post-processing to create $@...
endef
target_stem = $(notdir $(basename $@))
mem_start_address = $($(target_stem)_START)
mem_end_address = $($(target_stem)_END)
mem_span = $($(target_stem)_SPAN)
mem_width = $($(target_stem)_WIDTH)
mem_hex_width = $($(target_stem)_HEX_DATA_WIDTH)
mem_endianness = $($(target_stem)_ENDIANNESS)
mem_create_lanes = $($(target_stem)_CREATE_LANES)
mem_pad_flag = $($(target_stem)_PAD_FLAG)
mem_reloc_input_flag = $($(target_stem)_RELOC_INPUT_FLAG)
mem_no_zero_fill_flag = $($(target_stem)_NO_ZERO_FILL_FLAG)
flash_mem_epcs_flag = $($(target_stem)_EPCS_FLAGS)
flash_mem_cfi_flag = $($(target_stem)_CFI_FLAGS)
flash_mem_boot_loader_flag = $($(target_stem)_BOOT_LOADER_FLAG)
elf2dat_extra_args = $(mem_pad_flag)
elf2hex_extra_args = $(mem_no_zero_fill_flag)
elf2flash_extra_args = $(flash_mem_cfi_flag) $(flash_mem_epcs_flag) $(flash_mem_boot_loader_flag)
flash2dat_extra_args = $(mem_pad_flag) $(mem_reloc_input_flag)
#------------------------------------------------------------------------------
# BSP SPECIFIC CONTENT
#
# The content below is controlled by the BSP and SOPC System
#------------------------------------------------------------------------------
#START OF BSP SPECIFIC
#-------------------------------------
# Global Settings
#-------------------------------------
# The following TYPE comment allows tools to identify the 'type' of target this
# makefile is associated with.
# TYPE: BSP_MEMINIT_MAKEFILE
# This following VERSION comment indicates the version of the tool used to
# generate this makefile. A makefile variable is provided for VERSION as well.
# ACDS_VERSION: 18.1
ACDS_VERSION := 18.1
# This following BUILD_NUMBER comment indicates the build number of the tool
# used to generate this makefile.
# BUILD_NUMBER: 625
# Optimize for simulation
SIM_OPTIMIZE ?= 1
# The CPU reset address as needed by elf2flash
RESET_ADDRESS ?= 0x00000000
# The specific Nios II ELF file format to use.
NIOS2_ELF_FORMAT ?= elf32-littlenios2
#-------------------------------------
# Pre-Initialized Memory Descriptions
#-------------------------------------
# Memory: mem
MEM_0 := niosII_mem
$(MEM_0)_NAME := mem
$(MEM_0)_MEM_INIT_FILE_PARAM_NAME := INIT_FILE
HEX_FILES += $(MEM_INIT_DIR)/$(MEM_0).hex
MEM_INIT_INSTALL_FILES += $(MEM_INIT_INSTALL_DIR)/$(MEM_0).hex
DAT_FILES += $(HDL_SIM_DIR)/$(MEM_0).dat
HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).dat
SYM_FILES += $(HDL_SIM_DIR)/$(MEM_0).sym
HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).sym
$(MEM_0)_START := 0x00000000
$(MEM_0)_END := 0x0001ffff
$(MEM_0)_SPAN := 0x00020000
$(MEM_0)_HIERARCHICAL_PATH := mem
$(MEM_0)_WIDTH := 32
$(MEM_0)_HEX_DATA_WIDTH := 32
$(MEM_0)_ENDIANNESS := --little-endian-mem
$(MEM_0)_CREATE_LANES := 0
.PHONY: mem
mem: check_elf_exists $(MEM_INIT_DIR)/$(MEM_0).hex $(HDL_SIM_DIR)/$(MEM_0).dat $(HDL_SIM_DIR)/$(MEM_0).sym
#END OF BSP SPECIFIC
#-------------------------------------
# Pre-Initialized Memory Targets
#-------------------------------------
.PHONY: mem_init_install mem_init_generate mem_init_clean
ifeq ($(QSYS),1)
# Target mem_init_install is deprecated for QSys based systems
# To initialize onchip memories for Quartus II Synthesis with Qsys based systems:
# 1) Use "make mem_init_genearate"
# 2) Add the generated mem_init/meminit.qip file to your Quartus II Project
#
mem_init_install:
$(error Deprecated Makefile Target: '$@'. Use target 'mem_init_generate' and then add $(MEM_INIT_QIP_FILE) to your Quartus II Project)
else # QSYS != 1, if SopcBuilder based system
ifneq ($(MEM_INIT_INSTALL_DIR),)
mem_init_install: $(MEM_INIT_INSTALL_FILES)
endif
ifneq ($(HDL_SIM_INSTALL_DIR),)
mem_init_install: $(HDL_SIM_INSTALL_FILES)
endif
mem_init_install: mem_init_generate
ifeq ($(MEM_INIT_INSTALL_DIR),)
@echo "WARNING: MEM_INIT_INSTALL_DIR not set. Set your QUARTUS_PROJECT_DIR environment variable."
endif
ifeq ($(HDL_SIM_INSTALL_DIR),)
@echo "WARNING: HDL_SIM_INSTALL_DIR not set. Set your QUARTUS_PROJECT_DIR and SOPC_NAME environment variable."
endif
$(MEM_INIT_INSTALL_FILES): $(MEM_INIT_INSTALL_DIR)/%: $(MEM_INIT_DIR)/%
@$(MKDIR) $(@D)
@$(CP) -v $< $@
$(HDL_SIM_INSTALL_FILES): $(HDL_SIM_INSTALL_DIR)/%: $(HDL_SIM_DIR)/%
@$(MKDIR) $(@D)
@$(CP) -v $< $@
endif # QSYS == 1
mem_init_generate: hex dat sym flash $(MEM_INIT_DESCRIPTOR_FILE) $(MEM_INIT_QIP_FILE)
mem_init_clean:
@$(RM) -r $(MEM_INIT_DIR) $(HDL_SIM_DIR) $(FLASH_FILES)
.PHONY: hex dat sym flash
hex: check_elf_exists $(HEX_FILES)
dat: check_elf_exists $(DAT_FILES)
sym: check_elf_exists $(SYM_FILES)
flash: check_elf_exists $(FLASH_FILES)
#-------------------------------------
# Pre-Initialized Memory Rules
#-------------------------------------
.PHONY: check_elf_exists
check_elf_exists: $(ELF)
ifeq ($(ELF),)
$(error ELF var not set in mem_init.mk)
endif
$(filter-out $(FLASH_DAT_FILES),$(DAT_FILES)): %.dat: $(ELF)
$(post-process-info)
@$(MKDIR) $(@D)
$(ELF2DAT) --infile=$< --outfile=$@ \
--base=$(mem_start_address) --end=$(mem_end_address) --width=$(mem_width) \
$(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2dat_extra_args)
$(foreach i,0 1 2 3 4 5 6 7,%_lane$(i).dat): %.dat
@true
ELF_TO_HEX_CMD_NO_BOOTLOADER = $(ELF2HEX) $< $(mem_start_address) $(mem_end_address) --width=$(mem_hex_width) \
$(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2hex_extra_args) $@
ELF_TO_HEX_CMD_WITH_BOOTLOADER = $(ALT_FILE_CONVERT) -I $(NIOS2_ELF_FORMAT) -O hex --input=$< --output=$@ \
--base=$(mem_start_address) --end=$(mem_end_address) --reset=$(RESET_ADDRESS) \
--out-data-width=$(mem_hex_width) $(flash_mem_boot_loader_flag)
ELF_TO_HEX_CMD = $(strip $(if $(flash_mem_boot_loader_flag), \
$(ELF_TO_HEX_CMD_WITH_BOOTLOADER), \
$(ELF_TO_HEX_CMD_NO_BOOTLOADER) \
))
$(HEX_FILES): %.hex: $(ELF)
$(post-process-info)
@$(MKDIR) $(@D)
$(ELF_TO_HEX_CMD)
$(SYM_FILES): %.sym: $(ELF)
$(post-process-info)
@$(MKDIR) $(@D)
$(NM) -n $< > $@
$(FLASH_FILES): %.flash: $(ELF)
$(post-process-info)
@$(MKDIR) $(@D)
$(ELF2FLASH) --input=$< --outfile=$@ --sim_optimize=$(SIM_OPTIMIZE) $(mem_endianness) \
$(elf2flash_extra_args)
#
# Function generate_spd_entry
# Arg1: path to the memory initialization file
# Arg2: Type HEX or DAT
# Arg3: Output spd file to append
gen_spd_entry.BASE_FILE = $(basename $(notdir $1))
gen_spd_entry.PARAM_NAME = $($(gen_spd_entry.BASE_FILE)_MEM_INIT_FILE_PARAM_NAME)
gen_spd_entry.MEM_PATH = $($(gen_spd_entry.BASE_FILE)_HIERARCHICAL_PATH)
gen_spd_entry.SETTINGS = $(strip \
path=\"$1\" \
type=\"$2\" \
$(if $(gen_spd_entry.PARAM_NAME),initParamName=\"$(gen_spd_entry.PARAM_NAME)\") \
$(if $(gen_spd_entry.MEM_PATH),memoryPath=\"$(gen_spd_entry.MEM_PATH)\") \
)
define gen_spd_entry
$(ECHO) "<file $(gen_spd_entry.SETTINGS) />" >> $3
endef
$(MEM_INIT_DESCRIPTOR_FILE).DAT_FILESET := $(patsubst $(dir $(MEM_INIT_DESCRIPTOR_FILE))%,%,$(DAT_FILES))
$(MEM_INIT_DESCRIPTOR_FILE).HEX_FILESET := $(patsubst $(dir $(MEM_INIT_DESCRIPTOR_FILE))%,%,$(HEX_FILES))
$(MEM_INIT_DESCRIPTOR_FILE): %.spd: $(MEM_INIT_FILE)
$(post-process-info)
@$(MKDIR) $(@D)
@$(RM) $@
@$(ECHO) "<?xml version=\"1.0\" encoding=\"UTF-8\"?>" > $@
@$(ECHO) "<simPackage>" >> $@
@$(foreach dat_file,$($@.DAT_FILESET),$(call gen_spd_entry,$(dat_file),DAT,$@) &&)true
@$(foreach hex_file,$($@.HEX_FILESET),$(call gen_spd_entry,$(hex_file),HEX,$@) &&)true
@$(ECHO) "</simPackage>" >> $@
.DELETE_ON_ERROR: $(MEM_INIT_DESCRIPTOR_FILE)
$(MEM_INIT_QIP_FILE): %.qip: $(MEM_INIT_FILE)
$(post-process-info)
@$(MKDIR) $(@D)
@$(RM) $@
@$(ECHO) "set_global_assignment -name SEARCH_PATH $$::quartus(qip_path)" > $@
.DELETE_ON_ERROR: $(MEM_INIT_QIP_FILE)

50
Top/software/semafor_bsp/memory.gdb Normal file
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# memory.gdb - GDB memory region definitions
#
# Machine generated for CPU 'cpu' in SOPC Builder design 'niosII'
# SOPC Builder design path: ../../niosII.sopcinfo
#
# Generated: Wed Oct 19 15:19:38 MSK 2022
# DO NOT MODIFY THIS FILE
#
# Changing this file will have subtle consequences
# which will almost certainly lead to a nonfunctioning
# system. If you do modify this file, be aware that your
# changes will be overwritten and lost when this file
# is generated again.
#
# DO NOT MODIFY THIS FILE
# License Agreement
#
# Copyright (c) 2008
# Altera Corporation, San Jose, California, USA.
# All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
# DEALINGS IN THE SOFTWARE.
#
# This agreement shall be governed in all respects by the laws of the State
# of California and by the laws of the United States of America.
# Define memory regions for each memory connected to the CPU.
# The cache attribute is specified which improves GDB performance
# by allowing GDB to cache memory contents on the host.
# mem
memory 0x0 0x20000 cache

401
Top/software/semafor_bsp/public.mk Normal file
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#------------------------------------------------------------------------------
# BSP "PUBLIC" MAKEFILE CONTENT
#
# This file is intended to be included in an application or library
# Makefile that is using this BSP. You can create such a Makefile with
# the nios2-app-generate-makefile or nios2-lib-generate-makefile
# commands.
#
# The following variables must be defined before including this file:
#
# ALT_LIBRARY_ROOT_DIR
# Contains the path to the BSP top-level (aka root) directory
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
# PATHS
#------------------------------------------------------------------------------
# Path to the provided linker script.
BSP_LINKER_SCRIPT := $(ALT_LIBRARY_ROOT_DIR)/linker.x
# Include paths:
# The path to root of all header files that a library wishes to make
# available for an application's use is specified here. Note that this
# may not be *all* folders within a hierarchy. For example, if it is
# desired that the application developer type:
# #include <sockets.h>
# #include <ip/tcpip.h>
# With files laid out like this:
# <root of library>/inc/sockets.h
# <root of library>/inc/ip/tcpip.h
#
# Then, only <root of library>/inc need be added to the list of include
# directories. Alternatively, if you wish to be able to directly include
# all files in a hierarchy, separate paths to each folder in that
# hierarchy must be defined.
# The following are the "base" set of include paths for a BSP.
# These paths are appended to the list that individual software
# components, drivers, etc., add in the generated portion of this
# file (below).
ALT_INCLUDE_DIRS_TO_APPEND += \
$(ALT_LIBRARY_ROOT_DIR) \
$(ALT_LIBRARY_ROOT_DIR)/drivers/inc
# Additions to linker library search-path:
# Here we provide a path to "our self" for the application to construct a
# "-L <path to BSP>" out of. This should contain a list of directories,
# relative to the library root, of all directories with .a files to link
# against.
ALT_LIBRARY_DIRS += $(ALT_LIBRARY_ROOT_DIR)
#------------------------------------------------------------------------------
# COMPILATION FLAGS
#------------------------------------------------------------------------------
# Default C pre-processor flags for a BSP:
ALT_CPPFLAGS += -pipe
#------------------------------------------------------------------------------
# MANAGED CONTENT
#
# All content between the lines "START MANAGED" and "END MANAGED" below is
# generated based on variables in the BSP settings file when the
# nios2-bsp-generate-files command is invoked. If you wish to persist any
# information pertaining to the build process, it is recomended that you
# utilize the BSP settings mechanism to do so.
#------------------------------------------------------------------------------
#START MANAGED
# The following TYPE comment allows tools to identify the 'type' of target this
# makefile is associated with.
# TYPE: BSP_PUBLIC_MAKEFILE
# This following VERSION comment indicates the version of the tool used to
# generate this makefile. A makefile variable is provided for VERSION as well.
# ACDS_VERSION: 18.1
ACDS_VERSION := 18.1
# This following BUILD_NUMBER comment indicates the build number of the tool
# used to generate this makefile.
# BUILD_NUMBER: 625
# Qsys--generated SOPCINFO file. Required for resolving node instance ID's with
# design component names.
SOPCINFO_FILE := $(ABS_BSP_ROOT_DIR)/../../niosII.sopcinfo
# Big-Endian operation.
# setting BIG_ENDIAN is false
# BMX present.
# setting BMX is false
# Path to the provided C language runtime initialization code.
BSP_CRT0 := $(ALT_LIBRARY_ROOT_DIR)/obj/HAL/src/crt0.o
# Name of BSP library as provided to linker using the "-msys-lib" flag or
# linker script GROUP command.
# setting BSP_SYS_LIB is hal_bsp
BSP_SYS_LIB := hal_bsp
ELF_PATCH_FLAG += --thread_model hal
# Type identifier of the BSP library
# setting BSP_TYPE is hal
ALT_CPPFLAGS += -D__hal__
BSP_TYPE := hal
# CDX present.
# setting CDX is false
# CPU Name
# setting CPU_NAME is cpu
CPU_NAME = cpu
ELF_PATCH_FLAG += --cpu_name $(CPU_NAME)
# Hardware Divider present.
# setting HARDWARE_DIVIDE is false
ALT_CFLAGS += -mno-hw-div
# Hardware Multiplier present.
# setting HARDWARE_MULTIPLY is false
ALT_CFLAGS += -mno-hw-mul
# Hardware Mulx present.
# setting HARDWARE_MULX is false
ALT_CFLAGS += -mno-hw-mulx
# Debug Core present.
# setting HAS_DEBUG_CORE is true
CPU_HAS_DEBUG_CORE = 1
# Qsys generated design
# setting QSYS is 1
QSYS := 1
ELF_PATCH_FLAG += --qsys true
# Design Name
# setting SOPC_NAME is niosII
SOPC_NAME := niosII
# SopcBuilder Simulation Enabled
# setting SOPC_SIMULATION_ENABLED is false
ELF_PATCH_FLAG += --simulation_enabled false
# Enable JTAG UART driver to recover when host is inactive causing buffer to
# full without returning error. Printf will not fail with this recovery. none
# setting altera_avalon_jtag_uart_driver.enable_jtag_uart_ignore_fifo_full_error is false
# Small-footprint (polled mode) driver none
# setting altera_avalon_jtag_uart_driver.enable_small_driver is false
# Build a custom version of newlib with the specified space-separated compiler
# flags. The custom newlib build will be placed in the <bsp root>/newlib
# directory, and will be used only for applications that utilize this BSP.
# setting hal.custom_newlib_flags is none
# Enable support for a subset of the C++ language. This option increases code
# footprint by adding support for C++ constructors. Certain features, such as
# multiple inheritance and exceptions are not supported. If false, adds
# -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code
# footprint. none
# setting hal.enable_c_plus_plus is true
# When your application exits, close file descriptors, call C++ destructors,
# etc. Code footprint can be reduced by disabling clean exit. If disabled, adds
# -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS -D'exit(a)=_exit(a)' in public.mk. none
# setting hal.enable_clean_exit is true
# Add exit() support. This option increases code footprint if your "main()"
# routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to
# ALT_CPPFLAGS in public.mk, and reduces footprint none
# setting hal.enable_exit is true
# Causes code to be compiled with gprof profiling enabled and the application
# ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to
# ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. none
# setting hal.enable_gprof is false
# Enables lightweight device driver API. This reduces code and data footprint
# by removing the HAL layer that maps device names (e.g. /dev/uart0) to file
# descriptors. Instead, driver routines are called directly. The open(),
# close(), and lseek() routines will always fail if called. The read(),
# write(), fstat(), ioctl(), and isatty() routines only work for the stdio
# devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.
# The Altera Host and read-only ZIP file systems can't be used if
# hal.enable_lightweight_device_driver_api is true.
# setting hal.enable_lightweight_device_driver_api is false
# Adds code to emulate multiply and divide instructions in case they are
# executed but aren't present in the CPU. Normally this isn't required because
# the compiler won't use multiply and divide instructions that aren't present
# in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in
# public.mk. none
# setting hal.enable_mul_div_emulation is false
ALT_CPPFLAGS += -DALT_NO_INSTRUCTION_EMULATION
# Certain drivers are compiled with reduced functionality to reduce code
# footprint. Not all drivers observe this setting. The altera_avalon_uart and
# altera_avalon_jtag_uart drivers switch from interrupt-driven to polled
# operation. CAUTION: Several device drivers are disabled entirely. These
# include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and
# altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash
# access routines) to fail. You can define a symbol provided by each driver to
# prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to
# ALT_CPPFLAGS in public.mk. none
# setting hal.enable_reduced_device_drivers is false
# Turns on HAL runtime stack checking feature. Enabling this setting causes
# additional code to be placed into each subroutine call to generate an
# exception if a stack collision occurs with the heap or statically allocated
# data. If true, adds -DALT_STACK_CHECK and -fstack-limit-register=et to
# ALT_CPPFLAGS in public.mk. none
# setting hal.enable_runtime_stack_checking is false
# The BSP is compiled with optimizations to speedup HDL simulation such as
# initializing the cache, clearing the .bss section, and skipping long delay
# loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. When
# this setting is true, the BSP shouldn't be used to build applications that
# are expected to run real hardware.
# setting hal.enable_sim_optimize is true
ALT_CPPFLAGS += -DALT_SIM_OPTIMIZE
# Causes the small newlib (C library) to be used. This reduces code and data
# footprint at the expense of reduced functionality. Several newlib features
# are removed such as floating-point support in printf(), stdin input routines,
# and buffered I/O. The small C library is not compatible with Micrium
# MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. none
# setting hal.enable_small_c_library is false
# Enable SOPC Builder System ID. If a System ID SOPC Builder component is
# connected to the CPU associated with this BSP, it will be enabled in the
# creation of command-line arguments to download an ELF to the target.
# Otherwise, system ID and timestamp values are left out of public.mk for
# application Makefile "download-elf" target definition. With the system ID
# check disabled, the Nios II EDS tools will not automatically ensure that the
# application .elf file (and BSP it is linked against) corresponds to the
# hardware design on the target. If false, adds --accept-bad-sysid to
# SOPC_SYSID_FLAG in public.mk. none
# setting hal.enable_sopc_sysid_check is true
# C/C++ compiler to generate (do not generate) GP-relative accesses. 'none'
# tells the compilter not to generate GP-relative accesses. 'local' will
# generate GP-relative accesses for small data objects that are not external,
# weak, or uninitialized common symbols. Also use GP-relative addressing for
# objects that have been explicitly placed in a small data section via a
# section attribute. provides the default set of debug symbols typically
# required to debug a typical application. 'global' is same as 'local' but also
# generate GP-relative accesses for small data objects that are external, weak,
# or common. none
# setting hal.make.cflags_mgpopt is -mgpopt=global
ALT_CFLAGS += -mgpopt=global
# Enable BSP generation to query if SOPC system is big endian. If true ignores
# export of 'ALT_CFLAGS += -meb' to public.mk if big endian system. none
# setting hal.make.ignore_system_derived.big_endian is false
# If true, prevents GCC from using BMX instructions. If false, GCC uses BMX
# instructions if present in the CPU. none
# setting hal.make.ignore_system_derived.bmx_present is false
# If true, prevents GCC from using CDX instructions. If false, GCC uses CDX
# instructions if present in the CPU. none
# setting hal.make.ignore_system_derived.cdx_present is false
# Enable BSP generation to query if SOPC system has a debug core present. If
# true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core
# is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if
# no debug core is found in the system. none
# setting hal.make.ignore_system_derived.debug_core_present is false
# Enable BSP generation to query if SOPC system has FPU present. If true
# ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found
# in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU
# is not found in the system. none
# setting hal.make.ignore_system_derived.fpu_present is false
# Enable BSP generation to query if SOPC system has hardware divide present. If
# true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no
# division is found in system. If true ignores export of 'ALT_CFLAGS +=
# -mhw-div' if division is found in the system. none
# setting hal.make.ignore_system_derived.hardware_divide_present is false
# Enable BSP generation to query if SOPC system floating point custom
# instruction with a divider is present. If true ignores export of 'ALT_CFLAGS
# += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to
# public.mk if the custom instruction is found in the system. none
# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present is false
# Enable BSP generation to query if SOPC system floating point custom
# instruction without a divider is present. If true ignores export of
# 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS +=
# -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the
# system. none
# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present is false
# Enable BSP generation to query if SOPC system has multiplier present. If true
# ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier
# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if
# multiplier is found in the system. none
# setting hal.make.ignore_system_derived.hardware_multiplier_present is false
# Enable BSP generation to query if SOPC system has hardware mulx present. If
# true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx
# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx'
# if mulx is found in the system. none
# setting hal.make.ignore_system_derived.hardware_mulx_present is false
# Enable BSP generation to query if SOPC system has simulation enabled. If true
# ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. none
# setting hal.make.ignore_system_derived.sopc_simulation_enabled is false
# Enable BSP generation to query SOPC system for system ID base address. If
# true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and
# 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk. none
# setting hal.make.ignore_system_derived.sopc_system_base_address is false
# Enable BSP generation to query SOPC system for system ID. If true ignores
# export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG +=
# --id=<sysid>' to public.mk. none
# setting hal.make.ignore_system_derived.sopc_system_id is false
# Enable BSP generation to query SOPC system for system timestamp. If true
# ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and
# 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk. none
# setting hal.make.ignore_system_derived.sopc_system_timestamp is false
# Slave descriptor of STDERR character-mode device. This setting is used by the
# ALT_STDERR family of defines in system.h. none
# setting hal.stderr is jtag_uart
ELF_PATCH_FLAG += --stderr_dev jtag_uart
# Slave descriptor of STDIN character-mode device. This setting is used by the
# ALT_STDIN family of defines in system.h. none
# setting hal.stdin is jtag_uart
ELF_PATCH_FLAG += --stdin_dev jtag_uart
# Slave descriptor of STDOUT character-mode device. This setting is used by the
# ALT_STDOUT family of defines in system.h. none
# setting hal.stdout is jtag_uart
ELF_PATCH_FLAG += --stdout_dev jtag_uart
#------------------------------------------------------------------------------
# SOFTWARE COMPONENT & DRIVER INCLUDE PATHS
#------------------------------------------------------------------------------
ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/HAL/inc
#------------------------------------------------------------------------------
# SOFTWARE COMPONENT & DRIVER PRODUCED ALT_CPPFLAGS ADDITIONS
#------------------------------------------------------------------------------
ALT_CPPFLAGS += -DALT_SINGLE_THREADED
#END MANAGED
#------------------------------------------------------------------------------
# LIBRARY INFORMATION
#------------------------------------------------------------------------------
# Assemble the name of the BSP *.a file using the BSP library name
# (BSP_SYS_LIB) in generated content above.
BSP_LIB := lib$(BSP_SYS_LIB).a
# Additional libraries to link against:
# An application including this file will prefix each library with "-l".
# For example, to include the Newlib math library "m" is included, which
# becomes "-lm" when linking the application.
ALT_LIBRARY_NAMES += m
# Additions to linker dependencies:
# An application Makefile will typically add these directly to the list
# of dependencies required to build the executable target(s). The BSP
# library (*.a) file is specified here.
ALT_LDDEPS += $(ALT_LIBRARY_ROOT_DIR)/$(BSP_LIB)
# Is this library "Makeable"?
# Add to list of root library directories that support running 'make'
# to build them. Because libraries may or may not have a Makefile in their
# root, appending to this variable tells an application to run 'make' in
# the library root to build/update this library.
MAKEABLE_LIBRARY_ROOT_DIRS += $(ALT_LIBRARY_ROOT_DIR)
# Additional Assembler Flags
# -gdwarf2 flag is required for stepping through assembly code
ALT_ASFLAGS += -gdwarf2
#------------------------------------------------------------------------------
# FINAL INCLUDE PATH LIST
#------------------------------------------------------------------------------
# Append static include paths to paths specified by OS/driver/sw package
# additions to the BSP thus giving them precedence in case a BSP addition
# is attempting to override BSP sources.
ALT_INCLUDE_DIRS += $(ALT_INCLUDE_DIRS_TO_APPEND)

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<?xml version="1.0" encoding="UTF-8"?>
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>24.10.2022 23:23:55</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1666639435860</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile>
<JdiFile>default</JdiFile>
<Cpu>cpu</Cpu>
<SchemaVersion>1.9</SchemaVersion>
<Setting>
<SettingName>hal.sys_clk_timer</SettingName>
<Identifier>ALT_SYS_CLK</Identifier>
<Type>UnquotedString</Type>
<Value>sys_clk_timer</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>system_h_define</DestinationFile>
<Description>Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.timestamp_timer</SettingName>
<Identifier>ALT_TIMESTAMP_CLK</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>system_h_define</DestinationFile>
<Description>Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.max_file_descriptors</SettingName>
<Identifier>ALT_MAX_FD</Identifier>
<Type>DecimalNumber</Type>
<Value>32</Value>
<DefaultValue>32</DefaultValue>
<DestinationFile>system_h_define</DestinationFile>
<Description>Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h.</Description>
<Restrictions>If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr.</Restrictions>
<Enabled>false</Enabled>
<Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
</Setting>
<Setting>
<SettingName>hal.enable_instruction_related_exceptions_api</SettingName>
<Identifier>ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API</Identifier>
<Type>BooleanDefineOnly</Type>
<Value>true</Value>
<DefaultValue>false</DefaultValue>
<DestinationFile>system_h_define</DestinationFile>
<Description>Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code.</Description>
<Restrictions>These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types.</Restrictions>
<Enabled>false</Enabled>
<Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
</Setting>
<Setting>
<SettingName>hal.linker.allow_code_at_reset</SettingName>
<Identifier>ALT_ALLOW_CODE_AT_RESET</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>none</DestinationFile>
<Description>Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h.</Description>
<Restrictions>If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present.</Restrictions>
<Enabled>false</Enabled>
<Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
</Setting>
<Setting>
<SettingName>hal.linker.enable_alt_load</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>none</DestinationFile>
<Description>Enables the alt_load() facility. The alt_load() facility copies data sections (.rodata, .rwdata, or .exceptions) from boot memory to RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory.</Description>
<Restrictions>This setting is typically false if an external bootloader (e.g. flash bootloader) is present.</Restrictions>
<Enabled>false</Enabled>
<Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
</Setting>
<Setting>
<SettingName>hal.linker.enable_alt_load_copy_rodata</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>none</DestinationFile>
<Description>Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
</Setting>
<Setting>
<SettingName>hal.linker.enable_alt_load_copy_rwdata</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>none</DestinationFile>
<Description>Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
</Setting>
<Setting>
<SettingName>hal.linker.enable_alt_load_copy_exceptions</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>none</DestinationFile>
<Description>Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
</Setting>
<Setting>
<SettingName>hal.linker.enable_exception_stack</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>none</DestinationFile>
<Description>Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x.</Description>
<Restrictions>The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.linker.exception_stack_size</SettingName>
<Identifier>none</Identifier>
<Type>DecimalNumber</Type>
<Value>1024</Value>
<DefaultValue>1024</DefaultValue>
<DestinationFile>none</DestinationFile>
<Description>Size of the exception stack in bytes.</Description>
<Restrictions>Only used if hal.linker.enable_exception_stack is true.</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.linker.exception_stack_memory_region_name</SettingName>
<Identifier>none</Identifier>
<Type>UnquotedString</Type>
<Value>mem</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>none</DestinationFile>
<Description>Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region.</Description>
<Restrictions>Only used if hal.linker.enable_exception_stack is true.</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.linker.enable_interrupt_stack</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>none</DestinationFile>
<Description>Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x.</Description>
<Restrictions>The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.linker.interrupt_stack_size</SettingName>
<Identifier>none</Identifier>
<Type>DecimalNumber</Type>
<Value>1024</Value>
<DefaultValue>1024</DefaultValue>
<DestinationFile>none</DestinationFile>
<Description>Size of the interrupt stack in bytes.</Description>
<Restrictions>Only used if hal.linker.enable_interrupt_stack is true.</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.linker.interrupt_stack_memory_region_name</SettingName>
<Identifier>none</Identifier>
<Type>UnquotedString</Type>
<Value>mem</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>none</DestinationFile>
<Description>Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region.</Description>
<Restrictions>Only used if hal.linker.enable_interrupt_stack is true.</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.stdin</SettingName>
<Identifier>none</Identifier>
<Type>UnquotedString</Type>
<Value>jtag_uart</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>system_h_define</DestinationFile>
<Description>Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.stdout</SettingName>
<Identifier>none</Identifier>
<Type>UnquotedString</Type>
<Value>jtag_uart</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>system_h_define</DestinationFile>
<Description>Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.stderr</SettingName>
<Identifier>none</Identifier>
<Type>UnquotedString</Type>
<Value>jtag_uart</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>system_h_define</DestinationFile>
<Description>Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.log_port</SettingName>
<Identifier>none</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.build_pre_process</SettingName>
<Identifier>BUILD_PRE_PROCESS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Command executed before BSP built.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.ar_pre_process</SettingName>
<Identifier>AR_PRE_PROCESS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Command executed before archiver execution.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.bsp_cflags_defined_symbols</SettingName>
<Identifier>BSP_CFLAGS_DEFINED_SYMBOLS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.ar_post_process</SettingName>
<Identifier>AR_POST_PROCESS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Command executed after archiver execution.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.as</SettingName>
<Identifier>AS</Identifier>
<Type>UnquotedString</Type>
<Value>nios2-elf-gcc</Value>
<DefaultValue>nios2-elf-gcc</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Assembler command. Note that CC is used for .S files.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.build_post_process</SettingName>
<Identifier>BUILD_POST_PROCESS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Command executed after BSP built.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.bsp_cflags_debug</SettingName>
<Identifier>BSP_CFLAGS_DEBUG</Identifier>
<Type>UnquotedString</Type>
<Value>-g</Value>
<DefaultValue>-g</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.make.ar</SettingName>
<Identifier>AR</Identifier>
<Type>UnquotedString</Type>
<Value>nios2-elf-ar</Value>
<DefaultValue>nios2-elf-ar</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Archiver command. Creates library files.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.rm</SettingName>
<Identifier>RM</Identifier>
<Type>UnquotedString</Type>
<Value>rm -f</Value>
<DefaultValue>rm -f</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Command used to remove files during 'clean' target.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.cxx_pre_process</SettingName>
<Identifier>CXX_PRE_PROCESS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Command executed before each C++ file is compiled.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.bsp_cflags_warnings</SettingName>
<Identifier>BSP_CFLAGS_WARNINGS</Identifier>
<Type>UnquotedString</Type>
<Value>-Wall</Value>
<DefaultValue>-Wall</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.bsp_arflags</SettingName>
<Identifier>BSP_ARFLAGS</Identifier>
<Type>UnquotedString</Type>
<Value>-src</Value>
<DefaultValue>-src</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.bsp_cflags_optimization</SettingName>
<Identifier>BSP_CFLAGS_OPTIMIZATION</Identifier>
<Type>UnquotedString</Type>
<Value>-O0</Value>
<DefaultValue>-O0</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.make.as_post_process</SettingName>
<Identifier>AS_POST_PROCESS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Command executed after each assembly file is compiled.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.cc_pre_process</SettingName>
<Identifier>CC_PRE_PROCESS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Command executed before each .c/.S file is compiled.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.bsp_asflags</SettingName>
<Identifier>BSP_ASFLAGS</Identifier>
<Type>UnquotedString</Type>
<Value>-Wa,-gdwarf2</Value>
<DefaultValue>-Wa,-gdwarf2</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.as_pre_process</SettingName>
<Identifier>AS_PRE_PROCESS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Command executed before each assembly file is compiled.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.bsp_cflags_undefined_symbols</SettingName>
<Identifier>BSP_CFLAGS_UNDEFINED_SYMBOLS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.cc_post_process</SettingName>
<Identifier>CC_POST_PROCESS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Command executed after each .c/.S file is compiled.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.cxx_post_process</SettingName>
<Identifier>CXX_POST_PROCESS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Command executed before each C++ file is compiled.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.cc</SettingName>
<Identifier>CC</Identifier>
<Type>UnquotedString</Type>
<Value>nios2-elf-gcc -xc</Value>
<DefaultValue>nios2-elf-gcc -xc</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>C compiler command.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.bsp_cxx_flags</SettingName>
<Identifier>BSP_CXXFLAGS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.bsp_inc_dirs</SettingName>
<Identifier>BSP_INC_DIRS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.cxx</SettingName>
<Identifier>CXX</Identifier>
<Type>UnquotedString</Type>
<Value>nios2-elf-gcc -xc++</Value>
<DefaultValue>nios2-elf-gcc -xc++</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>C++ compiler command.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.bsp_cflags_user_flags</SettingName>
<Identifier>BSP_CFLAGS_USER_FLAGS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>makefile_variable</DestinationFile>
<Description>Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.cflags_mgpopt</SettingName>
<Identifier>CFLAGS_MGPOPT</Identifier>
<Type>UnquotedString</Type>
<Value>-mgpopt=global</Value>
<DefaultValue>-mgpopt=global</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>C/C++ compiler to generate (do not generate) GP-relative accesses. 'none' tells the compilter not to generate GP-relative accesses. 'local' will generate GP-relative accesses for small data objects that are not external, weak, or uninitialized common symbols. Also use GP-relative addressing for objects that have been explicitly placed in a small data section via a section attribute. provides the default set of debug symbols typically required to debug a typical application. 'global' is same as 'local' but also generate GP-relative accesses for small data objects that are external, weak, or common.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.make.ignore_system_derived.sopc_system_id</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=&lt;sysid>' and 'ELF_PATCH_FLAG += --id=&lt;sysid>' to public.mk.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.ignore_system_derived.sopc_system_timestamp</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=&lt;timestamp>' and 'ELF_PATCH_FLAG += --timestamp=&lt;timestamp>' to public.mk.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.ignore_system_derived.sopc_system_base_address</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=&lt;address>' and 'ELF_PATCH_FLAG += --sidp=&lt;address>' to public.mk.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.ignore_system_derived.sopc_simulation_enabled</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.ignore_system_derived.fpu_present</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.ignore_system_derived.cdx_present</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>If true, prevents GCC from using CDX instructions. If false, GCC uses CDX instructions if present in the CPU.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.ignore_system_derived.bmx_present</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>If true, prevents GCC from using BMX instructions. If false, GCC uses BMX instructions if present in the CPU.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.ignore_system_derived.hardware_multiplier_present</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.ignore_system_derived.hardware_mulx_present</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.ignore_system_derived.hardware_divide_present</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.ignore_system_derived.debug_core_present</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.ignore_system_derived.big_endian</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -meb' to public.mk if big endian system.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.enable_exit</SettingName>
<Identifier>ALT_NO_EXIT</Identifier>
<Type>Boolean</Type>
<Value>1</Value>
<DefaultValue>1</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.enable_small_c_library</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.enable_clean_exit</SettingName>
<Identifier>ALT_NO_CLEAN_EXIT</Identifier>
<Type>Boolean</Type>
<Value>1</Value>
<DefaultValue>1</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS -D'exit(a)=_exit(a)' in public.mk.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.enable_runtime_stack_checking</SettingName>
<Identifier>ALT_STACK_CHECK</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -fstack-limit-register=et to ALT_CPPFLAGS in public.mk.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.enable_gprof</SettingName>
<Identifier>ALT_PROVIDE_GMON</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.enable_c_plus_plus</SettingName>
<Identifier>ALT_NO_C_PLUS_PLUS</Identifier>
<Type>Boolean</Type>
<Value>1</Value>
<DefaultValue>1</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.enable_reduced_device_drivers</SettingName>
<Identifier>ALT_USE_SMALL_DRIVERS</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.enable_lightweight_device_driver_api</SettingName>
<Identifier>ALT_USE_DIRECT_DRIVERS</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.</Description>
<Restrictions>The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true.</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.enable_mul_div_emulation</SettingName>
<Identifier>ALT_NO_INSTRUCTION_EMULATION</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.enable_sim_optimize</SettingName>
<Identifier>ALT_SIM_OPTIMIZE</Identifier>
<Type>Boolean</Type>
<Value>1</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk.</Description>
<Restrictions>When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware.</Restrictions>
<Enabled>false</Enabled>
<Group>common</Group>
</Setting>
<Setting>
<SettingName>hal.enable_sopc_sysid_check</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>1</Value>
<DefaultValue>1</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.custom_newlib_flags</SettingName>
<Identifier>CUSTOM_NEWLIB_FLAGS</Identifier>
<Type>UnquotedString</Type>
<Value>none</Value>
<DefaultValue>none</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Build a custom version of newlib with the specified space-separated compiler flags.</Description>
<Restrictions>The custom newlib build will be placed in the &lt;bsp root>/newlib directory, and will be used only for applications that utilize this BSP.</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>hal.log_flags</SettingName>
<Identifier>ALT_LOG_FLAGS</Identifier>
<Type>DecimalNumber</Type>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3.</Description>
<Restrictions>hal.log_port must be set for this to be used.</Restrictions>
<Enabled>false</Enabled>
<Group>none</Group>
</Setting>
<Setting>
<SettingName>altera_avalon_jtag_uart_driver.enable_small_driver</SettingName>
<Identifier>ALTERA_AVALON_JTAG_UART_SMALL</Identifier>
<Type>BooleanDefineOnly</Type>
<Value>false</Value>
<DefaultValue>false</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Small-footprint (polled mode) driver</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
</Setting>
<Setting>
<SettingName>altera_avalon_jtag_uart_driver.enable_jtag_uart_ignore_fifo_full_error</SettingName>
<Identifier>ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR</Identifier>
<Type>BooleanDefineOnly</Type>
<Value>false</Value>
<DefaultValue>false</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>Enable JTAG UART driver to recover when host is inactive causing buffer to full without returning error. Printf will not fail with this recovery.</Description>
<Restrictions>none</Restrictions>
<Enabled>false</Enabled>
<Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
</Setting>
<MemoryMap>
<slaveDescriptor>mem</slaveDescriptor>
<addressRange>0x00000000 - 0x0001FFFF</addressRange>
<addressSpan>131072</addressSpan>
<attributes>memory</attributes>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>sys_clk_timer</slaveDescriptor>
<addressRange>0x00021000 - 0x0002101F</addressRange>
<addressSpan>32</addressSpan>
<attributes>timer</attributes>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>sem_ram_slave</slaveDescriptor>
<addressRange>0x00021020 - 0x0002102F</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>sem_ctl_slave</slaveDescriptor>
<addressRange>0x00021030 - 0x00021037</addressRange>
<addressSpan>8</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>jtag_uart</slaveDescriptor>
<addressRange>0x00021038 - 0x0002103F</addressRange>
<addressSpan>8</addressSpan>
<attributes>printable</attributes>
</MemoryMap>
<LinkerSection>
<sectionName>.text</sectionName>
<regionName>mem</regionName>
</LinkerSection>
<LinkerSection>
<sectionName>.rodata</sectionName>
<regionName>mem</regionName>
</LinkerSection>
<LinkerSection>
<sectionName>.rwdata</sectionName>
<regionName>mem</regionName>
</LinkerSection>
<LinkerSection>
<sectionName>.bss</sectionName>
<regionName>mem</regionName>
</LinkerSection>
<LinkerSection>
<sectionName>.heap</sectionName>
<regionName>mem</regionName>
</LinkerSection>
<LinkerSection>
<sectionName>.stack</sectionName>
<regionName>mem</regionName>
</LinkerSection>
</sch:Settings>

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/*
* system.h - SOPC Builder system and BSP software package information
*
* Machine generated for CPU 'cpu' in SOPC Builder design 'niosII'
* SOPC Builder design path: ../../niosII.sopcinfo
*
* Generated: Mon Oct 24 11:12:11 MSK 2022
*/
/*
* DO NOT MODIFY THIS FILE
*
* Changing this file will have subtle consequences
* which will almost certainly lead to a nonfunctioning
* system. If you do modify this file, be aware that your
* changes will be overwritten and lost when this file
* is generated again.
*
* DO NOT MODIFY THIS FILE
*/
/*
* License Agreement
*
* Copyright (c) 2008
* Altera Corporation, San Jose, California, USA.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This agreement shall be governed in all respects by the laws of the State
* of California and by the laws of the United States of America.
*/
#ifndef __SYSTEM_H_
#define __SYSTEM_H_
/* Include definitions from linker script generator */
#include "linker.h"
/*
* CPU configuration
*
*/
#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"
#define ALT_CPU_BIG_ENDIAN 0
#define ALT_CPU_BREAK_ADDR 0x00020820
#define ALT_CPU_CPU_ARCH_NIOS2_R1
#define ALT_CPU_CPU_FREQ 50000000u
#define ALT_CPU_CPU_ID_SIZE 1
#define ALT_CPU_CPU_ID_VALUE 0x00000000
#define ALT_CPU_CPU_IMPLEMENTATION "tiny"
#define ALT_CPU_DATA_ADDR_WIDTH 0x12
#define ALT_CPU_DCACHE_LINE_SIZE 0
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_DCACHE_SIZE 0
#define ALT_CPU_EXCEPTION_ADDR 0x00000020
#define ALT_CPU_FLASH_ACCELERATOR_LINES 0
#define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
#define ALT_CPU_FLUSHDA_SUPPORTED
#define ALT_CPU_FREQ 50000000
#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0
#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 0
#define ALT_CPU_HARDWARE_MULX_PRESENT 0
#define ALT_CPU_HAS_DEBUG_CORE 1
#define ALT_CPU_HAS_DEBUG_STUB
#define ALT_CPU_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
#define ALT_CPU_HAS_JMPI_INSTRUCTION
#define ALT_CPU_ICACHE_LINE_SIZE 0
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_ICACHE_SIZE 0
#define ALT_CPU_INST_ADDR_WIDTH 0x12
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_OCI_VERSION 1
#define ALT_CPU_RESET_ADDR 0x00000000
/*
* CPU configuration (with legacy prefix - don't use these anymore)
*
*/
#define NIOS2_BIG_ENDIAN 0
#define NIOS2_BREAK_ADDR 0x00020820
#define NIOS2_CPU_ARCH_NIOS2_R1
#define NIOS2_CPU_FREQ 50000000u
#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0x00000000
#define NIOS2_CPU_IMPLEMENTATION "tiny"
#define NIOS2_DATA_ADDR_WIDTH 0x12
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_EXCEPTION_ADDR 0x00000020
#define NIOS2_FLASH_ACCELERATOR_LINES 0
#define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0
#define NIOS2_FLUSHDA_SUPPORTED
#define NIOS2_HARDWARE_DIVIDE_PRESENT 0
#define NIOS2_HARDWARE_MULTIPLY_PRESENT 0
#define NIOS2_HARDWARE_MULX_PRESENT 0
#define NIOS2_HAS_DEBUG_CORE 1
#define NIOS2_HAS_DEBUG_STUB
#define NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
#define NIOS2_HAS_JMPI_INSTRUCTION
#define NIOS2_ICACHE_LINE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE_LOG2 0
#define NIOS2_ICACHE_SIZE 0
#define NIOS2_INST_ADDR_WIDTH 0x12
#define NIOS2_OCI_VERSION 1
#define NIOS2_RESET_ADDR 0x00000000
/*
* Define for each module class mastered by the CPU
*
*/
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_TIMER
#define __ALTERA_NIOS2_GEN2
#define __SEM
/*
* System configuration
*
*/
#define ALT_DEVICE_FAMILY "Cyclone IV E"
#define ALT_ENHANCED_INTERRUPT_API_PRESENT
#define ALT_IRQ_BASE NULL
#define ALT_LOG_PORT "/dev/null"
#define ALT_LOG_PORT_BASE 0x0
#define ALT_LOG_PORT_DEV null
#define ALT_LOG_PORT_TYPE ""
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_BASE 0x21038
#define ALT_STDERR_DEV jtag_uart
#define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_BASE 0x21038
#define ALT_STDIN_DEV jtag_uart
#define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_BASE 0x21038
#define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_SYSTEM_NAME "niosII"
/*
* hal configuration
*
*/
#define ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
#define ALT_MAX_FD 32
#define ALT_SYS_CLK SYS_CLK_TIMER
#define ALT_TIMESTAMP_CLK none
/*
* jtag_uart configuration
*
*/
#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart
#define JTAG_UART_BASE 0x21038
#define JTAG_UART_IRQ 1
#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_SPAN 8
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
/*
* mem configuration
*
*/
#define ALT_MODULE_CLASS_mem altera_avalon_onchip_memory2
#define MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define MEM_BASE 0x0
#define MEM_CONTENTS_INFO ""
#define MEM_DUAL_PORT 1
#define MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define MEM_INIT_CONTENTS_FILE "niosII_mem"
#define MEM_INIT_MEM_CONTENT 1
#define MEM_INSTANCE_ID "NONE"
#define MEM_IRQ -1
#define MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define MEM_NAME "/dev/mem"
#define MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define MEM_RAM_BLOCK_TYPE "AUTO"
#define MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define MEM_SINGLE_CLOCK_OP 1
#define MEM_SIZE_MULTIPLE 1
#define MEM_SIZE_VALUE 131072
#define MEM_SPAN 131072
#define MEM_TYPE "altera_avalon_onchip_memory2"
#define MEM_WRITABLE 1
/*
* sem_ctl_slave configuration
*
*/
#define ALT_MODULE_CLASS_sem_ctl_slave sem
#define SEM_CTL_SLAVE_BASE 0x21030
#define SEM_CTL_SLAVE_IRQ -1
#define SEM_CTL_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SEM_CTL_SLAVE_NAME "/dev/sem_ctl_slave"
#define SEM_CTL_SLAVE_SPAN 8
#define SEM_CTL_SLAVE_TYPE "sem"
/*
* sem_ram_slave configuration
*
*/
#define ALT_MODULE_CLASS_sem_ram_slave sem
#define SEM_RAM_SLAVE_BASE 0x21020
#define SEM_RAM_SLAVE_IRQ -1
#define SEM_RAM_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SEM_RAM_SLAVE_NAME "/dev/sem_ram_slave"
#define SEM_RAM_SLAVE_SPAN 16
#define SEM_RAM_SLAVE_TYPE "sem"
/*
* sys_clk_timer configuration
*
*/
#define ALT_MODULE_CLASS_sys_clk_timer altera_avalon_timer
#define SYS_CLK_TIMER_ALWAYS_RUN 0
#define SYS_CLK_TIMER_BASE 0x21000
#define SYS_CLK_TIMER_COUNTER_SIZE 32
#define SYS_CLK_TIMER_FIXED_PERIOD 0
#define SYS_CLK_TIMER_FREQ 50000000
#define SYS_CLK_TIMER_IRQ 0
#define SYS_CLK_TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0
#define SYS_CLK_TIMER_LOAD_VALUE 49999
#define SYS_CLK_TIMER_MULT 0.001
#define SYS_CLK_TIMER_NAME "/dev/sys_clk_timer"
#define SYS_CLK_TIMER_PERIOD 1
#define SYS_CLK_TIMER_PERIOD_UNITS "ms"
#define SYS_CLK_TIMER_RESET_OUTPUT 0
#define SYS_CLK_TIMER_SNAPSHOT 1
#define SYS_CLK_TIMER_SPAN 32
#define SYS_CLK_TIMER_TICKS_PER_SEC 1000
#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define SYS_CLK_TIMER_TYPE "altera_avalon_timer"
#endif /* __SYSTEM_H_ */