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pt3.12 modelled

This commit is contained in:
Ivan I. Ovchinnikov 2022-10-24 22:35:24 +03:00
parent a5eddcc776
commit f6d43e003a
35 changed files with 21830 additions and 233 deletions
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11
Top/Semafor_hw.tcl
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@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 18.1
# Wed Oct 19 14:56:56 MSK 2022
# Mon Oct 24 17:47:36 MSK 2022
# DO NOT MODIFY
#
# Semafor "Semafor" v1.0
# 2022.10.19.14:56:56
# sem "Semafor" v1.0
# 2022.10.24.17:47:36
#
#
@ -16,10 +16,10 @@ package require -exact qsys 16.1
#
# module Semafor
# module sem
#
set_module_property DESCRIPTION ""
set_module_property NAME Semafor
set_module_property NAME sem
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
@ -44,6 +44,7 @@ add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv TOP_LEVEL_FILE
add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL dec
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv

18
Top/Semafor_hw.tcl~
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@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 18.1
# Wed Oct 19 14:12:17 MSK 2022
# Mon Oct 24 14:36:52 MSK 2022
# DO NOT MODIFY
#
# Semafor "Semafor" v1.0
# 2022.10.19.14:12:17
# sem "Semafor" v1.0
# 2022.10.24.14:36:52
#
#
@ -16,10 +16,10 @@ package require -exact qsys 16.1
#
# module Semafor
# module sem
#
set_module_property DESCRIPTION ""
set_module_property NAME Semafor
set_module_property NAME sem
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
@ -43,6 +43,13 @@ set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv TOP_LEVEL_FILE
add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL dec
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv
add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
#
# parameters
@ -52,6 +59,7 @@ set_parameter_property m DEFAULT_VALUE 8
set_parameter_property m DISPLAY_NAME m
set_parameter_property m TYPE INTEGER
set_parameter_property m UNITS None
set_parameter_property m ALLOWED_RANGES -2147483648:2147483647
set_parameter_property m HDL_PARAMETER true

14
Top/niosII.qsys
View File

@ -73,6 +73,14 @@
type = "String";
}
}
element niosII
{
datum _originalDeviceFamily
{
value = "Cyclone IV E";
type = "String";
}
}
element sem
{
datum _sortIndex
@ -163,7 +171,7 @@
<parameter name="dataAddrWidth" value="18" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='Semafor.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='Semafor.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
@ -346,7 +354,7 @@
version="18.1"
enabled="1">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="autoInitializationFileName" value="niosII_mem" />
<parameter name="autoInitializationFileName" value="$${FILENAME}_mem" />
<parameter name="blockType" value="AUTO" />
<parameter name="copyInitFile" value="false" />
<parameter name="dataWidth" value="32" />
@ -372,7 +380,7 @@
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
</module>
<module name="sem" kind="Semafor" version="1.0" enabled="1">
<module name="sem" kind="sem" version="1.0" enabled="1">
<parameter name="m" value="8" />
</module>
<module

10
Top/niosII.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2022.10.19.14:58:35 -->
<!-- 2022.10.24.18:25:23 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1666177115</value>
<value>1666621523</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
@ -2034,7 +2034,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="dataSlaveMapParam">
<type>java.lang.String</type>
<value><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='Semafor.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='Semafor.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></value>
<value><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
@ -5652,7 +5652,7 @@ parameters are a RESULT of the module parameters. -->
</port>
</interface>
</module>
<module name="sem" kind="Semafor" version="1.0" path="sem">
<module name="sem" kind="sem" version="1.0" path="sem">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
<parameter name="m">
@ -8346,7 +8346,7 @@ parameters are a RESULT of the module parameters. -->
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>Semafor</name>
<name>sem</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Semafor</displayName>

2
Top/niosII/niosII.bsf
View File

@ -75,7 +75,7 @@ refer to the applicable agreement for further details.
(text "red" (rect 117 163 252 336)(font "Arial" (color 0 0 0)))
(text "yellow" (rect 117 179 270 368)(font "Arial" (color 0 0 0)))
(text "green" (rect 117 195 264 400)(font "Arial" (color 0 0 0)))
(text " system " (rect 253 216 554 442)(font "Arial" ))
(text " niosII " (rect 262 216 572 442)(font "Arial" ))
(line (pt 112 32)(pt 176 32)(line_width 1))
(line (pt 176 32)(pt 176 216)(line_width 1))
(line (pt 112 216)(pt 176 216)(line_width 1))

10
Top/niosII/niosII.html
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@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table>
<table class="blueBar">
<tr>
<td class="l">2022.10.19.14:20:53</td>
<td class="l">2022.10.24.17:48:01</td>
<td class="r">Datasheet</td>
</tr>
</table>
@ -101,7 +101,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</a> altera_avalon_onchip_memory2 18.1
<br/>&#160;&#160;
<a href="#module_sem"><b>sem</b>
</a> Semafor 1.0
</a> sem 1.0
<br/>&#160;&#160;
<a href="#module_sys_clk_timer"><b>sys_clk_timer</b>
</a> altera_avalon_timer 18.1</span>
@ -1107,7 +1107,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">dataSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ram_slave' start='0x21020' end='0x21030' type='Semafor.ram_slave' /&gt;&lt;slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='Semafor.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /&gt;&lt;slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
@ -1766,7 +1766,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<a name="module_sem"> </a>
<div>
<hr/>
<h2>sem</h2>Semafor v1.0
<h2>sem</h2>sem v1.0
<br/>
<div class="greydiv">
<table class="connectionboxes">
@ -2039,7 +2039,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table class="blueBar">
<tr>
<td class="l">generation took 0,01 seconds</td>
<td class="r">rendering took 0,11 seconds</td>
<td class="r">rendering took 0,04 seconds</td>
</tr>
</table>
</body>

190
Top/niosII/niosII.xml
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File diff suppressed because one or more lines are too long

12
Top/niosII/synthesis/niosII.debuginfo
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@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="niosII" kind="system" version="18.1" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2022.10.19.14:21:25 -->
<!-- 2022.10.24.17:48:33 -->
<!-- A collection of modules and connections -->
<parameter name="clockCrossingAdapter">
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@ -53,7 +53,7 @@
</parameter>
<parameter name="generationId">
<type>int</type>
<value>1666174853</value>
<value>1666619281</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@ -2110,7 +2110,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="dataSlaveMapParam">
<type>java.lang.String</type>
<value><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='Semafor.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='Semafor.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></value>
<value><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
@ -5673,7 +5673,7 @@ parameters are a RESULT of the module parameters. -->
</port>
</interface>
</module>
<module name="sem" kind="Semafor" version="1.0" path="sem">
<module name="sem" kind="sem" version="1.0" path="sem">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
<parameter name="m">
@ -12830,7 +12830,7 @@ parameters are a RESULT of the module parameters. -->
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>Semafor</name>
<name>sem</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Semafor</displayName>
@ -12925,5 +12925,5 @@ parameters are a RESULT of the module parameters. -->
<version>18.1</version>
</plugin>
<reportVersion>18.1 625</reportVersion>
<uniqueIdentifier>7831C1D0809000000183EFC2B97A</uniqueIdentifier>
<uniqueIdentifier>7A31C1D08890000001840A4024CB</uniqueIdentifier>
</EnsembleReport>

8
Top/niosII/synthesis/niosII.qip
View File

@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1"
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"]
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1666174853"
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1666619281"
set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"]
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"]
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"]
@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY2NjE3NDg1Mw==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY2NjYxOTI4MQ==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U="
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@ -859,7 +859,7 @@ set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdTZW1hZm9yLnJhbV9zbGF2ZScgLz48c2xhdmUgbmFtZT0nc2VtLmN0bF9zbGF2ZScgc3RhcnQ9JzB4MjEwMzAnIGVuZD0nMHgyMTAzOCcgdHlwZT0nU2VtYWZvci5jdGxfc2xhdmUnIC8+PHNsYXZlIG5hbWU9J2p0YWdfdWFydC5hdmFsb25fanRhZ19zbGF2ZScgc3RhcnQ9JzB4MjEwMzgnIGVuZD0nMHgyMTA0MCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9qdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIC8+PC9hZGRyZXNzLW1hcD4=::ZGF0YVNsYXZlTWFwUGFyYW0="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTAzMCcgZW5kPScweDIxMDM4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDM4JyBlbmQ9JzB4MjEwNDAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ=="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="
@ -1042,7 +1042,7 @@ set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPON
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdTZW1hZm9yLnJhbV9zbGF2ZScgLz48c2xhdmUgbmFtZT0nc2VtLmN0bF9zbGF2ZScgc3RhcnQ9JzB4MjEwMzAnIGVuZD0nMHgyMTAzOCcgdHlwZT0nU2VtYWZvci5jdGxfc2xhdmUnIC8+PHNsYXZlIG5hbWU9J2p0YWdfdWFydC5hdmFsb25fanRhZ19zbGF2ZScgc3RhcnQ9JzB4MjEwMzgnIGVuZD0nMHgyMTA0MCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9qdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIC8+PC9hZGRyZXNzLW1hcD4=::ZGF0YVNsYXZlTWFwUGFyYW0="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTAzMCcgZW5kPScweDIxMDM4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDM4JyBlbmQ9JzB4MjEwNDAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ=="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="

2
Top/niosII/testbench/mentor/msim_setup.tcl
View File

@ -94,7 +94,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 win32 2022.10.19.14:59:25
# ACDS 18.1 625 win32 2022.10.24.18:26:02
# ----------------------------------------
# Initialize variables

12
Top/niosII/testbench/niosII.html
View File

@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table>
<table class="blueBar">
<tr>
<td class="l">2022.10.19.14:58:35</td>
<td class="l">2022.10.24.18:25:23</td>
<td class="r">Datasheet</td>
</tr>
</table>
@ -101,7 +101,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</a> altera_avalon_onchip_memory2 18.1
<br/>&#160;&#160;
<a href="#module_sem"><b>sem</b>
</a> Semafor 1.0
</a> sem 1.0
<br/>&#160;&#160;
<a href="#module_sys_clk_timer"><b>sys_clk_timer</b>
</a> altera_avalon_timer 18.1</span>
@ -1107,7 +1107,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">dataSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ram_slave' start='0x21020' end='0x21030' type='Semafor.ram_slave' /&gt;&lt;slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='Semafor.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /&gt;&lt;slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
@ -1766,7 +1766,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<a name="module_sem"> </a>
<div>
<hr/>
<h2>sem</h2>Semafor v1.0
<h2>sem</h2>sem v1.0
<br/>
<div class="greydiv">
<table class="connectionboxes">
@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0,02 seconds</td>
<td class="r">rendering took 0,09 seconds</td>
<td class="l">generation took 0,00 seconds</td>
<td class="r">rendering took 0,04 seconds</td>
</tr>
</table>
</body>

12
Top/niosII/testbench/niosII_tb.html
View File

@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table>
<table class="blueBar">
<tr>
<td class="l">2022.10.19.14:58:47</td>
<td class="l">2022.10.24.18:25:32</td>
<td class="r">Datasheet</td>
</tr>
</table>
@ -101,7 +101,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</a> altera_avalon_onchip_memory2 18.1
<br/>&#160;&#160;
<a href="#module_niosII_inst_sem"><b>niosII_inst_sem</b>
</a> Semafor 1.0
</a> sem 1.0
<br/>&#160;&#160;
<a href="#module_niosII_inst_sys_clk_timer"><b>niosII_inst_sys_clk_timer</b>
</a> altera_avalon_timer 18.1</span>
@ -211,7 +211,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table>
<tr>
<td class="parametername">AUTO_GENERATION_ID</td>
<td class="parametervalue">1666177126</td>
<td class="parametervalue">1666621532</td>
</tr>
<tr>
<td class="parametername">AUTO_UNIQUE_ID</td>
@ -1323,7 +1323,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">dataSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ram_slave' start='0x21020' end='0x21030' type='Semafor.ram_slave' /&gt;&lt;slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='Semafor.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /&gt;&lt;slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
@ -1982,7 +1982,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<a name="module_niosII_inst_sem"> </a>
<div>
<hr/>
<h2>niosII_inst_sem</h2>Semafor v1.0
<h2>niosII_inst_sem</h2>sem v1.0
<br/>
<div class="greydiv">
<table class="connectionboxes">
@ -2360,7 +2360,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table class="blueBar">
<tr>
<td class="l">generation took 0,00 seconds</td>
<td class="r">rendering took 0,08 seconds</td>
<td class="r">rendering took 0,05 seconds</td>
</tr>
</table>
</body>

4
Top/niosII/testbench/synopsys/vcs/vcs_setup.sh
View File

@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 18.1 625 win32 2022.10.19.14:59:25
# ACDS 18.1 625 win32 2022.10.24.18:26:02
# ----------------------------------------
# vcs - auto-generated simulation script
@ -94,7 +94,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 win32 2022.10.19.14:59:25
# ACDS 18.1 625 win32 2022.10.24.18:26:02
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="niosII_tb"

4
Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh
View File

@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 18.1 625 win32 2022.10.19.14:59:25
# ACDS 18.1 625 win32 2022.10.24.18:26:03
# ----------------------------------------
# vcsmx - auto-generated simulation script
@ -107,7 +107,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 win32 2022.10.19.14:59:25
# ACDS 18.1 625 win32 2022.10.24.18:26:03
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="niosII_tb"

12
Top/niosII_tb.csv
View File

@ -1,12 +1,12 @@
# system info niosII_tb on 2022.10.19.14:59:23
# system info niosII_tb on 2022.10.24.18:26:01
system_info:
name,value
DEVICE,EP4CE115F29C7
DEVICE_FAMILY,Cyclone IV E
GENERATION_ID,1666177126
GENERATION_ID,1666621532
#
#
# Files generated for niosII_tb on 2022.10.19.14:59:23
# Files generated for niosII_tb on 2022.10.24.18:26:01
files:
filepath,kind,attributes,module,is_top
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
@ -19,8 +19,8 @@ niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v,VERILOG,,niosII_cp
niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false
niosII/testbench/niosII_tb/simulation/submodules/dec.sv,SYSTEM_VERILOG,,niosII_sem,false
niosII/testbench/niosII_tb/simulation/submodules/periodram.v,VERILOG,,niosII_sem,false
niosII/testbench/niosII_tb/simulation/submodules/dec.sv,SYSTEM_VERILOG,,dec,false
niosII/testbench/niosII_tb/simulation/submodules/periodram.v,VERILOG,,dec,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v,VERILOG,,niosII_sys_clk_timer,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v,VERILOG,,niosII_mm_interconnect_0,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VERILOG,,niosII_irq_mapper,false
@ -76,7 +76,7 @@ niosII_tb.niosII_inst.cpu,niosII_cpu
niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu
niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart
niosII_tb.niosII_inst.mem,niosII_mem
niosII_tb.niosII_inst.sem,niosII_sem
niosII_tb.niosII_inst.sem,dec
niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer
niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0
niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_translator,altera_merlin_master_translator

1 # system info niosII_tb on 2022.10.19.14:59:23 # system info niosII_tb on 2022.10.24.18:26:01
2 system_info: system_info:
3 name,value name,value
4 DEVICE,EP4CE115F29C7 DEVICE,EP4CE115F29C7
5 DEVICE_FAMILY,Cyclone IV E DEVICE_FAMILY,Cyclone IV E
6 GENERATION_ID,1666177126 GENERATION_ID,1666621532
7 # #
8 # #
9 # Files generated for niosII_tb on 2022.10.19.14:59:23 # Files generated for niosII_tb on 2022.10.24.18:26:01
10 files: files:
11 filepath,kind,attributes,module,is_top filepath,kind,attributes,module,is_top
12 niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
19 niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false
20 niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false
21 niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false
22 niosII/testbench/niosII_tb/simulation/submodules/dec.sv,SYSTEM_VERILOG,,niosII_sem,false niosII/testbench/niosII_tb/simulation/submodules/dec.sv,SYSTEM_VERILOG,,dec,false
23 niosII/testbench/niosII_tb/simulation/submodules/periodram.v,VERILOG,,niosII_sem,false niosII/testbench/niosII_tb/simulation/submodules/periodram.v,VERILOG,,dec,false
24 niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v,VERILOG,,niosII_sys_clk_timer,false niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v,VERILOG,,niosII_sys_clk_timer,false
25 niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v,VERILOG,,niosII_mm_interconnect_0,false niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v,VERILOG,,niosII_mm_interconnect_0,false
26 niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VERILOG,,niosII_irq_mapper,false niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VERILOG,,niosII_irq_mapper,false
76 niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu
77 niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart
78 niosII_tb.niosII_inst.mem,niosII_mem niosII_tb.niosII_inst.mem,niosII_mem
79 niosII_tb.niosII_inst.sem,niosII_sem niosII_tb.niosII_inst.sem,dec
80 niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer
81 niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0 niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0
82 niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_translator,altera_merlin_master_translator niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_translator,altera_merlin_master_translator

4
Top/semafor.qsf
View File

@ -53,7 +53,7 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_
set_global_assignment -name QSYS_FILE niosII.qsys
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

2
Top/software/semafor/.settings/language.settings.xml
View File

@ -6,7 +6,7 @@
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
<provider copy-of="extension" id="altera.tool.Nios2GCCBuildCommandParser"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="altera.tool.Nios2GCCBuildCommandParser" keep-relative-paths="false" name="Nios II GCC Build Output Parser" parameter="(nios2-elf-gcc)|(nios2-elf-g\+\+)" prefer-non-shared="true"/>
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>

BIN
Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf Normal file
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Binary file not shown.

1645
Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.map Normal file
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File diff suppressed because it is too large Load Diff

8377
Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump Normal file
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File diff suppressed because it is too large Load Diff

7332
Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat Normal file
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File diff suppressed because it is too large Load Diff

169
Top/software/semafor/mem_init/hdl_sim/niosII_mem.sym Normal file
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@ -0,0 +1,169 @@
00000000 A __alt_mem_mem
00000000 T __reset
00000020 T alt_exception
00000020 T alt_irq_entry
000000fc T alt_irq_handler
000001d0 T alt_instruction_exception_entry
00000230 T _start
00000244 t alt_after_alt_main
00000248 T main
00000330 T _puts_r
000003f0 T puts
00000404 T strlen
0000049c t __fp_unlock
000004a4 T _cleanup_r
000004b0 t __sinit.part.1
0000064c t __fp_lock
00000654 T __sfmoreglue
000006cc T __sfp
000007e4 T _cleanup
000007fc T __sinit
0000080c T __sfp_lock_acquire
00000810 T __sfp_lock_release
00000814 T __sinit_lock_acquire
00000818 T __sinit_lock_release
0000081c T __fp_lock_all
00000834 T __fp_unlock_all
0000084c T __sfvwrite_r
00000d14 T _fwalk
00000dd8 T _fwalk_reent
00000e9c T _malloc_r
000016a8 T memchr
0000178c T memcpy
000018d4 T memmove
00001a30 T memset
00001b58 T _realloc_r
000020bc T _sbrk_r
00002110 T __sread
00002164 T __seofread
0000216c T __swrite
000021e8 T __sseek
00002244 T __sclose
0000224c T _write_r
000022ac T __swsetup_r
00002400 T _close_r
00002454 T _fclose_r
00002544 T fclose
00002558 T __sflush_r
00002774 T _fflush_r
000027d0 T fflush
00002800 T _malloc_trim_r
00002924 T _free_r
00002c34 T _lseek_r
00002c94 T __smakebuf_r
00002e50 T _read_r
00002eb0 T _fstat_r
00002f0c T _isatty_r
00002f60 T __divsi3
00002fe4 T __modsi3
00003058 T __udivsi3
000030bc T __umodsi3
00003114 T __mulsi3
0000313c t alt_get_errno
00003178 T close
00003250 T alt_dcache_flush
00003278 t alt_dev_null_write
000032a4 t alt_get_errno
000032e0 T fstat
00003398 t alt_get_errno
000033d4 T isatty
00003480 t alt_get_errno
000034bc T lseek
00003598 T alt_main
00003614 T __malloc_lock
00003638 T __malloc_unlock
0000365c t alt_get_errno
00003698 T read
0000379c T alt_release_fd
00003820 T sbrk
000038d0 t alt_get_errno
0000390c T write
00003a0c t alt_dev_reg
00003a40 T alt_irq_init
00003a78 T alt_sys_init
00003ad8 T altera_avalon_jtag_uart_read_fd
00003b38 T altera_avalon_jtag_uart_write_fd
00003b98 T altera_avalon_jtag_uart_close_fd
00003be8 T altera_avalon_jtag_uart_ioctl_fd
00003c3c T altera_avalon_jtag_uart_init
00003cfc t altera_avalon_jtag_uart_irq
00003f08 t altera_avalon_jtag_uart_timeout
00003fa8 T altera_avalon_jtag_uart_close
00004010 T altera_avalon_jtag_uart_ioctl
00004100 T altera_avalon_jtag_uart_read
0000431c T altera_avalon_jtag_uart_write
00004540 t alt_avalon_timer_sc_irq
000045b8 T alt_avalon_timer_sc_init
00004634 T alt_alarm_start
00004760 t alt_get_errno
0000479c T alt_dev_llist_insert
00004840 T _do_ctors
000048a0 T _do_dtors
00004900 T alt_ic_isr_register
00004950 T alt_ic_irq_enable
000049d8 T alt_ic_irq_disable
00004a64 T alt_ic_irq_enabled
00004ab0 T alt_iic_isr_register
00004ba0 t alt_open_fd
00004c84 T alt_io_redirect
00004d00 t alt_get_errno
00004d3c t alt_file_locked
00004e28 T open
00004f84 T alt_alarm_stop
00005020 T alt_tick
00005128 T altera_nios2_gen2_irq_init
0000514c T alt_find_dev
000051dc T alt_find_file
000052e4 T alt_get_fd
000053a8 T alt_exception_cause_generated_bad_addr
00005444 T atexit
00005458 T exit
00005490 T memcmp
0000550c T __register_exitproc
00005624 T __call_exitprocs
000057a4 T _exit
000057d8 A __CTOR_END__
000057d8 A __CTOR_LIST__
000057d8 A __DTOR_END__
000057d8 A __DTOR_LIST__
000057d8 R divisors
00005824 g impure_data
00005c48 G __malloc_av_
00006050 G alt_dev_null
00006078 G alt_fd_list
000061f8 g jtag_uart
00007258 G _global_impure_ptr
0000725c G _impure_ptr
00007260 G __malloc_sbrk_base
00007264 G __malloc_trim_threshold
00007268 G alt_fs_list
00007270 G alt_dev_list
00007278 G alt_max_fd
0000727c G alt_errno
00007280 g heap_end
00007284 G alt_priority_mask
00007288 G alt_alarm_list
00007290 A __bss_start
00007290 B __malloc_max_total_mem
00007290 A _edata
00007294 B __malloc_max_sbrked_mem
00007298 B __malloc_top_pad
0000729c B errno
000072a0 B alt_argc
000072a4 B alt_argv
000072a8 B alt_envp
000072ac B alt_irq_active
000072b0 B _alt_tick_rate
000072b4 B _alt_nticks
000072b8 B alt_instruction_exception_handler
000072bc B __malloc_current_mallinfo
000072e4 B alt_irq
000073e4 A __alt_heap_start
000073e4 A __alt_stack_base
000073e4 A __bss_end
000073e4 A _end
000073e4 A end
0000f258 A _gp
00020000 A __alt_data_end
00020000 A __alt_heap_limit
00020000 A __alt_stack_pointer

1
Top/software/semafor/mem_init/meminit.qip Normal file
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@ -0,0 +1 @@
set_global_assignment -name SEARCH_PATH $::quartus(qip_path)

5
Top/software/semafor/mem_init/meminit.spd Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file path="hdl_sim/niosII_mem.dat" type="DAT" initParamName="INIT_FILE" memoryPath="mem" />
<file path="niosII_mem.hex" type="HEX" initParamName="INIT_FILE" memoryPath="mem" />
</simPackage>

4098
Top/software/semafor/mem_init/niosII_mem.hex Normal file
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File diff suppressed because it is too large Load Diff

1
Top/software/semafor/transcript Normal file
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@ -0,0 +1 @@
# Reading C:/Software/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl

2
Top/software/semafor_bsp/.settings/language.settings.xml
View File

@ -6,7 +6,7 @@
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
<provider copy-of="extension" id="altera.tool.Nios2GCCBuildCommandParser"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="altera.tool.Nios2GCCBuildCommandParser" keep-relative-paths="false" name="Nios II GCC Build Output Parser" parameter="(nios2-elf-gcc)|(nios2-elf-g\+\+)" prefer-non-shared="true"/>
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>

BIN
Top/software/semafor_bsp/libhal_bsp.a Normal file
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18
Top/software/semafor_bsp/linker.h
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@ -4,7 +4,7 @@
* Machine generated for CPU 'cpu' in SOPC Builder design 'niosII'
* SOPC Builder design path: ../../niosII.sopcinfo
*
* Generated: Wed Oct 19 15:19:38 MSK 2022
* Generated: Wed Oct 19 16:14:31 MSK 2022
*/
/*
@ -82,20 +82,4 @@
#define ALT_RWDATA_DEVICE MEM
#define ALT_TEXT_DEVICE MEM
/*
* Initialization code at the reset address is allowed (e.g. no external bootloader).
*
*/
#define ALT_ALLOW_CODE_AT_RESET
/*
* The alt_load() facility is called from crt0 to copy sections into RAM.
*
*/
#define ALT_LOAD_COPY_RWDATA
#endif /* __LINKER_H_ */

47
Top/software/semafor_bsp/linker.x
View File

@ -4,7 +4,7 @@
* Machine generated for CPU 'cpu' in SOPC Builder design 'niosII'
* SOPC Builder design path: ../../niosII.sopcinfo
*
* Generated: Wed Oct 19 15:19:38 MSK 2022
* Generated: Wed Oct 19 16:14:31 MSK 2022
*/
/*
@ -64,12 +64,9 @@ OUTPUT_ARCH( nios2 )
ENTRY( _start )
/*
* The alt_load() facility is enabled. This typically happens when there isn't
* an external bootloader (e.g. flash bootloader).
* The LMA (aka physical address) of each loaded section is
* set to the .text memory device.
* The HAL alt_load() routine called from crt0 copies sections from
* the .text memory to RAM as needed.
* The alt_load() facility is disabled. This typically happens when an
* external bootloader is provided or the application runs in place.
* The LMA (aka physical address) of each section defaults to its VMA.
*/
SECTIONS
@ -221,18 +218,7 @@ SECTIONS
PROVIDE (__flash_rodata_start = LOADADDR(.rodata));
/*
*
* This section's LMA is set to the .text region.
* crt0 will copy to this section's specified mapped region virtual memory address (VMA)
*
* .rwdata region equals the .text region, and is set to be loaded into .text region.
* This requires two copies of .rwdata in the .text region. One read writable at VMA.
* and one read-only at LMA. crt0 will copy from LMA to VMA on reset
*
*/
.rwdata LOADADDR (.rodata) + SIZEOF (.rodata) : AT ( LOADADDR (.rodata) + SIZEOF (.rodata)+ SIZEOF (.rwdata) )
.rwdata :
{
PROVIDE (__ram_rwdata_start = ABSOLUTE(.));
. = ALIGN(4);
@ -255,14 +241,7 @@ SECTIONS
PROVIDE (__flash_rwdata_start = LOADADDR(.rwdata));
/*
*
* This section's LMA is set to the .text region.
* crt0 will copy to this section's specified mapped region virtual memory address (VMA)
*
*/
.bss LOADADDR (.rwdata) + SIZEOF (.rwdata) : AT ( LOADADDR (.rwdata) + SIZEOF (.rwdata) )
.bss :
{
__bss_start = ABSOLUTE(.);
PROVIDE (__sbss_start = ABSOLUTE(.));
@ -293,21 +272,9 @@ SECTIONS
* The output section used for the heap is treated in a special way,
* i.e. the symbols "end" and "_end" are added to point to the heap start.
*
* Because alt_load() is enabled, these sections have
* their LMA set to be loaded into the .text memory region.
* However, the alt_load() code will NOT automatically copy
* these sections into their mapped memory region.
*
*/
/*
*
* This section's LMA is set to the .text region.
* crt0 will copy to this section's specified mapped region virtual memory address (VMA)
*
*/
.mem LOADADDR (.bss) + SIZEOF (.bss) : AT ( LOADADDR (.bss) + SIZEOF (.bss) )
.mem :
{
PROVIDE (_alt_partition_mem_start = ABSOLUTE(.));
*(.mem .mem. mem.*)

2
Top/software/semafor_bsp/mem_init.mk
View File

@ -158,7 +158,7 @@ ACDS_VERSION := 18.1
# BUILD_NUMBER: 625
# Optimize for simulation
SIM_OPTIMIZE ?= 0
SIM_OPTIMIZE ?= 1
# The CPU reset address as needed by elf2flash
RESET_ADDRESS ?= 0x00000000

3
Top/software/semafor_bsp/public.mk
View File

@ -221,7 +221,8 @@ ALT_CPPFLAGS += -DALT_NO_INSTRUCTION_EMULATION
# loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. When
# this setting is true, the BSP shouldn't be used to build applications that
# are expected to run real hardware.
# setting hal.enable_sim_optimize is false
# setting hal.enable_sim_optimize is true
ALT_CPPFLAGS += -DALT_SIM_OPTIMIZE
# Causes the small newlib (C library) to be used. This reduces code and data
# footprint at the expense of reduced functionality. Several newlib features

12
Top/software/semafor_bsp/settings.bsp
View File

@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>19.10.2022 15:24:36</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1666178676551</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>24.10.2022 23:23:55</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1666639435860</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile>
@ -62,7 +62,7 @@
<SettingName>hal.linker.allow_code_at_reset</SettingName>
<Identifier>ALT_ALLOW_CODE_AT_RESET</Identifier>
<Type>Boolean</Type>
<Value>1</Value>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>none</DestinationFile>
<Description>Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h.</Description>
@ -74,7 +74,7 @@
<SettingName>hal.linker.enable_alt_load</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>1</Value>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>none</DestinationFile>
<Description>Enables the alt_load() facility. The alt_load() facility copies data sections (.rodata, .rwdata, or .exceptions) from boot memory to RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory.</Description>
@ -98,7 +98,7 @@
<SettingName>hal.linker.enable_alt_load_copy_rwdata</SettingName>
<Identifier>none</Identifier>
<Type>Boolean</Type>
<Value>1</Value>
<Value>0</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>none</DestinationFile>
<Description>Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h.</Description>
@ -830,7 +830,7 @@
<SettingName>hal.enable_sim_optimize</SettingName>
<Identifier>ALT_SIM_OPTIMIZE</Identifier>
<Type>Boolean</Type>
<Value>0</Value>
<Value>1</Value>
<DefaultValue>0</DefaultValue>
<DestinationFile>public_mk_define</DestinationFile>
<Description>The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk.</Description>

12
Top/software/semafor_bsp/summary.html
View File

@ -22,10 +22,10 @@
<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>19.10.2022 15:24:36</td>
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>24.10.2022 23:23:55</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1666178676551</td>
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1666639435860</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td>
@ -423,7 +423,7 @@
<td width="20%">Default Value:</td><td>0</td>
</tr>
<tr>
<td width="20%">Value:</td><td>0</td>
<td width="20%">Value:</td><td>1</td>
</tr>
<tr>
<td width="20%">Type:</td><td>Boolean</td>
@ -504,7 +504,7 @@
<td width="20%">Default Value:</td><td>0</td>
</tr>
<tr>
<td width="20%">Value:</td><td>1</td>
<td width="20%">Value:</td><td>0</td>
</tr>
<tr>
<td width="20%">Type:</td><td>Boolean</td>
@ -531,7 +531,7 @@
<td width="20%">Default Value:</td><td>0</td>
</tr>
<tr>
<td width="20%">Value:</td><td>1</td>
<td width="20%">Value:</td><td>0</td>
</tr>
<tr>
<td width="20%">Type:</td><td>Boolean</td>
@ -612,7 +612,7 @@
<td width="20%">Default Value:</td><td>0</td>
</tr>
<tr>
<td width="20%">Value:</td><td>1</td>
<td width="20%">Value:</td><td>0</td>
</tr>
<tr>
<td width="20%">Type:</td><td>Boolean</td>

12
Top/software/semafor_bsp/system.h
View File

@ -4,7 +4,7 @@
* Machine generated for CPU 'cpu' in SOPC Builder design 'niosII'
* SOPC Builder design path: ../../niosII.sopcinfo
*
* Generated: Wed Oct 19 15:19:38 MSK 2022
* Generated: Mon Oct 24 11:12:11 MSK 2022
*/
/*
@ -137,7 +137,7 @@
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_TIMER
#define __ALTERA_NIOS2_GEN2
#define __SEMAFOR
#define __SEM
/*
@ -239,13 +239,13 @@
*
*/
#define ALT_MODULE_CLASS_sem_ctl_slave Semafor
#define ALT_MODULE_CLASS_sem_ctl_slave sem
#define SEM_CTL_SLAVE_BASE 0x21030
#define SEM_CTL_SLAVE_IRQ -1
#define SEM_CTL_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SEM_CTL_SLAVE_NAME "/dev/sem_ctl_slave"
#define SEM_CTL_SLAVE_SPAN 8
#define SEM_CTL_SLAVE_TYPE "Semafor"
#define SEM_CTL_SLAVE_TYPE "sem"
/*
@ -253,13 +253,13 @@
*
*/
#define ALT_MODULE_CLASS_sem_ram_slave Semafor
#define ALT_MODULE_CLASS_sem_ram_slave sem
#define SEM_RAM_SLAVE_BASE 0x21020
#define SEM_RAM_SLAVE_IRQ -1
#define SEM_RAM_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SEM_RAM_SLAVE_NAME "/dev/sem_ram_slave"
#define SEM_RAM_SLAVE_SPAN 16
#define SEM_RAM_SLAVE_TYPE "Semafor"
#define SEM_RAM_SLAVE_TYPE "sem"
/*