fpga-lab-2/Top/niosII_tb.spd

237 lines
8.3 KiB
XML

<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file
path="niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv"
type="SYSTEM_VERILOG"
library="altera_common_sv_packages"
systemVerilogPackageName="avalon_vip_verbosity_pkg" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
type="SYSTEM_VERILOG"
library="error_adapter_0" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v"
type="VERILOG"
library="avalon_st_adapter" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv"
type="SYSTEM_VERILOG"
library="rsp_mux_001" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
library="rsp_mux_001" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv"
type="SYSTEM_VERILOG"
library="rsp_mux" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
library="rsp_mux" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv"
type="SYSTEM_VERILOG"
library="rsp_demux" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv"
type="SYSTEM_VERILOG"
library="cmd_mux_002" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
library="cmd_mux_002" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv"
type="SYSTEM_VERILOG"
library="cmd_mux" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
library="cmd_mux" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv"
type="SYSTEM_VERILOG"
library="cmd_demux_001" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv"
type="SYSTEM_VERILOG"
library="cmd_demux" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv"
type="SYSTEM_VERILOG"
library="router_008" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv"
type="SYSTEM_VERILOG"
library="router_004" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv"
type="SYSTEM_VERILOG"
library="router_002" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv"
type="SYSTEM_VERILOG"
library="router_001" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv"
type="SYSTEM_VERILOG"
library="router" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v"
type="VERILOG"
library="jtag_uart_avalon_jtag_slave_agent_rsp_fifo" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv"
type="SYSTEM_VERILOG"
library="jtag_uart_avalon_jtag_slave_agent" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv"
type="SYSTEM_VERILOG"
library="jtag_uart_avalon_jtag_slave_agent" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv"
type="SYSTEM_VERILOG"
library="cpu_data_master_agent" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv"
type="SYSTEM_VERILOG"
library="jtag_uart_avalon_jtag_slave_translator" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv"
type="SYSTEM_VERILOG"
library="cpu_data_master_translator" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat"
type="DAT"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat"
type="DAT"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif"
type="MIF"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat"
type="DAT"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do"
type="OTHER"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex"
type="HEX"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif"
type="MIF"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc"
type="SDC"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex"
type="HEX"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif"
type="MIF"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex"
type="HEX"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v"
type="VERILOG"
library="rst_controller" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v"
type="VERILOG"
library="rst_controller" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc"
type="SDC"
library="rst_controller" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv"
type="SYSTEM_VERILOG"
library="irq_mapper" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v"
type="VERILOG"
library="mm_interconnect_0" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v"
type="VERILOG"
library="sys_clk_timer" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/dec.sv"
type="SYSTEM_VERILOG"
library="sem" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/periodram.v"
type="VERILOG"
library="sem" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex"
type="HEX"
library="mem" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v"
type="VERILOG"
library="mem" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v"
type="VERILOG"
library="jtag_uart" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv"
type="SYSTEM_VERILOG"
library="niosII_inst_reset_bfm" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv"
type="SYSTEM_VERILOG"
library="niosII_inst_clk_bfm" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII.v"
type="VERILOG"
library="niosII_inst" />
<file
path="niosII/testbench/niosII_tb/simulation/niosII_tb.v"
type="VERILOG" />
<topLevel name="niosII_tb" />
<deviceFamily name="cycloneive" />
<modelMap
controllerPath="niosII_tb.niosII_inst.mem"
modelPath="niosII_tb.niosII_inst.mem" />
</simPackage>