304 lines
11 KiB
Systemverilog
304 lines
11 KiB
Systemverilog
// (C) 2001-2018 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $
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// $Revision: #1 $
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// $Date: 2018/07/18 $
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// $Author: psgswbuild $
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// --------------------------------------
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// Merlin Master Agent
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//
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// Converts Avalon-MM transactions into
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// Merlin network packets.
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// --------------------------------------
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`timescale 1 ns / 1 ns
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module altera_merlin_master_agent
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#(
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// -------------------
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// Packet Format Parameters
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// -------------------
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parameter
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PKT_QOS_H = 109,
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PKT_QOS_L = 106,
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PKT_DATA_SIDEBAND_H = 105,
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PKT_DATA_SIDEBAND_L = 98,
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PKT_ADDR_SIDEBAND_H = 97,
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PKT_ADDR_SIDEBAND_L = 93,
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PKT_CACHE_H = 92,
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PKT_CACHE_L = 89,
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PKT_THREAD_ID_H = 88,
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PKT_THREAD_ID_L = 87,
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PKT_BEGIN_BURST = 81,
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PKT_PROTECTION_H = 80,
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PKT_PROTECTION_L = 80,
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PKT_BURSTWRAP_H = 79,
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PKT_BURSTWRAP_L = 77,
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PKT_BYTE_CNT_H = 76,
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PKT_BYTE_CNT_L = 74,
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PKT_ADDR_H = 73,
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PKT_ADDR_L = 42,
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PKT_BURST_SIZE_H = 86,
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PKT_BURST_SIZE_L = 84,
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PKT_BURST_TYPE_H = 94,
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PKT_BURST_TYPE_L = 93,
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PKT_TRANS_EXCLUSIVE = 83,
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PKT_TRANS_LOCK = 82,
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PKT_TRANS_COMPRESSED_READ = 41,
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PKT_TRANS_POSTED = 40,
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PKT_TRANS_WRITE = 39,
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PKT_TRANS_READ = 38,
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PKT_DATA_H = 37,
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PKT_DATA_L = 6,
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PKT_BYTEEN_H = 5,
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PKT_BYTEEN_L = 2,
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PKT_SRC_ID_H = 1,
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PKT_SRC_ID_L = 1,
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PKT_DEST_ID_H = 0,
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PKT_DEST_ID_L = 0,
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PKT_RESPONSE_STATUS_L = 110,
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PKT_RESPONSE_STATUS_H = 111,
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PKT_ORI_BURST_SIZE_L = 112,
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PKT_ORI_BURST_SIZE_H = 114,
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ST_DATA_W = 115,
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ST_CHANNEL_W = 1,
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// -------------------
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// Agent Parameters
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// -------------------
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AV_BURSTCOUNT_W = 3,
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ID = 1,
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SUPPRESS_0_BYTEEN_RSP = 1,
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BURSTWRAP_VALUE = 4,
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CACHE_VALUE = 0,
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SECURE_ACCESS_BIT = 1,
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USE_READRESPONSE = 0,
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USE_WRITERESPONSE = 0,
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// -------------------
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// Derived Parameters
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// -------------------
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PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
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PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
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PKT_PROTECTION_W = PKT_PROTECTION_H - PKT_PROTECTION_L + 1,
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PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1,
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PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1,
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PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
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PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1,
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PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1,
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PKT_BURST_SIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1
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) (
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// -------------------
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// Clock & Reset
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// -------------------
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input clk,
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input reset,
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// -------------------
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// Avalon-MM Anti-Master
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// -------------------
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input [PKT_ADDR_W-1 : 0] av_address,
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input av_write,
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input av_read,
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input [PKT_DATA_W-1 : 0] av_writedata,
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output reg [PKT_DATA_W-1 : 0] av_readdata,
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output reg av_waitrequest,
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output reg av_readdatavalid,
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input [PKT_BYTEEN_W-1 : 0] av_byteenable,
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input [AV_BURSTCOUNT_W-1 : 0] av_burstcount,
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input av_debugaccess,
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input av_lock,
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output reg [1 : 0] av_response,
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output reg av_writeresponsevalid,
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// -------------------
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// Command Source
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// -------------------
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output reg cp_valid,
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output reg [ST_DATA_W-1 : 0] cp_data,
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output wire cp_startofpacket,
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output wire cp_endofpacket,
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input cp_ready,
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// -------------------
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// Response Sink
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// -------------------
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input rp_valid,
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input [ST_DATA_W-1 : 0] rp_data,
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input [ST_CHANNEL_W-1 : 0] rp_channel,
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input rp_startofpacket,
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input rp_endofpacket,
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output reg rp_ready
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);
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// ------------------------------------------------------------
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// Utility Functions
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// ------------------------------------------------------------
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function integer clogb2;
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input [31 : 0] value;
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begin
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for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
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value = value >> 1;
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clogb2 = clogb2 - 1;
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end
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endfunction // clogb2
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localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1);
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localparam NUMSYMBOLS = PKT_BYTEEN_W;
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localparam BURSTING = (MAX_BURST > NUMSYMBOLS);
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localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS);
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localparam BURST_SIZE = clogb2(NUMSYMBOLS);
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typedef enum bit [1 : 0]
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{
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FIXED = 2'b00,
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INCR = 2'b01,
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WRAP = 2'b10,
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OTHER_WRAP = 2'b11
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} MerlinBurstType;
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// --------------------------------------
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// Potential optimization: compare in words to save bits?
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// --------------------------------------
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wire is_burst;
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assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS);
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wire [31 : 0] burstwrap_value_int = BURSTWRAP_VALUE;
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wire [31 : 0] id_int = ID;
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wire [PKT_BURST_SIZE_W-1 : 0] burstsize_sig = BURST_SIZE[PKT_BURST_SIZE_W-1 : 0];
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wire [1 : 0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP;
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// --------------------------------------
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// Address alignment
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//
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// The packet format requires that addresses be aligned to
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// the transaction size.
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// --------------------------------------
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wire [PKT_ADDR_W-1 : 0] av_address_aligned;
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generate
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if (NUMSYMBOLS > 1) begin
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assign av_address_aligned =
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{av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}};
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end
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else begin
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assign av_address_aligned = av_address;
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end
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endgenerate
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// --------------------------------------
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// Command & Response Construction
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// --------------------------------------
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always_comb begin
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cp_data = '0;
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cp_data[PKT_PROTECTION_L] = av_debugaccess;
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cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // secure cache bit
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cp_data[PKT_PROTECTION_L+2] = 1'b0; // instruction/data cache bit
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cp_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L] = burstwrap_value_int[PKT_BURSTWRAP_W-1 : 0];
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cp_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = av_burstcount;
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cp_data[PKT_ADDR_H : PKT_ADDR_L] = av_address_aligned;
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cp_data[PKT_TRANS_EXCLUSIVE] = 1'b0;
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cp_data[PKT_TRANS_LOCK] = av_lock;
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cp_data[PKT_TRANS_COMPRESSED_READ] = av_read & is_burst;
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cp_data[PKT_TRANS_READ] = av_read;
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cp_data[PKT_TRANS_WRITE] = av_write;
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cp_data[PKT_TRANS_POSTED] = av_write & !USE_WRITERESPONSE;
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cp_data[PKT_DATA_H : PKT_DATA_L] = av_writedata;
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cp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] = av_byteenable;
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cp_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L] = burstsize_sig;
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cp_data[PKT_ORI_BURST_SIZE_H : PKT_ORI_BURST_SIZE_L] = burstsize_sig;
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cp_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L] = bursttype_value;
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cp_data[PKT_SRC_ID_H : PKT_SRC_ID_L] = id_int[PKT_SRC_ID_W-1 : 0];
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cp_data[PKT_THREAD_ID_H : PKT_THREAD_ID_L] = '0;
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cp_data[PKT_CACHE_H : PKT_CACHE_L] = CACHE_VALUE[3 : 0];
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cp_data[PKT_QOS_H : PKT_QOS_L] = '0;
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cp_data[PKT_ADDR_SIDEBAND_H : PKT_ADDR_SIDEBAND_L] = '0;
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cp_data[PKT_DATA_SIDEBAND_H : PKT_DATA_SIDEBAND_L] = '0;
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av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L];
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if (USE_WRITERESPONSE || USE_READRESPONSE)
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av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L];
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else
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av_response = '0;
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end
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// --------------------------------------
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// Command Control
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// --------------------------------------
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reg hold_waitrequest;
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always @ (posedge clk, posedge reset) begin
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if (reset)
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hold_waitrequest <= 1'b1;
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else
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hold_waitrequest <= 1'b0;
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end
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always_comb begin
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cp_valid = 0;
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if ((av_write || av_read) && ~hold_waitrequest)
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cp_valid = 1;
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end
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generate if (BURSTING) begin
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reg sop_enable;
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always @(posedge clk, posedge reset) begin
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if (reset) begin
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sop_enable <= 1'b1;
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end
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else begin
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if (cp_valid && cp_ready) begin
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sop_enable <= 1'b0;
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if (cp_endofpacket)
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sop_enable <= 1'b1;
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end
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end
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end
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assign cp_startofpacket = sop_enable;
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assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS);
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end
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else begin
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assign cp_startofpacket = 1'b1;
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assign cp_endofpacket = 1'b1;
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end
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endgenerate
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// --------------------------------------
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// Backpressure & Readdatavalid
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// --------------------------------------
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always_comb begin
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rp_ready = 1;
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av_readdatavalid = 0;
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av_writeresponsevalid = 0;
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av_waitrequest = hold_waitrequest | !cp_ready;
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if (USE_WRITERESPONSE && (rp_data[PKT_TRANS_WRITE] == 1))
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av_writeresponsevalid = rp_valid;
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else
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av_readdatavalid = rp_valid;
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if (SUPPRESS_0_BYTEEN_RSP) begin
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if (rp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] == 0)
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av_readdatavalid = 0;
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end
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end
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endmodule
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