126 lines
4.0 KiB
Verilog
126 lines
4.0 KiB
Verilog
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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// turn off superfluous verilog processor warnings
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// altera message_level Level1
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// altera message_off 10034 10035 10036 10037 10230 10240 10030
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module niosII_mem (
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// inputs:
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address,
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address2,
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byteenable,
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byteenable2,
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chipselect,
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chipselect2,
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clk,
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clken,
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clken2,
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freeze,
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reset,
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reset_req,
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write,
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write2,
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writedata,
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writedata2,
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// outputs:
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readdata,
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readdata2
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)
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;
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parameter INIT_FILE = "niosII_mem.hex";
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output [ 31: 0] readdata;
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output [ 31: 0] readdata2;
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input [ 14: 0] address;
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input [ 14: 0] address2;
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input [ 3: 0] byteenable;
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input [ 3: 0] byteenable2;
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input chipselect;
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input chipselect2;
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input clk;
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input clken;
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input clken2;
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input freeze;
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input reset;
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input reset_req;
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input write;
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input write2;
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input [ 31: 0] writedata;
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input [ 31: 0] writedata2;
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wire clocken0;
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wire not_clken;
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wire not_clken2;
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wire [ 31: 0] readdata;
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wire [ 31: 0] readdata2;
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wire wren;
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wire wren2;
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assign wren = chipselect & write & clken;
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assign not_clken = ~clken;
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assign not_clken2 = ~clken2;
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assign clocken0 = ~reset_req;
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assign wren2 = chipselect2 & write2 & clken2;
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altsyncram the_altsyncram
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(
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.address_a (address),
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.address_b (address2),
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.addressstall_a (not_clken),
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.addressstall_b (not_clken2),
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.byteena_a (byteenable),
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.byteena_b (byteenable2),
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.clock0 (clk),
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.clocken0 (clocken0),
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.data_a (writedata),
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.data_b (writedata2),
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.q_a (readdata),
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.q_b (readdata2),
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.wren_a (wren),
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.wren_b (wren2)
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);
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defparam the_altsyncram.address_reg_b = "CLOCK0",
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the_altsyncram.byte_size = 8,
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the_altsyncram.byteena_reg_b = "CLOCK0",
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the_altsyncram.indata_reg_b = "CLOCK0",
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the_altsyncram.init_file = INIT_FILE,
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the_altsyncram.lpm_type = "altsyncram",
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the_altsyncram.maximum_depth = 32768,
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the_altsyncram.numwords_a = 32768,
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the_altsyncram.numwords_b = 32768,
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the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
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the_altsyncram.outdata_reg_a = "UNREGISTERED",
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the_altsyncram.outdata_reg_b = "UNREGISTERED",
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the_altsyncram.ram_block_type = "AUTO",
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the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
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the_altsyncram.width_a = 32,
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the_altsyncram.width_b = 32,
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the_altsyncram.width_byteena_a = 4,
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the_altsyncram.width_byteena_b = 4,
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the_altsyncram.widthad_a = 15,
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the_altsyncram.widthad_b = 15,
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the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK0";
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//s1, which is an e_avalon_slave
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//s2, which is an e_avalon_slave
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endmodule
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