273 lines
9.0 KiB
Systemverilog
273 lines
9.0 KiB
Systemverilog
// (C) 2001-2018 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// (C) 2001-2010 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $
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// $Revision: #3 $
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// $Date: 2010/07/07 $
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// $Author: jyeap $
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/* -----------------------------------------------------------------------
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Round-robin/fixed arbitration implementation.
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Q: how do you find the least-significant set-bit in an n-bit binary number, X?
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A: M = X & (~X + 1)
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Example: X = 101000100
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101000100 &
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010111011 + 1 =
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101000100 &
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010111100 =
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-----------
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000000100
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The method can be generalized to find the first set-bit
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at a bit index no lower than bit-index N, simply by adding
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2**N rather than 1.
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Q: how does this relate to round-robin arbitration?
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A:
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Let X be the concatenation of all request signals.
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Let the number to be added to X (hereafter called the
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top_priority) initialize to 1, and be assigned from the
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concatenation of the previous saved-grant, left-rotated
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by one position, each time arbitration occurs. The
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concatenation of grants is then M.
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Problem: consider this case:
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top_priority = 010000
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request = 001001
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~request + top_priority = 000110
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next_grant = 000000 <- no one is granted!
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There was no "set bit at a bit index no lower than bit-index 4", so
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the result was 0.
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We need to propagate the carry out from (~request + top_priority) to the LSB, so
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that the sum becomes 000111, and next_grant is 000001. This operation could be
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called a "circular add".
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A bit of experimentation on the circular add reveals a significant amount of
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delay in exiting and re-entering the carry chain - this will vary with device
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family. Quartus also reports a combinational loop warning. Finally,
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Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But
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Modelsim _doesn't_ report a combinational loop!)
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An alternate solution: concatenate the request vector with itself, and OR
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corresponding bits from the top and bottom halves to determine next_grant.
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Example:
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top_priority = 010000
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{request, request} = 001001 001001
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{~request, ~request} + top_priority = 110111 000110
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result of & operation = 000001 000000
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next_grant = 000001
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Notice that if request = 0, the sum operation will overflow, but we can ignore
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this; the next_grant result is 0 (no one granted), as you might expect.
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In the implementation, the last-granted value must be maintained as
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a non-zero value - best probably simply not to update it when no requests
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occur.
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----------------------------------------------------------------------- */
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`timescale 1 ns / 1 ns
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module altera_merlin_arbitrator
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#(
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parameter NUM_REQUESTERS = 8,
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// --------------------------------------
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// Implemented schemes
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// "round-robin"
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// "fixed-priority"
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// "no-arb"
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// --------------------------------------
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parameter SCHEME = "round-robin",
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parameter PIPELINE = 0
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)
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(
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input clk,
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input reset,
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// --------------------------------------
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// Requests
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// --------------------------------------
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input [NUM_REQUESTERS-1:0] request,
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// --------------------------------------
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// Grants
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// --------------------------------------
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output [NUM_REQUESTERS-1:0] grant,
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// --------------------------------------
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// Control Signals
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// --------------------------------------
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input increment_top_priority,
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input save_top_priority
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);
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// --------------------------------------
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// Signals
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// --------------------------------------
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wire [NUM_REQUESTERS-1:0] top_priority;
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reg [NUM_REQUESTERS-1:0] top_priority_reg;
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reg [NUM_REQUESTERS-1:0] last_grant;
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wire [2*NUM_REQUESTERS-1:0] result;
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// --------------------------------------
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// Scheme Selection
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// --------------------------------------
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generate
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if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
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assign top_priority = top_priority_reg;
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end
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else begin
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// Fixed arbitration (or single-requester corner case)
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assign top_priority = 1'b1;
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end
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endgenerate
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// --------------------------------------
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// Decision Logic
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// --------------------------------------
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altera_merlin_arb_adder
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#(
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.WIDTH (2 * NUM_REQUESTERS)
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)
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adder
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(
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.a ({ ~request, ~request }),
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.b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
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.sum (result)
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);
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generate if (SCHEME == "no-arb") begin
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// --------------------------------------
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// No arbitration: just wire request directly to grant
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// --------------------------------------
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assign grant = request;
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end else begin
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// Do the math in double-vector domain
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wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
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assign grant_double_vector = {request, request} & result;
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// --------------------------------------
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// Extract grant from the top and bottom halves
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// of the double vector.
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// --------------------------------------
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assign grant =
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grant_double_vector[NUM_REQUESTERS - 1 : 0] |
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grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
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end
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endgenerate
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// --------------------------------------
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// Left-rotate the last grant vector to create top_priority.
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// --------------------------------------
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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top_priority_reg <= 1'b1;
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end
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else begin
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if (PIPELINE) begin
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if (increment_top_priority) begin
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top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
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grant[NUM_REQUESTERS-1]} : top_priority_reg;
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end
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end else begin
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if (increment_top_priority) begin
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if (|request)
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top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
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grant[NUM_REQUESTERS-1] };
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else
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top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
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end
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else if (save_top_priority) begin
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top_priority_reg <= grant;
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end
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end
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end
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end
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endmodule
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// ----------------------------------------------
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// Adder for the standard arbitrator
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// ----------------------------------------------
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module altera_merlin_arb_adder
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#(
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parameter WIDTH = 8
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)
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(
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input [WIDTH-1:0] a,
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input [WIDTH-1:0] b,
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output [WIDTH-1:0] sum
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);
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wire [WIDTH:0] sum_lint;
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// ----------------------------------------------
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// Benchmarks indicate that for small widths, the full
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// adder has higher fmax because synthesis can merge
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// it with the mux, allowing partial decisions to be
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// made early.
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//
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// The magic number is 4 requesters, which means an
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// 8 bit adder.
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// ----------------------------------------------
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genvar i;
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generate if (WIDTH <= 8) begin : full_adder
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wire cout[WIDTH-1:0];
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assign sum[0] = (a[0] ^ b[0]);
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assign cout[0] = (a[0] & b[0]);
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for (i = 1; i < WIDTH; i = i+1) begin : arb
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assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
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assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
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end
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end else begin : carry_chain
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assign sum_lint = a + b;
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assign sum = sum_lint[WIDTH-1:0];
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end
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endgenerate
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endmodule
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