| .. |
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altera_avalon_sc_fifo.v
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wip lab4, nios connected, ready to program
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2023-01-27 18:04:01 +03:00 |
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altera_merlin_arbitrator.sv
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wip lab4, nios connected, ready to program
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2023-01-27 18:04:01 +03:00 |
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altera_merlin_burst_uncompressor.sv
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wip lab4, nios connected, ready to program
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2023-01-27 18:04:01 +03:00 |
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altera_merlin_master_agent.sv
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wip lab4, nios connected, ready to program
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2023-01-27 18:04:01 +03:00 |
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altera_merlin_master_translator.sv
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wip lab4, nios connected, ready to program
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2023-01-27 18:04:01 +03:00 |
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altera_merlin_slave_agent.sv
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wip lab4, nios connected, ready to program
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2023-01-27 18:04:01 +03:00 |
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altera_merlin_slave_translator.sv
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wip lab4, nios connected, ready to program
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2023-01-27 18:04:01 +03:00 |
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altera_reset_controller.sdc
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wip lab4, nios connected, ready to program
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2023-01-27 18:04:01 +03:00 |
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altera_reset_controller.v
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wip lab4, nios connected, ready to program
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2023-01-27 18:04:01 +03:00 |
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altera_reset_synchronizer.v
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wip lab4, nios connected, ready to program
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2023-01-27 18:04:01 +03:00 |
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dec.sv
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Merge remote-tracking branch 'my/simulation' into simulation preferring their
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2023-01-24 15:05:03 +03:00 |
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niosII_cpu.v
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_cpu_cpu.sdc
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reported lr2 + individual
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2023-01-18 16:45:45 +03:00 |
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niosII_cpu_cpu.v
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_cpu_cpu_debug_slave_sysclk.v
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reported lr2 + individual
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2023-01-18 16:45:45 +03:00 |
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niosII_cpu_cpu_debug_slave_tck.v
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reported lr2 + individual
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2023-01-18 16:45:45 +03:00 |
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niosII_cpu_cpu_debug_slave_wrapper.v
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reported lr2 + individual
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2023-01-18 16:45:45 +03:00 |
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niosII_cpu_cpu_ociram_default_contents.mif
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reported lr2 + individual
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2023-01-18 16:45:45 +03:00 |
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niosII_cpu_cpu_rf_ram_a.mif
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wip lab4, nios connected, ready to program
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2023-01-27 18:04:01 +03:00 |
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niosII_cpu_cpu_rf_ram_b.mif
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wip lab4, nios connected, ready to program
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2023-01-27 18:04:01 +03:00 |
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niosII_cpu_cpu_test_bench.v
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_irq_mapper.sv
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pt2 done, qsys added, compiled successfully
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2022-10-19 13:25:43 +03:00 |
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niosII_jtag_uart.v
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reported lr2 + individual
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2023-01-18 16:45:45 +03:00 |
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niosII_mem.hex
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_mem.v
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_mm_interconnect_0.v
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_mm_interconnect_0_avalon_st_adapter.v
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wip lab4, nios connected, ready to program
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2023-01-27 18:04:01 +03:00 |
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niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
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pt2 done, qsys added, compiled successfully
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2022-10-19 13:25:43 +03:00 |
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niosII_mm_interconnect_0_cmd_demux.sv
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_mm_interconnect_0_cmd_demux_001.sv
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_mm_interconnect_0_cmd_mux.sv
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_mm_interconnect_0_cmd_mux_002.sv
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_mm_interconnect_0_router.sv
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_mm_interconnect_0_router_001.sv
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_mm_interconnect_0_router_002.sv
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_mm_interconnect_0_router_004.sv
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_mm_interconnect_0_router_008.sv
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done in hardware
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2023-01-24 12:46:22 +03:00 |
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niosII_mm_interconnect_0_rsp_demux.sv
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_mm_interconnect_0_rsp_mux.sv
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_mm_interconnect_0_rsp_mux_001.sv
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work board parameters
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2023-02-07 13:31:34 +03:00 |
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niosII_sys_clk_timer.v
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reported lr2 + individual
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2023-01-18 16:45:45 +03:00 |
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periodram.v
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done in hardware
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2023-01-24 12:46:22 +03:00 |
