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fpga-lab-2/Top/niosII/synthesis/submodules
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Ivan I. Ovchinnikov 77e2cf25d3 Merge remote-tracking branch 'my/simulation' into simulation preferring their 
# Conflicts:
#	Top/niosII.sopcinfo
#	Top/semafor.qws
#	Top/software/semafor/.settings/language.settings.xml
#	Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf
#	Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.map
#	Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump
#	Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat
#	Top/software/semafor/mem_init/hdl_sim/niosII_mem.sym
#	Top/software/semafor/mem_init/niosII_mem.hex
#	Top/software/semafor/obj/default/runtime/sim/mentor/wave.do
#	Top/software/semafor/sem.c
#	Top/software/semafor_bsp/.settings/language.settings.xml
#	Top/software/semafor_bsp/libhal_bsp.a
#	Top/software/semafor_bsp/settings.bsp
#	Top/software/semafor_bsp/summary.html
 		2023-01-24 15:05:03 +03:00
..
altera_avalon_sc_fifo.v done in hardware 2023-01-24 12:46:22 +03:00
altera_merlin_arbitrator.sv done in hardware 2023-01-24 12:46:22 +03:00
altera_merlin_burst_uncompressor.sv done in hardware 2023-01-24 12:46:22 +03:00
altera_merlin_master_agent.sv done in hardware 2023-01-24 12:46:22 +03:00
altera_merlin_master_translator.sv done in hardware 2023-01-24 12:46:22 +03:00
altera_merlin_slave_agent.sv done in hardware 2023-01-24 12:46:22 +03:00
altera_merlin_slave_translator.sv done in hardware 2023-01-24 12:46:22 +03:00
altera_reset_controller.sdc done in hardware 2023-01-24 12:46:22 +03:00
altera_reset_controller.v done in hardware 2023-01-24 12:46:22 +03:00
altera_reset_synchronizer.v done in hardware 2023-01-24 12:46:22 +03:00
dec.sv Merge remote-tracking branch 'my/simulation' into simulation preferring their 2023-01-24 15:05:03 +03:00
niosII_cpu.v pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_cpu_cpu.sdc reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu_debug_slave_sysclk.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu_debug_slave_tck.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu_debug_slave_wrapper.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu_ociram_default_contents.mif reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu_rf_ram_a.mif done in hardware 2023-01-24 12:46:22 +03:00
niosII_cpu_cpu_rf_ram_b.mif done in hardware 2023-01-24 12:46:22 +03:00
niosII_cpu_cpu_test_bench.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_irq_mapper.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_jtag_uart.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_mem.hex done in hardware 2023-01-24 12:46:22 +03:00
niosII_mem.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_mm_interconnect_0.v ram32ok 2022-12-22 22:27:05 +03:00
niosII_mm_interconnect_0_avalon_st_adapter.v done in hardware 2023-01-24 12:46:22 +03:00
niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mm_interconnect_0_cmd_demux.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mm_interconnect_0_cmd_demux_001.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mm_interconnect_0_cmd_mux.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mm_interconnect_0_cmd_mux_002.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mm_interconnect_0_router.sv ram32ok 2022-12-22 22:27:05 +03:00
niosII_mm_interconnect_0_router_001.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mm_interconnect_0_router_002.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mm_interconnect_0_router_004.sv done in hardware 2023-01-24 12:46:22 +03:00
niosII_mm_interconnect_0_router_008.sv done in hardware 2023-01-24 12:46:22 +03:00
niosII_mm_interconnect_0_rsp_demux.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mm_interconnect_0_rsp_mux.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mm_interconnect_0_rsp_mux_001.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_sys_clk_timer.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
periodram.v done in hardware 2023-01-24 12:46:22 +03:00