96 lines
8.4 KiB
Verilog
96 lines
8.4 KiB
Verilog
// niosII_cpu.v
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// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
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// will probably be lost.
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//
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// Generated using ACDS version 18.1 625
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`timescale 1 ps / 1 ps
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module niosII_cpu (
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input wire clk, // clk.clk
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input wire reset_n, // reset.reset_n
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input wire reset_req, // .reset_req
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output wire [17:0] d_address, // data_master.address
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output wire [3:0] d_byteenable, // .byteenable
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output wire d_read, // .read
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input wire [31:0] d_readdata, // .readdata
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input wire d_waitrequest, // .waitrequest
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output wire d_write, // .write
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output wire [31:0] d_writedata, // .writedata
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output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
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output wire [17:0] i_address, // instruction_master.address
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output wire i_read, // .read
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input wire [31:0] i_readdata, // .readdata
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input wire i_waitrequest, // .waitrequest
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input wire [31:0] irq, // irq.irq
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output wire debug_reset_request, // debug_reset_request.reset
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input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
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input wire [3:0] debug_mem_slave_byteenable, // .byteenable
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input wire debug_mem_slave_debugaccess, // .debugaccess
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input wire debug_mem_slave_read, // .read
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output wire [31:0] debug_mem_slave_readdata, // .readdata
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output wire debug_mem_slave_waitrequest, // .waitrequest
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input wire debug_mem_slave_write, // .write
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input wire [31:0] debug_mem_slave_writedata, // .writedata
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input wire [31:0] E_ci_result, // custom_instruction_master.result
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output wire [4:0] D_ci_a, // .a
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output wire [4:0] D_ci_b, // .b
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output wire [4:0] D_ci_c, // .c
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output wire [7:0] D_ci_n, // .n
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output wire D_ci_readra, // .readra
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output wire D_ci_readrb, // .readrb
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output wire D_ci_writerc, // .writerc
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output wire [31:0] E_ci_dataa, // .dataa
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output wire [31:0] E_ci_datab, // .datab
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output wire E_ci_multi_clock, // .clk
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output wire E_ci_multi_reset, // .reset
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output wire E_ci_multi_reset_req, // .reset_req
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output wire W_ci_estatus, // .estatus
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output wire [31:0] W_ci_ipending // .ipending
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);
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niosII_cpu_cpu cpu (
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.clk (clk), // clk.clk
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.reset_n (reset_n), // reset.reset_n
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.reset_req (reset_req), // .reset_req
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.d_address (d_address), // data_master.address
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.d_byteenable (d_byteenable), // .byteenable
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.d_read (d_read), // .read
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.d_readdata (d_readdata), // .readdata
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.d_waitrequest (d_waitrequest), // .waitrequest
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.d_write (d_write), // .write
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.d_writedata (d_writedata), // .writedata
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.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
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.i_address (i_address), // instruction_master.address
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.i_read (i_read), // .read
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.i_readdata (i_readdata), // .readdata
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.i_waitrequest (i_waitrequest), // .waitrequest
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.irq (irq), // irq.irq
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.debug_reset_request (debug_reset_request), // debug_reset_request.reset
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.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
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.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
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.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
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.debug_mem_slave_read (debug_mem_slave_read), // .read
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.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
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.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
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.debug_mem_slave_write (debug_mem_slave_write), // .write
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.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
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.E_ci_result (E_ci_result), // custom_instruction_master.result
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.D_ci_a (D_ci_a), // .a
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.D_ci_b (D_ci_b), // .b
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.D_ci_c (D_ci_c), // .c
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.D_ci_n (D_ci_n), // .n
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.D_ci_readra (D_ci_readra), // .readra
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.D_ci_readrb (D_ci_readrb), // .readrb
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.D_ci_writerc (D_ci_writerc), // .writerc
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.E_ci_dataa (E_ci_dataa), // .dataa
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.E_ci_datab (E_ci_datab), // .datab
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.E_ci_multi_clock (E_ci_multi_clock), // .clk
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.E_ci_multi_reset (E_ci_multi_reset), // .reset
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.E_ci_multi_reset_req (E_ci_multi_reset_req), // .reset_req
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.W_ci_estatus (W_ci_estatus), // .estatus
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.W_ci_ipending (W_ci_ipending) // .ipending
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);
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endmodule
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