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fpga-lab-2/Top/niosII/synthesis/submodules
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Ivan I. Ovchinnikov 83b0f857d3 Merge branch 'simulation' into lab3 preferring lab3 in conflicts 
# Conflicts:
#	Top/niosII.sopcinfo
#	Top/niosII/niosII.html
#	Top/niosII/niosII.xml
#	Top/niosII/synthesis/niosII.debuginfo
#	Top/niosII/synthesis/niosII.qip
#	Top/semafor.qws
 		2023-01-20 12:59:24 +03:00
..
altera_avalon_sc_fifo.v pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
altera_merlin_arbitrator.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
altera_merlin_burst_uncompressor.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
altera_merlin_master_agent.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
altera_merlin_master_translator.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
altera_merlin_slave_agent.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
altera_merlin_slave_translator.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
altera_reset_controller.sdc pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
altera_reset_controller.v pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
altera_reset_synchronizer.v pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
dec.sv reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu.v lab3 until board programming (pt1 p9) 2022-12-24 22:37:46 +03:00
niosII_cpu_cpu.sdc reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu.v Merge branch 'simulation' into lab3 preferring lab3 in conflicts 2023-01-20 12:59:24 +03:00
niosII_cpu_cpu_debug_slave_sysclk.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu_debug_slave_tck.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu_debug_slave_wrapper.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu_ociram_default_contents.mif reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu_rf_ram_a.mif pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_cpu_cpu_rf_ram_b.mif pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_cpu_cpu_test_bench.v Merge branch 'simulation' into lab3 preferring lab3 in conflicts 2023-01-20 12:59:24 +03:00
niosII_irq_mapper.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_jtag_uart.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_mem.hex pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mem.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_mm_interconnect_0.v lab3 until board programming (pt1 p9) 2022-12-24 22:37:46 +03:00
niosII_mm_interconnect_0_avalon_st_adapter.v pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mm_interconnect_0_cmd_demux.sv lab3 until board programming (pt1 p9) 2022-12-24 22:37:46 +03:00
niosII_mm_interconnect_0_cmd_demux_001.sv lab3 until board programming (pt1 p9) 2022-12-24 22:37:46 +03:00
niosII_mm_interconnect_0_cmd_mux.sv lab3 until board programming (pt1 p9) 2022-12-24 22:37:46 +03:00
niosII_mm_interconnect_0_cmd_mux_002.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mm_interconnect_0_router.sv lab3 until board programming (pt1 p9) 2022-12-24 22:37:46 +03:00
niosII_mm_interconnect_0_router_001.sv lab3 until board programming (pt1 p9) 2022-12-24 22:37:46 +03:00
niosII_mm_interconnect_0_router_002.sv lab3 until board programming (pt1 p9) 2022-12-24 22:37:46 +03:00
niosII_mm_interconnect_0_router_004.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mm_interconnect_0_router_008.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mm_interconnect_0_rsp_demux.sv lab3 until board programming (pt1 p9) 2022-12-24 22:37:46 +03:00
niosII_mm_interconnect_0_rsp_mux.sv lab3 until board programming (pt1 p9) 2022-12-24 22:37:46 +03:00
niosII_mm_interconnect_0_rsp_mux_001.sv lab3 until board programming (pt1 p9) 2022-12-24 22:37:46 +03:00
niosII_sys_clk_timer.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
periodram.v ram32ok 2022-12-22 22:27:05 +03:00