212 lines
6.6 KiB
Verilog
212 lines
6.6 KiB
Verilog
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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// turn off superfluous verilog processor warnings
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// altera message_level Level1
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// altera message_off 10034 10035 10036 10037 10230 10240 10030
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module niosII_sys_clk_timer (
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// inputs:
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address,
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chipselect,
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clk,
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reset_n,
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write_n,
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writedata,
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// outputs:
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irq,
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readdata
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)
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;
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output irq;
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output [ 15: 0] readdata;
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input [ 2: 0] address;
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input chipselect;
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input clk;
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input reset_n;
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input write_n;
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input [ 15: 0] writedata;
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wire clk_en;
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wire control_continuous;
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wire control_interrupt_enable;
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reg [ 3: 0] control_register;
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wire control_wr_strobe;
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reg counter_is_running;
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wire counter_is_zero;
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wire [ 31: 0] counter_load_value;
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reg [ 31: 0] counter_snapshot;
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reg delayed_unxcounter_is_zeroxx0;
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wire do_start_counter;
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wire do_stop_counter;
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reg force_reload;
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reg [ 31: 0] internal_counter;
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wire irq;
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reg [ 15: 0] period_h_register;
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wire period_h_wr_strobe;
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reg [ 15: 0] period_l_register;
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wire period_l_wr_strobe;
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wire [ 15: 0] read_mux_out;
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reg [ 15: 0] readdata;
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wire snap_h_wr_strobe;
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wire snap_l_wr_strobe;
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wire [ 31: 0] snap_read_value;
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wire snap_strobe;
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wire start_strobe;
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wire status_wr_strobe;
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wire stop_strobe;
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wire timeout_event;
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reg timeout_occurred;
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assign clk_en = 1;
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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internal_counter <= 32'hC34F;
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else if (counter_is_running || force_reload)
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if (counter_is_zero || force_reload)
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internal_counter <= counter_load_value;
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else
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internal_counter <= internal_counter - 1;
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end
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assign counter_is_zero = internal_counter == 0;
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assign counter_load_value = {period_h_register,
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period_l_register};
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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force_reload <= 0;
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else if (clk_en)
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force_reload <= period_h_wr_strobe || period_l_wr_strobe;
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end
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assign do_start_counter = start_strobe;
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assign do_stop_counter = (stop_strobe ) ||
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(force_reload ) ||
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(counter_is_zero && ~control_continuous );
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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counter_is_running <= 1'b0;
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else if (clk_en)
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if (do_start_counter)
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counter_is_running <= -1;
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else if (do_stop_counter)
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counter_is_running <= 0;
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end
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//delayed_unxcounter_is_zeroxx0, which is an e_register
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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delayed_unxcounter_is_zeroxx0 <= 0;
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else if (clk_en)
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delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
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end
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assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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timeout_occurred <= 0;
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else if (clk_en)
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if (status_wr_strobe)
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timeout_occurred <= 0;
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else if (timeout_event)
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timeout_occurred <= -1;
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end
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assign irq = timeout_occurred && control_interrupt_enable;
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//s1, which is an e_avalon_slave
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assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
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({16 {(address == 3)}} & period_h_register) |
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({16 {(address == 4)}} & snap_read_value[15 : 0]) |
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({16 {(address == 5)}} & snap_read_value[31 : 16]) |
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({16 {(address == 1)}} & control_register) |
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({16 {(address == 0)}} & {counter_is_running,
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timeout_occurred});
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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readdata <= 0;
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else if (clk_en)
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readdata <= read_mux_out;
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end
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assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
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assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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period_l_register <= 49999;
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else if (period_l_wr_strobe)
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period_l_register <= writedata;
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end
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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period_h_register <= 0;
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else if (period_h_wr_strobe)
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period_h_register <= writedata;
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end
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assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
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assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
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assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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counter_snapshot <= 0;
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else if (snap_strobe)
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counter_snapshot <= internal_counter;
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end
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assign snap_read_value = counter_snapshot;
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assign control_wr_strobe = chipselect && ~write_n && (address == 1);
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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control_register <= 0;
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else if (control_wr_strobe)
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control_register <= writedata[3 : 0];
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end
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assign stop_strobe = writedata[3] && control_wr_strobe;
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assign start_strobe = writedata[2] && control_wr_strobe;
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assign control_continuous = control_register[1];
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assign control_interrupt_enable = control_register[0];
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assign status_wr_strobe = chipselect && ~write_n && (address == 0);
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endmodule
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