fpga-lab-2/HDL
Ivan I. Ovchinnikov dad79c26fb wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
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IP wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00
dec.sv Merge remote-tracking branch 'my/simulation' into simulation preferring their 2023-01-24 15:05:03 +03:00
phacc.sv wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00
sdmod.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
sigdel.sv wip lab4, tested module 2023-01-27 17:06:29 +03:00