24 lines
427 B
Systemverilog
24 lines
427 B
Systemverilog
module phacc
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#(
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parameter unsigned WIDTH = 14
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) (
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input logic [7:0] phinc,
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input clk,
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input reset,
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output [7:0] phase
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);
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logic [WIDTH - 1 : 0] sum;
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always_ff @(posedge clk, negedge reset) begin
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if (~reset) begin
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sum <= 0;
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end else begin
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sum <= sum + phinc;
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end
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end
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assign phase = sum[WIDTH - 1 : WIDTH - 8];
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endmodule
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