fpga-lab-2/HDL/IP/periodram_inst.v

9 lines
180 B
Verilog

periodram periodram_inst (
.clock ( clock_sig ),
.data ( data_sig ),
.rdaddress ( rdaddress_sig ),
.wraddress ( wraddress_sig ),
.wren ( wren_sig ),
.q ( q_sig )
);