56 lines
1.2 KiB
Systemverilog
56 lines
1.2 KiB
Systemverilog
`timescale 1 ns/1 ns
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module lut_mod_tb();
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// Parameters
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localparam CLK_PRD = 20;
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localparam PHACC_WIDTH = 14;
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logic clk, clr_n, wr_n, daco;
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logic [7:0] phinc_val, phase, sine;
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// Instantiate UUT and connect used ports
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phacc phacc (
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.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase)
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);
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defparam phacc.WIDTH = PHACC_WIDTH;
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sinelut sinelut_inst (
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.address(phase), .clock(clk), .q(sine)
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);
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sdmod sdmod_inst (
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.val(sine), .clk(clk), .reset(clr_n), .daco(daco)
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// .val(8'd0), .clk(clk), .reset(clr_n), .daco(daco)
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// .val(8'd255), .clk(clk), .reset(clr_n), .daco(daco)
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);
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// Clock definition
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initial begin
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clk = 0;
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forever #(CLK_PRD/2) clk = ~clk;
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end
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// Reset and initial values definition
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initial begin
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clr_n = 0;
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#(CLK_PRD*5) clr_n = 1;
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end
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// Bus write transaction simulation
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initial begin
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// Wait until system is out of reset
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@(posedge clr_n);
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phinc_val=(2**(PHACC_WIDTH - 8));
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if ((phinc_val <= 255) && (phinc_val != 0)) begin
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#(CLK_PRD * 256 * 10) $stop;
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end else begin
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$display("Error: value of phase increment is out of range! Stopped simulation.");
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#1 $stop;
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end
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end
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endmodule
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