fpga-lab-2/Top/niosII/niosII_bb.v

11 lines
174 B
Verilog

module niosII (
clk_clk,
conduit_end_writeresponsevalid_n,
reset_reset_n);
input clk_clk;
output conduit_end_writeresponsevalid_n;
input reset_reset_n;
endmodule