377 lines
31 KiB
Tcl
377 lines
31 KiB
Tcl
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# (C) 2001-2023 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions and
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# other software and tools, and its AMPP partner logic functions, and
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# any output files any of the foregoing (including device programming
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# or simulation files), and any associated documentation or information
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# are expressly subject to the terms and conditions of the Altera
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# Program License Subscription Agreement, Altera MegaCore Function
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# License Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by Altera
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# or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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# ----------------------------------------
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# Auto-generated simulation script msim_setup.tcl
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# ----------------------------------------
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# This script provides commands to simulate the following IP detected in
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# your Quartus project:
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# niosII_tb
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#
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# Altera recommends that you source this Quartus-generated IP simulation
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# script from your own customized top-level script, and avoid editing this
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# generated script.
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#
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# To write a top-level script that compiles Altera simulation libraries and
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# the Quartus-generated IP in your project, along with your design and
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# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
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# into a new file, e.g. named "mentor.do", and modify the text as directed.
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#
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# ----------------------------------------
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# # TOP-LEVEL TEMPLATE - BEGIN
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# #
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# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
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# # construct paths to the files required to simulate the IP in your Quartus
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# # project. By default, the IP script assumes that you are launching the
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# # simulator from the IP script location. If launching from another
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# # location, set QSYS_SIMDIR to the output directory you specified when you
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# # generated the IP script, relative to the directory from which you launch
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# # the simulator.
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# #
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# set QSYS_SIMDIR <script generation output directory>
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# #
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# # Source the generated IP simulation script.
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# source $QSYS_SIMDIR/mentor/msim_setup.tcl
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# #
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# # Set any compilation options you require (this is unusual).
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# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
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# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
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# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
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# #
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# # Call command to compile the Quartus EDA simulation library.
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# dev_com
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# #
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# # Call command to compile the Quartus-generated IP simulation files.
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# com
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# #
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# # Add commands to compile all design files and testbench files, including
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# # the top level. (These are all the files required for simulation other
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# # than the files compiled by the Quartus-generated IP simulation script)
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# #
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# vlog <compilation options> <design and testbench files>
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# #
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# # Set the top-level simulation or testbench module/entity name, which is
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# # used by the elab command to elaborate the top level.
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# #
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# set TOP_LEVEL_NAME <simulation top>
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# #
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# # Set any elaboration options you require.
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# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
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# #
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# # Call command to elaborate your design and testbench.
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# elab
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# #
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# # Run the simulation.
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# run -a
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# #
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# # Report success to the shell.
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# exit -code 0
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# #
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# # TOP-LEVEL TEMPLATE - END
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# ----------------------------------------
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#
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# IP SIMULATION SCRIPT
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# ----------------------------------------
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# If niosII_tb is one of several IP cores in your
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# Quartus project, you can generate a simulation script
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# suitable for inclusion in your top-level simulation
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# script by running the following command line:
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#
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# ip-setup-simulation --quartus-project=<quartus project>
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#
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# ip-setup-simulation will discover the Altera IP
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# within the Quartus project, and generate a unified
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# script which supports all the Altera IP within the design.
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# ----------------------------------------
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# ACDS 18.1 625 linux 2023.01.17.19:01:36
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# ----------------------------------------
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# Initialize variables
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if ![info exists SYSTEM_INSTANCE_NAME] {
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set SYSTEM_INSTANCE_NAME ""
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} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
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set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
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}
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if ![info exists TOP_LEVEL_NAME] {
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set TOP_LEVEL_NAME "niosII_tb"
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}
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if ![info exists QSYS_SIMDIR] {
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set QSYS_SIMDIR "./../"
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}
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if ![info exists QUARTUS_INSTALL_DIR] {
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set QUARTUS_INSTALL_DIR "/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/"
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}
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if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
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set USER_DEFINED_COMPILE_OPTIONS ""
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}
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if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
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set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
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}
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if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
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set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
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}
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if ![info exists USER_DEFINED_ELAB_OPTIONS] {
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set USER_DEFINED_ELAB_OPTIONS ""
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}
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# ----------------------------------------
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# Initialize simulation properties - DO NOT MODIFY!
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set ELAB_OPTIONS ""
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set SIM_OPTIONS ""
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if ![ string match "*-64 vsim*" [ vsim -version ] ] {
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} else {
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}
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# ----------------------------------------
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# Copy ROM/RAM files to simulation directory
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alias file_copy {
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echo "\[exec\] file_copy"
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file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
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file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
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file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
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file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
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file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
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file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
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file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
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file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
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file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
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file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
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}
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# ----------------------------------------
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# Create compilation libraries
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proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
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ensure_lib ./libraries/
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ensure_lib ./libraries/work/
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vmap work ./libraries/work/
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vmap work_lib ./libraries/work/
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if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
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ensure_lib ./libraries/altera_ver/
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vmap altera_ver ./libraries/altera_ver/
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ensure_lib ./libraries/lpm_ver/
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vmap lpm_ver ./libraries/lpm_ver/
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ensure_lib ./libraries/sgate_ver/
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vmap sgate_ver ./libraries/sgate_ver/
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ensure_lib ./libraries/altera_mf_ver/
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vmap altera_mf_ver ./libraries/altera_mf_ver/
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ensure_lib ./libraries/altera_lnsim_ver/
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vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
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ensure_lib ./libraries/cycloneive_ver/
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vmap cycloneive_ver ./libraries/cycloneive_ver/
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}
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ensure_lib ./libraries/altera_common_sv_packages/
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vmap altera_common_sv_packages ./libraries/altera_common_sv_packages/
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ensure_lib ./libraries/error_adapter_0/
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vmap error_adapter_0 ./libraries/error_adapter_0/
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ensure_lib ./libraries/avalon_st_adapter/
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vmap avalon_st_adapter ./libraries/avalon_st_adapter/
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ensure_lib ./libraries/rsp_mux_001/
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vmap rsp_mux_001 ./libraries/rsp_mux_001/
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ensure_lib ./libraries/rsp_mux/
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vmap rsp_mux ./libraries/rsp_mux/
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ensure_lib ./libraries/rsp_demux/
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vmap rsp_demux ./libraries/rsp_demux/
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ensure_lib ./libraries/cmd_mux_002/
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vmap cmd_mux_002 ./libraries/cmd_mux_002/
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ensure_lib ./libraries/cmd_mux/
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vmap cmd_mux ./libraries/cmd_mux/
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ensure_lib ./libraries/cmd_demux_001/
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vmap cmd_demux_001 ./libraries/cmd_demux_001/
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ensure_lib ./libraries/cmd_demux/
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vmap cmd_demux ./libraries/cmd_demux/
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ensure_lib ./libraries/router_008/
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vmap router_008 ./libraries/router_008/
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ensure_lib ./libraries/router_004/
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vmap router_004 ./libraries/router_004/
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ensure_lib ./libraries/router_002/
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vmap router_002 ./libraries/router_002/
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ensure_lib ./libraries/router_001/
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vmap router_001 ./libraries/router_001/
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ensure_lib ./libraries/router/
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vmap router ./libraries/router/
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ensure_lib ./libraries/jtag_uart_avalon_jtag_slave_agent_rsp_fifo/
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vmap jtag_uart_avalon_jtag_slave_agent_rsp_fifo ./libraries/jtag_uart_avalon_jtag_slave_agent_rsp_fifo/
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ensure_lib ./libraries/jtag_uart_avalon_jtag_slave_agent/
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vmap jtag_uart_avalon_jtag_slave_agent ./libraries/jtag_uart_avalon_jtag_slave_agent/
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ensure_lib ./libraries/cpu_data_master_agent/
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vmap cpu_data_master_agent ./libraries/cpu_data_master_agent/
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ensure_lib ./libraries/jtag_uart_avalon_jtag_slave_translator/
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vmap jtag_uart_avalon_jtag_slave_translator ./libraries/jtag_uart_avalon_jtag_slave_translator/
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ensure_lib ./libraries/cpu_data_master_translator/
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vmap cpu_data_master_translator ./libraries/cpu_data_master_translator/
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ensure_lib ./libraries/cpu/
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vmap cpu ./libraries/cpu/
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ensure_lib ./libraries/rst_controller/
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vmap rst_controller ./libraries/rst_controller/
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ensure_lib ./libraries/irq_mapper/
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vmap irq_mapper ./libraries/irq_mapper/
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ensure_lib ./libraries/mm_interconnect_0/
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vmap mm_interconnect_0 ./libraries/mm_interconnect_0/
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ensure_lib ./libraries/sys_clk_timer/
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vmap sys_clk_timer ./libraries/sys_clk_timer/
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ensure_lib ./libraries/sem/
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vmap sem ./libraries/sem/
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ensure_lib ./libraries/mem/
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vmap mem ./libraries/mem/
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ensure_lib ./libraries/jtag_uart/
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vmap jtag_uart ./libraries/jtag_uart/
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ensure_lib ./libraries/niosII_inst_reset_bfm/
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vmap niosII_inst_reset_bfm ./libraries/niosII_inst_reset_bfm/
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ensure_lib ./libraries/niosII_inst_clk_bfm/
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vmap niosII_inst_clk_bfm ./libraries/niosII_inst_clk_bfm/
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ensure_lib ./libraries/niosII_inst/
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vmap niosII_inst ./libraries/niosII_inst/
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# ----------------------------------------
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# Compile device library files
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alias dev_com {
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echo "\[exec\] dev_com"
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if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v" -work cycloneive_ver
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}
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}
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# ----------------------------------------
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# Compile the design files in correct order
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alias com {
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echo "\[exec\] com"
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/verbosity_pkg.sv" -work altera_common_sv_packages
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" -L altera_common_sv_packages -work error_adapter_0
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v" -work avalon_st_adapter
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv" -L altera_common_sv_packages -work rsp_mux_001
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -L altera_common_sv_packages -work rsp_mux_001
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv" -L altera_common_sv_packages -work rsp_mux
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -L altera_common_sv_packages -work rsp_mux
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv" -L altera_common_sv_packages -work rsp_demux
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv" -L altera_common_sv_packages -work cmd_mux_002
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -L altera_common_sv_packages -work cmd_mux_002
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv" -L altera_common_sv_packages -work cmd_mux
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -L altera_common_sv_packages -work cmd_mux
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv" -L altera_common_sv_packages -work cmd_demux_001
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv" -L altera_common_sv_packages -work cmd_demux
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv" -L altera_common_sv_packages -work router_008
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv" -L altera_common_sv_packages -work router_004
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv" -L altera_common_sv_packages -work router_002
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv" -L altera_common_sv_packages -work router_001
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv" -L altera_common_sv_packages -work router
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v" -work jtag_uart_avalon_jtag_slave_agent_rsp_fifo
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv" -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_agent
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv" -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_agent
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv" -L altera_common_sv_packages -work cpu_data_master_agent
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv" -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_translator
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv" -L altera_common_sv_packages -work cpu_data_master_translator
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v" -work cpu
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v" -work cpu
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v" -work cpu
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v" -work cpu
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v" -work cpu
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v" -work rst_controller
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_synchronizer.v" -work rst_controller
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_irq_mapper.sv" -L altera_common_sv_packages -work irq_mapper
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v" -work mm_interconnect_0
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v" -work sys_clk_timer
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/dec.sv" -L altera_common_sv_packages -work sem
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/periodram.v" -work sem
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.v" -work mem
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_jtag_uart.v" -work jtag_uart
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu.v" -work cpu
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv" -L altera_common_sv_packages -work niosII_inst_reset_bfm
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eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv" -L altera_common_sv_packages -work niosII_inst_clk_bfm
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII.v" -work niosII_inst
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eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/niosII_tb.v"
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}
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# ----------------------------------------
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# Elaborate top level design
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alias elab {
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|
echo "\[exec\] elab"
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eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_common_sv_packages -L error_adapter_0 -L avalon_st_adapter -L rsp_mux_001 -L rsp_mux -L rsp_demux -L cmd_mux_002 -L cmd_mux -L cmd_demux_001 -L cmd_demux -L router_008 -L router_004 -L router_002 -L router_001 -L router -L jtag_uart_avalon_jtag_slave_agent_rsp_fifo -L jtag_uart_avalon_jtag_slave_agent -L cpu_data_master_agent -L jtag_uart_avalon_jtag_slave_translator -L cpu_data_master_translator -L cpu -L rst_controller -L irq_mapper -L mm_interconnect_0 -L sys_clk_timer -L sem -L mem -L jtag_uart -L niosII_inst_reset_bfm -L niosII_inst_clk_bfm -L niosII_inst -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver $TOP_LEVEL_NAME
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|
}
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|
|
|
# ----------------------------------------
|
|
# Elaborate the top level design with novopt option
|
|
alias elab_debug {
|
|
echo "\[exec\] elab_debug"
|
|
eval vsim -novopt -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_common_sv_packages -L error_adapter_0 -L avalon_st_adapter -L rsp_mux_001 -L rsp_mux -L rsp_demux -L cmd_mux_002 -L cmd_mux -L cmd_demux_001 -L cmd_demux -L router_008 -L router_004 -L router_002 -L router_001 -L router -L jtag_uart_avalon_jtag_slave_agent_rsp_fifo -L jtag_uart_avalon_jtag_slave_agent -L cpu_data_master_agent -L jtag_uart_avalon_jtag_slave_translator -L cpu_data_master_translator -L cpu -L rst_controller -L irq_mapper -L mm_interconnect_0 -L sys_clk_timer -L sem -L mem -L jtag_uart -L niosII_inst_reset_bfm -L niosII_inst_clk_bfm -L niosII_inst -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver $TOP_LEVEL_NAME
|
|
}
|
|
|
|
# ----------------------------------------
|
|
# Compile all the design files and elaborate the top level design
|
|
alias ld "
|
|
dev_com
|
|
com
|
|
elab
|
|
"
|
|
|
|
# ----------------------------------------
|
|
# Compile all the design files and elaborate the top level design with -novopt
|
|
alias ld_debug "
|
|
dev_com
|
|
com
|
|
elab_debug
|
|
"
|
|
|
|
# ----------------------------------------
|
|
# Print out user commmand line aliases
|
|
alias h {
|
|
echo "List Of Command Line Aliases"
|
|
echo
|
|
echo "file_copy -- Copy ROM/RAM files to simulation directory"
|
|
echo
|
|
echo "dev_com -- Compile device library files"
|
|
echo
|
|
echo "com -- Compile the design files in correct order"
|
|
echo
|
|
echo "elab -- Elaborate top level design"
|
|
echo
|
|
echo "elab_debug -- Elaborate the top level design with novopt option"
|
|
echo
|
|
echo "ld -- Compile all the design files and elaborate the top level design"
|
|
echo
|
|
echo "ld_debug -- Compile all the design files and elaborate the top level design with -novopt"
|
|
echo
|
|
echo
|
|
echo
|
|
echo "List Of Variables"
|
|
echo
|
|
echo "TOP_LEVEL_NAME -- Top level module name."
|
|
echo " For most designs, this should be overridden"
|
|
echo " to enable the elab/elab_debug aliases."
|
|
echo
|
|
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
|
|
echo
|
|
echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
|
|
echo
|
|
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
|
|
echo
|
|
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
|
|
echo
|
|
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
|
|
echo
|
|
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
|
|
echo
|
|
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
|
|
}
|
|
file_copy
|
|
h
|