199 lines
9.8 KiB
Bash
199 lines
9.8 KiB
Bash
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# (C) 2001-2023 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions and
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# other software and tools, and its AMPP partner logic functions, and
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# any output files any of the foregoing (including device programming
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# or simulation files), and any associated documentation or information
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# are expressly subject to the terms and conditions of the Altera
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# Program License Subscription Agreement, Altera MegaCore Function
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# License Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by Altera
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# or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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# ACDS 18.1 625 linux 2023.01.17.19:01:36
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# ----------------------------------------
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# vcs - auto-generated simulation script
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# ----------------------------------------
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# This script provides commands to simulate the following IP detected in
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# your Quartus project:
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# niosII_tb
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#
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# Altera recommends that you source this Quartus-generated IP simulation
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# script from your own customized top-level script, and avoid editing this
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# generated script.
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#
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# To write a top-level shell script that compiles Altera simulation libraries
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# and the Quartus-generated IP in your project, along with your design and
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# testbench files, follow the guidelines below.
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#
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# 1) Copy the shell script text from the TOP-LEVEL TEMPLATE section
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# below into a new file, e.g. named "vcs_sim.sh".
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#
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# 2) Copy the text from the DESIGN FILE LIST & OPTIONS TEMPLATE section into
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# a separate file, e.g. named "filelist.f".
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#
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# ----------------------------------------
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# # TOP-LEVEL TEMPLATE - BEGIN
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# #
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# # TOP_LEVEL_NAME is used in the Quartus-generated IP simulation script to
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# # set the top-level simulation or testbench module/entity name.
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# #
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# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
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# # construct paths to the files required to simulate the IP in your Quartus
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# # project. By default, the IP script assumes that you are launching the
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# # simulator from the IP script location. If launching from another
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# # location, set QSYS_SIMDIR to the output directory you specified when you
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# # generated the IP script, relative to the directory from which you launch
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# # the simulator.
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# #
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# # Source the Quartus-generated IP simulation script and do the following:
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# # - Compile the Quartus EDA simulation library and IP simulation files.
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# # - Specify TOP_LEVEL_NAME and QSYS_SIMDIR.
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# # - Compile the design and top-level simulation module/entity using
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# # information specified in "filelist.f".
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# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
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# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
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# # - Run the simulation.
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# #
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# source <script generation output directory>/synopsys/vcs/vcs_setup.sh \
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# TOP_LEVEL_NAME=<simulation top> \
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# QSYS_SIMDIR=<script generation output directory> \
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# USER_DEFINED_ELAB_OPTIONS="\"-f filelist.f\"" \
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# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
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# #
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# # TOP-LEVEL TEMPLATE - END
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# ----------------------------------------
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#
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# ----------------------------------------
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# # DESIGN FILE LIST & OPTIONS TEMPLATE - BEGIN
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# #
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# # Compile all design files and testbench files, including the top level.
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# # (These are all the files required for simulation other than the files
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# # compiled by the Quartus-generated IP simulation script)
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# #
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# +systemverilogext+.sv
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# <design and testbench files, compile-time options, elaboration options>
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# #
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# # DESIGN FILE LIST & OPTIONS TEMPLATE - END
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# ----------------------------------------
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#
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# IP SIMULATION SCRIPT
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# ----------------------------------------
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# If niosII_tb is one of several IP cores in your
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# Quartus project, you can generate a simulation script
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# suitable for inclusion in your top-level simulation
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# script by running the following command line:
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#
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# ip-setup-simulation --quartus-project=<quartus project>
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#
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# ip-setup-simulation will discover the Altera IP
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# within the Quartus project, and generate a unified
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# script which supports all the Altera IP within the design.
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# ----------------------------------------
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# ACDS 18.1 625 linux 2023.01.17.19:01:36
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# ----------------------------------------
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# initialize variables
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TOP_LEVEL_NAME="niosII_tb"
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QSYS_SIMDIR="./../../"
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QUARTUS_INSTALL_DIR="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/"
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SKIP_FILE_COPY=0
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SKIP_SIM=0
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USER_DEFINED_ELAB_OPTIONS=""
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USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
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# ----------------------------------------
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# overwrite variables - DO NOT MODIFY!
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# This block evaluates each command line argument, typically used for
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# overwriting variables. An example usage:
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# sh <simulator>_setup.sh SKIP_SIM=1
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for expression in "$@"; do
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eval $expression
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if [ $? -ne 0 ]; then
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echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
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exit $?
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fi
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done
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# ----------------------------------------
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# initialize simulation properties - DO NOT MODIFY!
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ELAB_OPTIONS=""
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SIM_OPTIONS=""
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if [[ `vcs -platform` != *"amd64"* ]]; then
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:
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else
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:
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fi
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# ----------------------------------------
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# copy RAM/ROM files to simulation directory
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if [ $SKIP_FILE_COPY -eq 0 ]; then
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cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
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cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
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cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
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cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
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cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
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cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
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cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
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cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
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cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
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cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
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fi
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vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
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$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/verbosity_pkg.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_synchronizer.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_irq_mapper.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/dec.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/periodram.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_jtag_uart.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu.v \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv \
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$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII.v \
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$QSYS_SIMDIR/niosII_tb/simulation/niosII_tb.v \
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-top $TOP_LEVEL_NAME
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# ----------------------------------------
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# simulate
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if [ $SKIP_SIM -eq 0 ]; then
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./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
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fi
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