2022-10-19 13:25:43 +03:00
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# (C) 2001-2018 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions and other
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# software and tools, and its AMPP partner logic functions, and any output
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# files from any of the foregoing (including device programming or simulation
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# files), and any associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License Subscription
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# Agreement, Intel FPGA IP License Agreement, or other applicable
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# license agreement, including, without limitation, that your use is for the
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# sole purpose of programming logic devices manufactured by Intel and sold by
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# Intel or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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2023-01-27 18:04:01 +03:00
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# +---------------------------------------------------
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# | Cut the async clear paths
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# +---------------------------------------------------
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set aclr_counter 0
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set clrn_counter 0
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set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
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set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
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set aclr_counter [get_collection_size $aclr_collection]
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set clrn_counter [get_collection_size $clrn_collection]
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if {$aclr_counter > 0} {
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set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
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}
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if {$clrn_counter > 0} {
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set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
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}
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