fpga-lab-2/Top/top.sv

module top
//(
//	input logic clk,
//	input logic train,
//	output logic green,
//	output logic red,
//	output logic yellow
//);
// 
//  niosII u0 (
//        .clk_clk           (clk),           //        clk.clk
//        .reset_reset_n     (1'b1),     //      reset.reset_n
//        .sem_export_train  (~train),  // sem_export.train
//        .sem_export_red    (red),    //           .red
//        .sem_export_yellow (yellow), //           .yellow
//        .sem_export_green  (green)   //           .green
//    );

(

// reset
nreset,

	//////////// CLOCK //////////
	CLOCK_50,
	CLOCK2_50,
	CLOCK3_50,

	//////////// LED //////////
	LEDG,
	LEDR,
	FOUTA
);

output							FOUTA;
//////////// CLOCK //////////
input 		          		CLOCK_50;
input 		          		CLOCK2_50;
input 		          		CLOCK3_50;
input nreset;

//////////// LED //////////
output		     [8:0]		LEDG;
output		    [17:0]		LEDR;

    niosII u0 (
        .clk_clk                          (CLOCK_50), //         clk.clk
        .conduit_end_writeresponsevalid_n (LEDG[0]),  // conduit_end.writeresponsevalid_n
        .reset_reset_n                    (nreset)      //       reset.reset_n
    );


assign LEDG[7:1] = 1'b0;
assign LEDR[17:0] = 1'b0;
assign FOUTA = LEDG[0];
	 
endmodule