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fpga-lab-2/Top/niosII/niosII.xml

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pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<?xml version="1.0" encoding="UTF-8"?>
<deploy
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
date="2022.12.24.02:16:58"
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
outputDirectory="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/">
<perimeter>
<parameter
name="AUTO_GENERATION_ID"
type="Integer"
defaultValue="0"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_UNIQUE_ID"
type="String"
defaultValue=""
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_FAMILY"
type="String"
defaultValue="Cyclone IV E"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE"
type="String"
defaultValue="EP4CE115F29C7"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_SPEEDGRADE"
type="String"
defaultValue="7"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_CLK_CLOCK_RATE"
type="Long"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_CLK_CLOCK_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_CLK_RESET_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<interface name="clk" kind="clock" start="0">
<property name="clockRate" value="50000000" />
<property name="externallyDriven" value="false" />
<property name="ptfSchematicName" value="" />
<port name="clk_clk" direction="input" role="clk" width="1" />
</interface>
<interface name="reset" kind="reset" start="0">
<property name="associatedClock" value="" />
<property name="synchronousEdges" value="NONE" />
<port name="reset_reset_n" direction="input" role="reset_n" width="1" />
</interface>
<interface name="sem_export" kind="conduit" start="0">
<property name="associatedClock" value="" />
<property name="associatedReset" value="reset" />
<port name="sem_export_train" direction="input" role="train" width="1" />
<port name="sem_export_red" direction="output" role="red" width="1" />
<port name="sem_export_yellow" direction="output" role="yellow" width="1" />
<port name="sem_export_green" direction="output" role="green" width="1" />
</interface>
</perimeter>
<entity
path=""
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
parameterizationKey="niosII:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=EP4CE115F29C7,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=7,AUTO_GENERATION_ID=1671833790,AUTO_UNIQUE_ID=(clock_source:18.1:clockFrequency=50000000,clockFrequencyKnown=true,inputClockFrequency=0,resetSynchronousEdges=NONE)(altera_nios2_gen2:18.1:AUTO_CLK_CLOCK_DOMAIN=1,AUTO_CLK_RESET_DOMAIN=1,AUTO_DEVICE=EP4CE115F29C7,AUTO_DEVICE_SPEEDGRADE=7,bht_ramBlockType=Automatic,breakAbsoluteAddr=133152,breakOffset=32,breakSlave=None,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,customInstSlavesSystemInfo=&lt;info/&gt;,customInstSlavesSystemInfo_nios_a=&lt;info/&gt;,customInstSlavesSystemInfo_nios_b=&lt;info/&gt;,customInstSlavesSystemInfo_nios_c=&lt;info/&gt;,dataAddrWidth=18,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;mem.s2&apos; start=&apos;0x0&apos; end=&apos;0x20000&apos; type=&apos;altera_avalon_onchip_memory2.s2&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x20800&apos; end=&apos;0x21000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;sem.ram_slave&apos; start=&apos;0x21000&apos; end=&apos;0x21040&apos; type=&apos;sem.ram_slave&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x21040&apos; end=&apos;0x21060&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;sem.ctl_slave&apos; start=&apos;0x21060&apos; end=&apos;0x21068&apos; type=&apos;sem.ctl_slave&apos; /&gt;&lt;slave name=&apos;jtag_uart.avalon_jtag_slave&apos; start=&apos;0x21068&apos; end=&apos;0x21070&apos; type=&apos;altera_avalon_jtag_uart.avalon_jtag_slave&apos; /&gt;&lt;/address-map&gt;,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_size=0,data_master_paddr_base=0,data_master_paddr_size=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=0,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=Cyclone IV E,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 H
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
instancePathKey="niosII"
kind="niosII"
version="1.0"
name="niosII">
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<parameter name="AUTO_GENERATION_ID" value="1671833790" />
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<parameter name="AUTO_DEVICE" value="EP4CE115F29C7" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
<parameter name="AUTO_UNIQUE_ID" value="" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/niosII.v"
type="VERILOG" />
</generatedFiles>
<childGeneratedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu.v"
type="VERILOG" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu.sdc"
type="SDC"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_sysclk.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_tck.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_wrapper.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_ociram_default_contents.mif"
type="MIF"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_a.mif"
type="MIF"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_b.mif"
type="MIF"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_jtag_uart.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mem.hex"
type="HEX"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mem.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/dec.sv"
type="SYSTEM_VERILOG"
attributes="TOP_LEVEL_FILE" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/periodram.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_sys_clk_timer.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0.v"
type="VERILOG" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_master_translator.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_slave_translator.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_master_agent.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_slave_agent.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_avalon_sc_fifo.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_001.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_002.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_004.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_008.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_demux.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v"
type="VERILOG" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_irq_mapper.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_reset_controller.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_reset_synchronizer.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_reset_controller.sdc"
type="SDC"
attributes="" />
</childGeneratedFiles>
<sourceFiles>
<file path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII.qsys" />
</sourceFiles>
<childSourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
<file path="C:/Software/FPGA/iu3-31m/Lab2/Top/Semafor_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_irq_mapper/altera_irq_mapper_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
</childSourceFiles>
<messages>
<message level="Debug" culprit="niosII">queue size: 0 starting:niosII "niosII"</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug">Transform: CustomInstructionTransform</message>
<message level="Debug">No custom instruction connections, skipping transform </message>
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>6</b> modules, <b>25</b> connections]]></message>
<message level="Debug">Transform: MMTransform</message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>6</b> modules, <b>23</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
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<message level="Debug" culprit="merlin_translator_transform"><![CDATA[After transform: <b>15</b> modules, <b>59</b> connections]]></message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform merlin_domain_transform not run on matched interfaces cpu.data_master and cpu_data_master_translator.avalon_anti_master_0</message>
<message level="Debug">Transform merlin_domain_transform not run on matched interfaces cpu.instruction_master and cpu_instruction_master_translator.avalon_anti_master_0</message>
<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="min"></message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave</message>
<message level="Debug">Transform merlin_domain_transform not run on matched interfaces sem_ctl_slave_translator.avalon_anti_slave_0 and sem.ctl_slave</message>
<message level="Debug">Transform merlin_domain_transform not run on matched interfaces cpu_debug_mem_slave_translator.avalon_anti_slave_0 and cpu.debug_mem_slave</message>
<message level="Debug">Transform merlin_domain_transform not run on matched interfaces sem_ram_slave_translator.avalon_anti_slave_0 and sem.ram_slave</message>
<message level="Debug">Transform merlin_domain_transform not run on matched interfaces sys_clk_timer_s1_translator.avalon_anti_slave_0 and sys_clk_timer.s1</message>
<message level="Debug">Transform merlin_domain_transform not run on matched interfaces mem_s2_translator.avalon_anti_slave_0 and mem.s2</message>
<message level="Debug">Transform merlin_domain_transform not run on matched interfaces mem_s1_translator.avalon_anti_slave_0 and mem.s1</message>
<message level="Debug" culprit="merlin_domain_transform"><![CDATA[After transform: <b>32</b> modules, <b>174</b> connections]]></message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug" culprit="merlin_router_transform"><![CDATA[After transform: <b>41</b> modules, <b>210</b> connections]]></message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug" culprit="merlin_network_to_switch_transform"><![CDATA[After transform: <b>58</b> modules, <b>253</b> connections]]></message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug" culprit="merlin_clock_and_reset_bridge_transform"><![CDATA[After transform: <b>60</b> modules, <b>312</b> connections]]></message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>7</b> modules, <b>29</b> connections]]></message>
<message level="Debug" culprit="merlin_mm_transform"><![CDATA[After transform: <b>7</b> modules, <b>29</b> connections]]></message>
<message level="Debug">Transform: InterruptMapperTransform</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug" culprit="merlin_interrupt_mapper_transform"><![CDATA[After transform: <b>8</b> modules, <b>33</b> connections]]></message>
<message level="Debug">Transform: InterruptSyncTransform</message>
<message level="Debug">Transform: InterruptFanoutTransform</message>
<message level="Debug">Transform: AvalonStreamingTransform</message>
<message level="Debug">Transform: ResetAdaptation</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug" culprit="reset_adaptation_transform"><![CDATA[After transform: <b>10</b> modules, <b>35</b> connections]]></message>
<message level="Debug" culprit="niosII"><![CDATA["<b>niosII</b>" reuses <b>altera_nios2_gen2</b> "<b>submodules/niosII_cpu</b>"]]></message>
<message level="Debug" culprit="niosII"><![CDATA["<b>niosII</b>" reuses <b>altera_avalon_jtag_uart</b> "<b>submodules/niosII_jtag_uart</b>"]]></message>
<message level="Debug" culprit="niosII"><![CDATA["<b>niosII</b>" reuses <b>altera_avalon_onchip_memory2</b> "<b>submodules/niosII_mem</b>"]]></message>
pt3.12 modelled
2022-10-24 22:35:24 +03:00
<message level="Debug" culprit="niosII"><![CDATA["<b>niosII</b>" reuses <b>sem</b> "<b>submodules/dec</b>"]]></message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Debug" culprit="niosII"><![CDATA["<b>niosII</b>" reuses <b>altera_avalon_timer</b> "<b>submodules/niosII_sys_clk_timer</b>"]]></message>
<message level="Debug" culprit="niosII"><![CDATA["<b>niosII</b>" reuses <b>altera_mm_interconnect</b> "<b>submodules/niosII_mm_interconnect_0</b>"]]></message>
<message level="Debug" culprit="niosII"><![CDATA["<b>niosII</b>" reuses <b>altera_irq_mapper</b> "<b>submodules/niosII_irq_mapper</b>"]]></message>
<message level="Debug" culprit="niosII"><![CDATA["<b>niosII</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 7 starting:altera_nios2_gen2 "submodules/niosII_cpu"</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug">Transform: CustomInstructionTransform</message>
<message level="Debug">No custom instruction connections, skipping transform </message>
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
<message level="Debug">Transform: MMTransform</message>
<message level="Debug">Transform: InterruptMapperTransform</message>
<message level="Debug">Transform: InterruptSyncTransform</message>
<message level="Debug">Transform: InterruptFanoutTransform</message>
<message level="Debug">Transform: AvalonStreamingTransform</message>
<message level="Debug">Transform: ResetAdaptation</message>
<message level="Debug" culprit="cpu"><![CDATA["<b>cpu</b>" reuses <b>altera_nios2_gen2_unit</b> "<b>submodules/niosII_cpu_cpu</b>"]]></message>
<message level="Info" culprit="cpu"><![CDATA["<b>niosII</b>" instantiated <b>altera_nios2_gen2</b> "<b>cpu</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu"</message>
<message level="Info" culprit="cpu">Starting RTL generation for module 'niosII_cpu_cpu'</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Info" culprit="cpu"> Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ]</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:53 (*) Starting Nios II generation</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:53 (*) Checking for plaintext license.</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) Defaulting to contents of LM_LICENSE_FILE environment variable</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) LM_LICENSE_FILE environment variable is empty</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) Plaintext license not found.</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) No license required to generate encrypted Nios II/e.</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) Elaborating CPU configuration settings</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) Creating all objects for CPU</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:55 (*) Generating RTL from CPU objects</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:55 (*) Creating plain-text RTL</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:56 (*) Done Nios II generation</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Info" culprit="cpu">Done RTL generation for module 'niosII_cpu_cpu'</message>
<message level="Info" culprit="cpu"><![CDATA["<b>cpu</b>" instantiated <b>altera_nios2_gen2_unit</b> "<b>cpu</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 7 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart"</message>
<message level="Info" culprit="jtag_uart">Starting RTL generation for module 'niosII_jtag_uart'</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Info" culprit="jtag_uart"> Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ]</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Info" culprit="jtag_uart">Done RTL generation for module 'niosII_jtag_uart'</message>
<message level="Info" culprit="jtag_uart"><![CDATA["<b>niosII</b>" instantiated <b>altera_avalon_jtag_uart</b> "<b>jtag_uart</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 6 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem"</message>
<message level="Info" culprit="mem">Starting RTL generation for module 'niosII_mem'</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Info" culprit="mem"> Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ]</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Info" culprit="mem">Done RTL generation for module 'niosII_mem'</message>
<message level="Info" culprit="mem"><![CDATA["<b>niosII</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>mem</b>"]]></message>
pt3.12 modelled
2022-10-24 22:35:24 +03:00
<message level="Debug" culprit="niosII">queue size: 5 starting:sem "submodules/dec"</message>
<message level="Info" culprit="sem"><![CDATA["<b>niosII</b>" instantiated <b>sem</b> "<b>sem</b>"]]></message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Debug" culprit="niosII">queue size: 4 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer"</message>
<message level="Info" culprit="sys_clk_timer">Starting RTL generation for module 'niosII_sys_clk_timer'</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Info" culprit="sys_clk_timer"> Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ]</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Info" culprit="sys_clk_timer">Done RTL generation for module 'niosII_sys_clk_timer'</message>
<message level="Info" culprit="sys_clk_timer"><![CDATA["<b>niosII</b>" instantiated <b>altera_avalon_timer</b> "<b>sys_clk_timer</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 3 starting:altera_mm_interconnect "submodules/niosII_mm_interconnect_0"</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug">Transform: CustomInstructionTransform</message>
<message level="Debug">No custom instruction connections, skipping transform </message>
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: MMTransform</message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InterruptMapperTransform</message>
<message level="Debug">Transform: InterruptSyncTransform</message>
<message level="Debug">Transform: InterruptFanoutTransform</message>
<message level="Debug">Transform: AvalonStreamingTransform</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Info" culprit="avalon_st_adapter">Inserting error_adapter: error_adapter_0</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Debug" culprit="avalon_st_adapter.clk_bridge_0">Timing: ELA:1/0.001s</message>
<message level="Debug" culprit="avalon_st_adapter.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
<message level="Debug" culprit="avalon_st_adapter.error_adapter_0">Timing: ELA:1/0.027s</message>
<message level="Debug" culprit="avalon_st_adapter">Timing: COM:3/0.052s/0.076s</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Info" culprit="avalon_st_adapter_001">Inserting error_adapter: error_adapter_0</message>
ram32ok
2022-12-22 22:27:05 +03:00
<message level="Debug" culprit="avalon_st_adapter_001.clk_bridge_0">Timing: ELA:1/0.001s</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Debug" culprit="avalon_st_adapter_001.rst_bridge_0">Timing: ELA:2/0.001s/0.002s</message>
<message level="Debug" culprit="avalon_st_adapter_001.error_adapter_0">Timing: ELA:1/0.011s</message>
<message level="Debug" culprit="avalon_st_adapter_001">Timing: COM:3/0.021s/0.022s</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Info" culprit="avalon_st_adapter_002">Inserting error_adapter: error_adapter_0</message>
<message level="Debug" culprit="avalon_st_adapter_002.clk_bridge_0">Timing: ELA:1/0.000s</message>
ram32ok
2022-12-22 22:27:05 +03:00
<message level="Debug" culprit="avalon_st_adapter_002.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Debug" culprit="avalon_st_adapter_002.error_adapter_0">Timing: ELA:1/0.009s</message>
<message level="Debug" culprit="avalon_st_adapter_002">Timing: COM:3/0.019s/0.025s</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Info" culprit="avalon_st_adapter_003">Inserting error_adapter: error_adapter_0</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Debug" culprit="avalon_st_adapter_003.clk_bridge_0">Timing: ELA:1/0.000s</message>
<message level="Debug" culprit="avalon_st_adapter_003.rst_bridge_0">Timing: ELA:2/0.001s/0.002s</message>
<message level="Debug" culprit="avalon_st_adapter_003.error_adapter_0">Timing: ELA:1/0.011s</message>
<message level="Debug" culprit="avalon_st_adapter_003">Timing: COM:3/0.021s/0.024s</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Info" culprit="avalon_st_adapter_004">Inserting error_adapter: error_adapter_0</message>
ram32ok
2022-12-22 22:27:05 +03:00
<message level="Debug" culprit="avalon_st_adapter_004.clk_bridge_0">Timing: ELA:1/0.001s</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Debug" culprit="avalon_st_adapter_004.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
<message level="Debug" culprit="avalon_st_adapter_004.error_adapter_0">Timing: ELA:1/0.010s</message>
<message level="Debug" culprit="avalon_st_adapter_004">Timing: COM:3/0.024s/0.032s</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Info" culprit="avalon_st_adapter_005">Inserting error_adapter: error_adapter_0</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Debug" culprit="avalon_st_adapter_005.clk_bridge_0">Timing: ELA:1/0.000s</message>
<message level="Debug" culprit="avalon_st_adapter_005.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
<message level="Debug" culprit="avalon_st_adapter_005.error_adapter_0">Timing: ELA:1/0.008s</message>
<message level="Debug" culprit="avalon_st_adapter_005">Timing: COM:3/0.019s/0.022s</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Info" culprit="avalon_st_adapter_006">Inserting error_adapter: error_adapter_0</message>
<message level="Debug" culprit="avalon_st_adapter_006.clk_bridge_0">Timing: ELA:1/0.000s</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Debug" culprit="avalon_st_adapter_006.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
<message level="Debug" culprit="avalon_st_adapter_006.error_adapter_0">Timing: ELA:1/0.011s</message>
<message level="Debug" culprit="avalon_st_adapter_006">Timing: COM:3/0.022s/0.028s</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message
level="Debug"
culprit="com_altera_sopcmodel_transforms_avalonst_AvalonStreamingTransform"><![CDATA[After transform: <b>61</b> modules, <b>199</b> connections]]></message>
<message level="Debug">Transform: ResetAdaptation</message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_001</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_002</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_002</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_004</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_002</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_002</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_002</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_008</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_demux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_demux_001</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_mux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_mux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_mux_002</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_mux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_mux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_mux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_mux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_demux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_demux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_demux_001</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_demux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_demux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_demux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_demux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_mux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_mux_001</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
<message level="Info" culprit="mm_interconnect_0"><![CDATA["<b>niosII</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 58 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
<message level="Info" culprit="cpu_data_master_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>cpu_data_master_translator</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 56 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
<message level="Info" culprit="jtag_uart_avalon_jtag_slave_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>jtag_uart_avalon_jtag_slave_translator</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 49 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
<message level="Info" culprit="cpu_data_master_agent"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_agent</b> "<b>cpu_data_master_agent</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 47 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
<message level="Info" culprit="jtag_uart_avalon_jtag_slave_agent"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>jtag_uart_avalon_jtag_slave_agent</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 46 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
<message level="Info" culprit="jtag_uart_avalon_jtag_slave_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>jtag_uart_avalon_jtag_slave_agent_rsp_fifo</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 33 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router"</message>
<message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 32 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001"</message>
<message level="Info" culprit="router_001"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 31 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"</message>
<message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 29 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_004"</message>
<message level="Info" culprit="router_004"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_004</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 25 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_008"</message>
<message level="Info" culprit="router_008"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_008</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 24 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux"</message>
<message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 23 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001"</message>
<message level="Info" culprit="cmd_demux_001"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_001</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 22 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"</message>
<message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 20 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_002"</message>
<message level="Info" culprit="cmd_mux_002"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_002</b>"]]></message>
<message level="Info"><![CDATA[Reusing file <b>C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
<message level="Debug" culprit="niosII">queue size: 15 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"</message>
<message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 8 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux"</message>
<message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
<message level="Info"><![CDATA[Reusing file <b>C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
<message level="Debug" culprit="niosII">queue size: 7 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux_001"</message>
<message level="Info" culprit="rsp_mux_001"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_001</b>"]]></message>
<message level="Info"><![CDATA[Reusing file <b>C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
<message level="Debug" culprit="niosII">queue size: 6 starting:altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug">Transform: CustomInstructionTransform</message>
<message level="Debug">No custom instruction connections, skipping transform </message>
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
<message level="Debug">Transform: MMTransform</message>
<message level="Debug">Transform: InterruptMapperTransform</message>
<message level="Debug">Transform: InterruptSyncTransform</message>
<message level="Debug">Transform: InterruptFanoutTransform</message>
<message level="Debug">Transform: AvalonStreamingTransform</message>
<message level="Debug">Transform: ResetAdaptation</message>
<message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0</b>"]]></message>
<message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 0 starting:error_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0"</message>
<message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 61 starting:altera_irq_mapper "submodules/niosII_irq_mapper"</message>
<message level="Info" culprit="irq_mapper"><![CDATA["<b>niosII</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 60 starting:altera_reset_controller "submodules/altera_reset_controller"</message>
<message level="Info" culprit="rst_controller"><![CDATA["<b>niosII</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
ram32ok
2022-12-22 22:27:05 +03:00
parameterizationKey="altera_nios2_gen2:18.1:AUTO_CLK_CLOCK_DOMAIN=1,AUTO_CLK_RESET_DOMAIN=1,AUTO_DEVICE=EP4CE115F29C7,AUTO_DEVICE_SPEEDGRADE=7,bht_ramBlockType=Automatic,breakAbsoluteAddr=133152,breakOffset=32,breakSlave=None,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,customInstSlavesSystemInfo=&lt;info/&gt;,customInstSlavesSystemInfo_nios_a=&lt;info/&gt;,customInstSlavesSystemInfo_nios_b=&lt;info/&gt;,customInstSlavesSystemInfo_nios_c=&lt;info/&gt;,dataAddrWidth=18,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;mem.s2&apos; start=&apos;0x0&apos; end=&apos;0x20000&apos; type=&apos;altera_avalon_onchip_memory2.s2&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x20800&apos; end=&apos;0x21000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;sem.ram_slave&apos; start=&apos;0x21000&apos; end=&apos;0x21040&apos; type=&apos;sem.ram_slave&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x21040&apos; end=&apos;0x21060&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;sem.ctl_slave&apos; start=&apos;0x21060&apos; end=&apos;0x21068&apos; type=&apos;sem.ctl_slave&apos; /&gt;&lt;slave name=&apos;jtag_uart.avalon_jtag_slave&apos; start=&apos;0x21068&apos; end=&apos;0x21070&apos; type=&apos;altera_avalon_jtag_uart.avalon_jtag_slave&apos; /&gt;&lt;/address-map&gt;,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_size=0,data_master_paddr_base=0,data_master_paddr_size=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=0,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=Cyclone IV E,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FI
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
instancePathKey="niosII:.:cpu"
kind="altera_nios2_gen2"
version="18.1"
name="niosII_cpu">
<parameter name="mpx_enabled" value="false" />
<parameter name="ocimem_ramBlockType" value="Automatic" />
<parameter name="dcache_victim_buf_impl" value="ram" />
<parameter name="setting_exportPCB" value="false" />
<parameter name="setting_ic_ecc_present" value="true" />
<parameter name="dcache_size_derived" value="2048" />
<parameter name="mmu_udtlbNumEntries" value="6" />
<parameter
name="deviceFeaturesSystemInfo"
value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPO
<parameter name="bht_ramBlockType" value="Automatic" />
<parameter name="mmu_TLBMissExcSlave" value="None" />
<parameter name="impl" value="Tiny" />
<parameter name="setting_branchpredictiontype" value="Dynamic" />
<parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
<parameter name="breakOffset" value="32" />
<parameter name="setting_activateTrace" value="false" />
<parameter name="debug_offchiptrace" value="false" />
<parameter name="setting_avalonDebugPortPresent" value="false" />
<parameter name="dcache_numTCDM" value="0" />
<parameter name="setting_tmr_output_disable" value="false" />
<parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
<parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
<parameter name="debug_debugReqSignals" value="false" />
<parameter name="AUTO_DEVICE" value="EP4CE115F29C7" />
<parameter name="instruction_master_high_performance_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
<parameter name="mmu_processIDNumBits" value="8" />
<parameter name="debug_onchiptrace" value="false" />
<parameter name="setting_rf_ecc_present" value="true" />
<parameter name="ocimem_ramInit" value="false" />
<parameter name="internalIrqMaskSystemInfo" value="3" />
<parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
<parameter name="exceptionAbsoluteAddr" value="32" />
<parameter name="icache_size" value="4096" />
<parameter
name="dataSlaveMapParam"
ram32ok
2022-12-22 22:27:05 +03:00
value="&lt;address-map&gt;&lt;slave name=&apos;mem.s2&apos; start=&apos;0x0&apos; end=&apos;0x20000&apos; type=&apos;altera_avalon_onchip_memory2.s2&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x20800&apos; end=&apos;0x21000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;sem.ram_slave&apos; start=&apos;0x21000&apos; end=&apos;0x21040&apos; type=&apos;sem.ram_slave&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x21040&apos; end=&apos;0x21060&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;sem.ctl_slave&apos; start=&apos;0x21060&apos; end=&apos;0x21068&apos; type=&apos;sem.ctl_slave&apos; /&gt;&lt;slave name=&apos;jtag_uart.avalon_jtag_slave&apos; start=&apos;0x21068&apos; end=&apos;0x21070&apos; type=&apos;altera_avalon_jtag_uart.avalon_jtag_slave&apos; /&gt;&lt;/address-map&gt;" />
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<parameter name="mpu_enabled" value="false" />
<parameter name="flash_instruction_master_paddr_size" value="0" />
<parameter name="setting_ecc_present" value="false" />
<parameter name="stratix_dspblock_shift_mul" value="false" />
<parameter name="shift_rot_impl" value="1" />
<parameter name="setting_ioregionBypassDCache" value="false" />
<parameter name="register_file_por" value="false" />
<parameter name="faAddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="exceptionSlave" value="mem.s1" />
<parameter name="debug_triggerArming" value="true" />
<parameter name="debug_OCIOnchipTrace" value="_128" />
<parameter name="dataAddrWidth" value="18" />
<parameter name="setting_bit31BypassDCache" value="false" />
<parameter name="instAddrWidth" value="18" />
<parameter name="io_regionbase" value="0" />
<parameter name="mul_32_impl" value="2" />
<parameter name="translate_on" value=" &quot;synthesis translate_on&quot; " />
<parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
<parameter name="mmu_autoAssignTlbPtrSz" value="true" />
<parameter name="instruction_master_paddr_base" value="0" />
<parameter name="userDefinedSettings" value="" />
<parameter name="mul_64_impl" value="0" />
<parameter name="clockFrequency" value="50000000" />
<parameter name="resetOffset" value="0" />
<parameter name="dcache_ramBlockType" value="Automatic" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="mul_shift_choice" value="0" />
<parameter name="tightlyCoupledDataMaster2MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
<parameter name="setting_asic_third_party_synthesis" value="false" />
<parameter name="mpu_minInstRegionSize" value="12" />
<parameter name="setting_exportdebuginfo" value="false" />
<parameter name="mmu_tlbPtrSz" value="7" />
<parameter name="resetSlave" value="mem.s1" />
<parameter name="dcache_bursts_derived" value="false" />
<parameter name="multiplierType" value="no_mul" />
<parameter name="debug_traceStorage" value="onchip_trace" />
<parameter name="setting_preciseIllegalMemAccessException" value="false" />
<parameter name="fa_cache_linesize" value="0" />
<parameter name="data_master_paddr_size" value="0" />
<parameter name="setting_HBreakTest" value="false" />
<parameter name="setting_disableocitrace" value="false" />
<parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
<parameter name="setting_showInternalSettings" value="false" />
<parameter name="instructionMasterHighPerformanceMapParam" value="" />
<parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
<parameter name="debug_datatrigger" value="0" />
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
<parameter name="debug_enabled" value="true" />
<parameter name="setting_export_large_RAMs" value="false" />
<parameter name="setting_dc_ecc_present" value="true" />
<parameter name="dividerType" value="no_div" />
<parameter name="setting_exportvectors" value="false" />
<parameter name="breakSlave_derived" value="cpu.debug_mem_slave" />
<parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
<parameter name="mmu_ramBlockType" value="Automatic" />
<parameter name="cdx_enabled" value="false" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
<parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
<parameter name="tracefilename" value="" />
<parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
<parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
<parameter name="setting_oci_version" value="1" />
<parameter name="icache_burstType" value="None" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="setting_disable_tmr_inj" value="false" />
<parameter name="instruction_master_high_performance_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
<parameter name="regfile_ramBlockType" value="Automatic" />
<parameter name="dcache_size" value="2048" />
<parameter name="breakSlave" value="None" />
<parameter name="exceptionOffset" value="32" />
<parameter name="tightlyCoupledDataMaster0MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
<parameter name="breakAbsoluteAddr" value="133152" />
<parameter name="setting_ecc_sim_test_ports" value="false" />
<parameter name="setting_showUnpublishedSettings" value="false" />
<parameter name="master_addr_map" value="false" />
<parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
<parameter name="resetAbsoluteAddr" value="0" />
<parameter name="cpuArchRev" value="1" />
<parameter name="setting_dtcm_ecc_present" value="true" />
<parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
<parameter name="setting_interruptControllerType" value="Internal" />
<parameter name="dcache_tagramBlockType" value="Automatic" />
<parameter name="debug_insttrace" value="false" />
<parameter name="setting_itcm_ecc_present" value="true" />
<parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
<parameter name="mmu_TLBMissExcAbsAddr" value="0" />
<parameter name="mpu_useLimit" value="false" />
<parameter name="icache_numTCIM" value="0" />
<parameter name="setting_usedesignware" value="false" />
<parameter name="tightlyCoupledDataMaster3MapParam" value="" />
<parameter name="instruction_master_paddr_size" value="0" />
<parameter name="mmu_TLBMissExcOffset" value="0" />
<parameter name="mmu_enabled" value="false" />
<parameter name="mmu_uitlbNumEntries" value="4" />
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
<parameter name="setting_activateTestEndChecker" value="false" />
<parameter name="cpuID" value="0" />
<parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
<parameter name="setting_asic_enabled" value="false" />
<parameter name="setting_HDLSimCachesCleared" value="true" />
<parameter name="setting_asic_add_scan_mode_input" value="false" />
<parameter name="setting_shadowRegisterSets" value="0" />
<parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
<parameter name="icache_ramBlockType" value="Automatic" />
<parameter name="faSlaveMapParam" value="" />
<parameter name="setting_clearXBitsLDNonBypass" value="true" />
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
<parameter name="fa_cache_line" value="2" />
<parameter name="debug_assignJtagInstanceID" value="false" />
<parameter name="setting_activateMonitors" value="true" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
<parameter name="setting_allow_break_inst" value="false" />
<parameter name="io_regionsize" value="0" />
<parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
<parameter name="translate_off" value=" &quot;synthesis translate_off&quot; " />
<parameter name="mpu_numOfInstRegion" value="8" />
<parameter name="flash_instruction_master_paddr_base" value="0" />
<parameter name="cpuReset" value="false" />
<parameter name="setting_removeRAMinit" value="false" />
<parameter name="icache_tagramBlockType" value="Automatic" />
<parameter name="setting_mmu_ecc_present" value="true" />
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
<parameter name="debug_datatrace" value="false" />
<parameter name="debug_hwbreakpoint" value="0" />
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
<parameter name="setting_bigEndian" value="false" />
<parameter name="mpu_minDataRegionSize" value="12" />
<parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
<parameter name="debug_jtagInstanceID" value="0" />
<parameter name="setting_breakslaveoveride" value="false" />
<parameter name="debug_traceType" value="none" />
<parameter name="setting_alwaysEncrypt" value="true" />
<parameter name="setting_oci_export_jtag_signals" value="false" />
<parameter name="dcache_lineSize_derived" value="32" />
<parameter name="deviceFamilyName" value="Cyclone IV E" />
<parameter name="tightlyCoupledDataMaster1MapParam" value="" />
<parameter name="setting_support31bitdcachebypass" value="true" />
<parameter
name="instSlaveMapParam"
value="&lt;address-map&gt;&lt;slave name=&apos;mem.s1&apos; start=&apos;0x0&apos; end=&apos;0x20000&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x20800&apos; end=&apos;0x21000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;/address-map&gt;" />
<parameter name="setting_bhtPtrSz" value="8" />
<parameter name="setting_exportHostDebugPort" value="false" />
<parameter name="tmr_enabled" value="false" />
<parameter name="data_master_paddr_base" value="0" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="mpu_numOfDataRegion" value="8" />
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
<parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
<parameter name="dcache_bursts" value="false" />
<parameter name="setting_asic_synopsys_translate_on_off" value="false" />
<parameter name="setting_fast_register_read" value="false" />
<parameter name="mmu_tlbNumWays" value="16" />
<parameter name="shifterType" value="medium_le_shift" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu.v"
type="VERILOG" />
</generatedFiles>
<childGeneratedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu.sdc"
type="SDC"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_sysclk.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_tck.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_wrapper.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_ociram_default_contents.mif"
type="MIF"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_a.mif"
type="MIF"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_b.mif"
type="MIF"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v"
type="VERILOG"
attributes="" />
</childGeneratedFiles>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_hw.tcl" />
</sourceFiles>
<childSourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
</childSourceFiles>
<instantiator instantiator="niosII" as="cpu" />
<messages>
<message level="Debug" culprit="niosII">queue size: 7 starting:altera_nios2_gen2 "submodules/niosII_cpu"</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug">Transform: CustomInstructionTransform</message>
<message level="Debug">No custom instruction connections, skipping transform </message>
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
<message level="Debug">Transform: MMTransform</message>
<message level="Debug">Transform: InterruptMapperTransform</message>
<message level="Debug">Transform: InterruptSyncTransform</message>
<message level="Debug">Transform: InterruptFanoutTransform</message>
<message level="Debug">Transform: AvalonStreamingTransform</message>
<message level="Debug">Transform: ResetAdaptation</message>
<message level="Debug" culprit="cpu"><![CDATA["<b>cpu</b>" reuses <b>altera_nios2_gen2_unit</b> "<b>submodules/niosII_cpu_cpu</b>"]]></message>
<message level="Info" culprit="cpu"><![CDATA["<b>niosII</b>" instantiated <b>altera_nios2_gen2</b> "<b>cpu</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu"</message>
<message level="Info" culprit="cpu">Starting RTL generation for module 'niosII_cpu_cpu'</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Info" culprit="cpu"> Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ]</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:53 (*) Starting Nios II generation</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:53 (*) Checking for plaintext license.</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) Defaulting to contents of LM_LICENSE_FILE environment variable</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) LM_LICENSE_FILE environment variable is empty</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) Plaintext license not found.</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) No license required to generate encrypted Nios II/e.</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) Elaborating CPU configuration settings</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) Creating all objects for CPU</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:55 (*) Generating RTL from CPU objects</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:55 (*) Creating plain-text RTL</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:56 (*) Done Nios II generation</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Info" culprit="cpu">Done RTL generation for module 'niosII_cpu_cpu'</message>
<message level="Info" culprit="cpu"><![CDATA["<b>cpu</b>" instantiated <b>altera_nios2_gen2_unit</b> "<b>cpu</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_avalon_jtag_uart:18.1:allowMultipleConnections=false,avalonSpec=2.0,clkFreq=50000000,enableInteractiveInput=false,enableInteractiveOutput=false,hubInstanceID=0,legacySignalAllow=false,readBufferDepth=64,readIRQThreshold=8,simInputCharacterStream=,simInteractiveOptions=NO_INTERACTIVE_WINDOWS,useRegistersForReadBuffer=false,useRegistersForWriteBuffer=false,useRelativePathForSimFile=false,writeBufferDepth=64,writeIRQThreshold=8"
instancePathKey="niosII:.:jtag_uart"
kind="altera_avalon_jtag_uart"
version="18.1"
name="niosII_jtag_uart">
<parameter name="readBufferDepth" value="64" />
<parameter name="clkFreq" value="50000000" />
<parameter name="useRelativePathForSimFile" value="false" />
<parameter name="hubInstanceID" value="0" />
<parameter name="enableInteractiveInput" value="false" />
<parameter name="avalonSpec" value="2.0" />
<parameter name="simInputCharacterStream" value="" />
<parameter name="readIRQThreshold" value="8" />
<parameter name="useRegistersForWriteBuffer" value="false" />
<parameter name="useRegistersForReadBuffer" value="false" />
<parameter name="simInteractiveOptions" value="NO_INTERACTIVE_WINDOWS" />
<parameter name="enableInteractiveOutput" value="false" />
<parameter name="writeIRQThreshold" value="8" />
<parameter name="writeBufferDepth" value="64" />
<parameter name="allowMultipleConnections" value="false" />
<parameter name="legacySignalAllow" value="false" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_jtag_uart.v"
type="VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="niosII" as="jtag_uart" />
<messages>
<message level="Debug" culprit="niosII">queue size: 7 starting:altera_avalon_jtag_uart "submodules/niosII_jtag_uart"</message>
<message level="Info" culprit="jtag_uart">Starting RTL generation for module 'niosII_jtag_uart'</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Info" culprit="jtag_uart"> Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosII_jtag_uart --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0031_jtag_uart_gen//niosII_jtag_uart_component_configuration.pl --do_build_sim=0 ]</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Info" culprit="jtag_uart">Done RTL generation for module 'niosII_jtag_uart'</message>
<message level="Info" culprit="jtag_uart"><![CDATA["<b>niosII</b>" instantiated <b>altera_avalon_jtag_uart</b> "<b>jtag_uart</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_avalon_onchip_memory2:18.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=niosII_mem,blockType=AUTO,copyInitFile=false,dataWidth=32,dataWidth2=32,derived_enableDiffWidth=false,derived_gui_ram_block_type=Automatic,derived_init_file_name=niosII_mem.hex,derived_is_hardcopy=false,derived_set_addr_width=15,derived_set_addr_width2=15,derived_set_data_width=32,derived_set_data_width2=32,derived_singleClockOperation=true,deviceFamily=Cyclone IV E,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1
instancePathKey="niosII:.:mem"
kind="altera_avalon_onchip_memory2"
version="18.1"
name="niosII_mem">
<parameter name="derived_singleClockOperation" value="true" />
<parameter name="derived_is_hardcopy" value="false" />
<parameter
name="deviceFeatures"
value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPO
<parameter name="autoInitializationFileName" value="niosII_mem" />
<parameter name="derived_gui_ram_block_type" value="Automatic" />
<parameter name="enPRInitMode" value="false" />
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
<parameter name="dualPort" value="true" />
<parameter name="derived_set_addr_width2" value="15" />
<parameter name="dataWidth" value="32" />
<parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="derived_set_addr_width" value="15" />
<parameter name="derived_init_file_name" value="niosII_mem.hex" />
<parameter name="initializationFileName" value="onchip_mem.hex" />
<parameter name="singleClockOperation" value="true" />
<parameter name="derived_set_data_width2" value="32" />
<parameter name="readDuringWriteMode" value="DONT_CARE" />
<parameter name="blockType" value="AUTO" />
<parameter name="derived_enableDiffWidth" value="false" />
<parameter name="useNonDefaultInitFile" value="false" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="simMemInitOnlyFilename" value="0" />
<parameter name="copyInitFile" value="false" />
<parameter name="deviceFamily" value="Cyclone IV E" />
<parameter name="simAllowMRAMContentsFile" value="false" />
<parameter name="ecc_enabled" value="false" />
<parameter name="derived_set_data_width" value="32" />
<parameter name="instanceID" value="NONE" />
<parameter name="memorySize" value="131072" />
<parameter name="dataWidth2" value="32" />
<parameter name="enableDiffWidth" value="false" />
<parameter name="initMemContent" value="true" />
<parameter name="slave1Latency" value="1" />
<parameter name="slave2Latency" value="1" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mem.hex"
type="HEX"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mem.v"
type="VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="niosII" as="mem" />
<messages>
<message level="Debug" culprit="niosII">queue size: 6 starting:altera_avalon_onchip_memory2 "submodules/niosII_mem"</message>
<message level="Info" culprit="mem">Starting RTL generation for module 'niosII_mem'</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Info" culprit="mem"> Generation command is [exec C:/software/intelfpga_lite/18.1/quartus/bin64/perl/bin/perl.exe -I C:/software/intelfpga_lite/18.1/quartus/bin64/perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosII_mem --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0032_mem_gen//niosII_mem_component_configuration.pl --do_build_sim=0 ]</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Info" culprit="mem">Done RTL generation for module 'niosII_mem'</message>
<message level="Info" culprit="mem"><![CDATA["<b>niosII</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>mem</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
sem ram widening correct, generate testbench in PD was needed
2022-12-19 22:48:11 +03:00
parameterizationKey="sem:1.1:m=32"
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
instancePathKey="niosII:.:sem"
pt3.12 modelled
2022-10-24 22:35:24 +03:00
kind="sem"
sem ram widening correct, generate testbench in PD was needed
2022-12-19 22:48:11 +03:00
version="1.1"
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
name="dec">
sem ram widening correct, generate testbench in PD was needed
2022-12-19 22:48:11 +03:00
<parameter name="m" value="32" />
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/dec.sv"
type="SYSTEM_VERILOG"
attributes="TOP_LEVEL_FILE" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/periodram.v"
type="VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file path="C:/Software/FPGA/iu3-31m/Lab2/Top/Semafor_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="niosII" as="sem" />
<messages>
pt3.12 modelled
2022-10-24 22:35:24 +03:00
<message level="Debug" culprit="niosII">queue size: 5 starting:sem "submodules/dec"</message>
<message level="Info" culprit="sem"><![CDATA["<b>niosII</b>" instantiated <b>sem</b> "<b>sem</b>"]]></message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_avalon_timer:18.1:alwaysRun=false,counterSize=32,fixedPeriod=false,loadValue=49999,mult=0.001,period=1,periodUnits=MSEC,periodUnitsString=ms,resetOutput=false,slave_address_width=3,snapshot=true,systemFrequency=50000000,ticksPerSec=1000.0,timeoutPulseOutput=false,timerPreset=FULL_FEATURED,valueInSecond=0.001,watchdogPulse=2"
instancePathKey="niosII:.:sys_clk_timer"
kind="altera_avalon_timer"
version="18.1"
name="niosII_sys_clk_timer">
<parameter name="loadValue" value="49999" />
<parameter name="timeoutPulseOutput" value="false" />
<parameter name="period" value="1" />
<parameter name="periodUnitsString" value="ms" />
<parameter name="mult" value="0.001" />
<parameter name="ticksPerSec" value="1000.0" />
<parameter name="systemFrequency" value="50000000" />
<parameter name="alwaysRun" value="false" />
<parameter name="valueInSecond" value="0.001" />
<parameter name="fixedPeriod" value="false" />
<parameter name="counterSize" value="32" />
<parameter name="periodUnits" value="MSEC" />
<parameter name="watchdogPulse" value="2" />
<parameter name="slave_address_width" value="3" />
<parameter name="resetOutput" value="false" />
<parameter name="snapshot" value="true" />
<parameter name="timerPreset" value="FULL_FEATURED" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_sys_clk_timer.v"
type="VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="niosII" as="sys_clk_timer" />
<messages>
<message level="Debug" culprit="niosII">queue size: 4 starting:altera_avalon_timer "submodules/niosII_sys_clk_timer"</message>
<message level="Info" culprit="sys_clk_timer">Starting RTL generation for module 'niosII_sys_clk_timer'</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Info" culprit="sys_clk_timer"> Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=niosII_sys_clk_timer --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen/ --quartus_dir=C:/software/intelfpga_lite/18.1/quartus --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0034_sys_clk_timer_gen//niosII_sys_clk_timer_component_configuration.pl --do_build_sim=0 ]</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Info" culprit="sys_clk_timer">Done RTL generation for module 'niosII_sys_clk_timer'</message>
<message level="Info" culprit="sys_clk_timer"><![CDATA["<b>niosII</b>" instantiated <b>altera_avalon_timer</b> "<b>sys_clk_timer</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
ram32ok
2022-12-22 22:27:05 +03:00
parameterizationKey="altera_mm_interconnect:18.1:AUTO_DEVICE=EP4CE115F29C7,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=,COMPOSE_CONTENTS=add_instance {cpu_data_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESS_W} {18};set_instance_parameter_value {cpu_data_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_data_master_translator} {UAV_ADDRESS_W} {18};set_instance_parameter_value {cpu_data_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_data_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_READ} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITE} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_DEBUGACCESS} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_data_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTBOUNDARIES} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_data_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_data_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_REGISTERINCOMINGSIGNALS} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_data_master_translator} {SYNC_RESET} {0};add_instance {cpu_instruction_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESS_W} {18};set_instance_parameter_value {cpu_instruction_master
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
&lt;address_map&gt;
&lt;slave
id=&quot;1&quot;
name=&quot;jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0&quot;
ram32ok
2022-12-22 22:27:05 +03:00
start=&quot;0x0000000000021068&quot;
end=&quot;0x00000000000021070&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;4&quot;
name=&quot;sem_ctl_slave_translator.avalon_universal_slave_0&quot;
ram32ok
2022-12-22 22:27:05 +03:00
start=&quot;0x0000000000021060&quot;
end=&quot;0x00000000000021068&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;0&quot;
name=&quot;cpu_debug_mem_slave_translator.avalon_universal_slave_0&quot;
start=&quot;0x0000000000020800&quot;
end=&quot;0x00000000000021000&quot;
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;5&quot;
name=&quot;sem_ram_slave_translator.avalon_universal_slave_0&quot;
ram32ok
2022-12-22 22:27:05 +03:00
start=&quot;0x0000000000021000&quot;
end=&quot;0x00000000000021040&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;0&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;6&quot;
name=&quot;sys_clk_timer_s1_translator.avalon_universal_slave_0&quot;
ram32ok
2022-12-22 22:27:05 +03:00
start=&quot;0x0000000000021040&quot;
end=&quot;0x00000000000021060&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;3&quot;
name=&quot;mem_s2_translator.avalon_universal_slave_0&quot;
start=&quot;0x0000000000000000&quot;
end=&quot;0x00000000000020000&quot;
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {cpu_data_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_data_master_agent} {ID} {0};set_instance_parameter_value {cpu_data_master_agent} {BURSTWRAP_VALUE} {7};set_instance_parameter_value {cpu_data_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_data_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_data_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_agent} {USE_WRITERESPONSE} {0};add_instance {cpu_instruction_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_H} {74};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_L} {74};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_H} {72};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_L} {72};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_H} {71};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_L} {71};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_H} {70};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_L} {69};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_H} {88};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_L} {85};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_H} {81};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_L} {81};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_EXCLUSIVE} {59};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {cpu_instruction_master_agent} {ST_DATA_W} {94};set_instance_parameter_
&lt;address_map&gt;
&lt;slave
id=&quot;0&quot;
name=&quot;cpu_debug_mem_slave_translator.avalon_universal_slave_0&quot;
start=&quot;0x0000000000020800&quot;
end=&quot;0x00000000000021000&quot;
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;2&quot;
name=&quot;mem_s1_translator.avalon_universal_slave_0&quot;
start=&quot;0x0000000000000000&quot;
end=&quot;0x00000000000020000&quot;
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
ram32ok
2022-12-22 22:27:05 +03:00
};set_instance_parameter_value {cpu_instruction_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_instruction_master_agent} {ID} {1};set_instance_parameter_value {cpu_instruction_master_agent} {BURSTWRAP_VALUE} {3};set_instance_parameter_value {cpu_instruction_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_instruction_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {USE_WRITERESPONSE} {0};add_instance {jtag_uart_avalon_jtag_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ST_CHANNEL_W} {7};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
&lt;address_map&gt;
&lt;slave
id=&quot;1&quot;
name=&quot;jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0&quot;
ram32ok
2022-12-22 22:27:05 +03:00
start=&quot;0x0000000000021068&quot;
end=&quot;0x00000000000021070&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;4&quot;
name=&quot;sem_ctl_slave_translator.avalon_universal_slave_0&quot;
ram32ok
2022-12-22 22:27:05 +03:00
start=&quot;0x0000000000021060&quot;
end=&quot;0x00000000000021068&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;0&quot;
name=&quot;cpu_debug_mem_slave_translator.avalon_universal_slave_0&quot;
start=&quot;0x0000000000020800&quot;
end=&quot;0x00000000000021000&quot;
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;5&quot;
name=&quot;sem_ram_slave_translator.avalon_universal_slave_0&quot;
ram32ok
2022-12-22 22:27:05 +03:00
start=&quot;0x0000000000021000&quot;
end=&quot;0x00000000000021040&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;0&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;6&quot;
name=&quot;sys_clk_timer_s1_translator.avalon_universal_slave_0&quot;
ram32ok
2022-12-22 22:27:05 +03:00
start=&quot;0x0000000000021040&quot;
end=&quot;0x00000000000021060&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;3&quot;
name=&quot;mem_s2_translator.avalon_universal_slave_0&quot;
start=&quot;0x0000000000000000&quot;
end=&quot;0x00000000000020000&quot;
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
,AV_BURSTBOUNDARIES=1,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=7,CACHE_VALUE=0,ID=0,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),PKT_ADDR_H=53,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=71,PKT_ADDR_SIDEBAND_L=71,PKT_BEGIN_BURST=73,PKT_BURSTWRAP_H=65,PKT_BURSTWRAP_L=63,PKT_BURST_SIZE_H=68,PKT_BURST_SIZE_L=66,PKT_BURST_TYPE_H=70,PKT_BURST_TYPE_L=69,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=62,PKT_BYTE_CNT_L=60,PKT_CACHE_H=88,PKT_CACHE_L=85,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=72,PKT_DATA_SIDEBAND_L=72,PKT_DEST_ID_H=80,PKT_DEST_ID_L=78,PKT_ORI_BURST_SIZE_H=93,PKT_ORI_BURST_SIZE_L=91,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_QOS_H=74,PKT_QOS_L=74,PKT_RESPONSE_STATUS_H=90,PKT_RESPONSE_STATUS_L=89,PKT_SRC_ID_H=77,PKT_SRC_ID_L=75,PKT_THREAD_ID_H=81,PKT_THREAD_ID_L=81,PKT_TRANS_COMPRESSED_READ=54,PKT_TRANS_EXCLUSIVE=59,PKT_TRANS_LOCK=58,PKT_TRANS_POSTED=55,PKT_TRANS_READ=57,PKT_TRANS_WRITE=56,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=7,ST_DATA_W=94,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_master_agent:18.1:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
&lt;slave
id=&quot;0&quot;
name=&quot;cpu_debug_mem_slave_translator.avalon_universal_slave_0&quot;
start=&quot;0x0000000000020800&quot;
end=&quot;0x00000000000021000&quot;
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;2&quot;
name=&quot;mem_s1_translator.avalon_universal_slave_0&quot;
start=&quot;0x0000000000000000&quot;
end=&quot;0x00000000000020000&quot;
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
ram32ok
2022-12-22 22:27:05 +03:00
,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=1,BURSTWRAP_VALUE=3,CACHE_VALUE=0,ID=1,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),PKT_ADDR_H=53,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=71,PKT_ADDR_SIDEBAND_L=71,PKT_BEGIN_BURST=73,PKT_BURSTWRAP_H=65,PKT_BURSTWRAP_L=63,PKT_BURST_SIZE_H=68,PKT_BURST_SIZE_L=66,PKT_BURST_TYPE_H=70,PKT_BURST_TYPE_L=69,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=62,PKT_BYTE_CNT_L=60,PKT_CACHE_H=88,PKT_CACHE_L=85,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=72,PKT_DATA_SIDEBAND_L=72,PKT_DEST_ID_H=80,PKT_DEST_ID_L=78,PKT_ORI_BURST_SIZE_H=93,PKT_ORI_BURST_SIZE_L=91,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_QOS_H=74,PKT_QOS_L=74,PKT_RESPONSE_STATUS_H=90,PKT_RESPONSE_STATUS_L=89,PKT_SRC_ID_H=77,PKT_SRC_ID_L=75,PKT_THREAD_ID_H=81,PKT_THREAD_ID_L=81,PKT_TRANS_COMPRESSED_READ=54,PKT_TRANS_EXCLUSIVE=59,PKT_TRANS_LOCK=58,PKT_TRANS_POSTED=55,PKT_TRANS_READ=57,PKT_TRANS_WRITE=56,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=7,ST_DATA_W=94,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_slave_agent:18.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=1,MAX_BURSTWRAP=7,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),PKT_ADDR_H=53,PKT_ADDR_L=36,PKT_BEGIN_BURST=73,PKT_BURSTWRAP_H=65,PKT_BURSTWRAP_L=63,PKT_BURST_SIZE_H=68,PKT_BURST_SIZE_L=66,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=62,PKT_BYTE_CNT_L=60,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=80,PKT_DEST_ID_L=78,PKT_ORI_BURST_SIZE_H=93,PKT_ORI_BURST_SIZE_L=91,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_RESPONSE_STATUS_H=90,PKT_RESPONSE_STATUS_L=89,PKT_SRC_ID_H=77,PKT_SRC_ID_L=75,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=54,PKT_TRANS_LOCK=58,PKT_TRANS_POSTED=55,PKT_TRANS_READ=57,PKT_TRANS_WRITE=56,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=7,ST_DATA_W=94,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:18.1:BITS_PER_SYMBOL=95,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:18.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=4,MAX_BURSTWRAP=7,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),PKT_ADDR_H=53,PKT_ADDR_L=36,PKT_BEGIN_BURST=73,PKT_BURSTWRAP_H=65,PKT_BURSTWRAP_L=63,PKT_BURST_SIZE_H=68,PKT_BURST_SIZE_L=66,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=62,PKT_BYTE_CNT_L=60,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=80,PKT_DEST_ID_L=78,PKT_ORI_BURST_SIZE_H=93,PKT_ORI_BURST_SIZE_L=91,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_RESPONSE_STATUS_H=90,PKT_RESPONSE_STATUS_L=89,PKT_SRC_ID_H=77,PKT_SRC_ID_L=75,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=54,PKT_TRANS_LOCK=58,PKT_TRANS_POSTED=55,PKT_TRANS_READ=57,PKT_TRANS_WRITE=56,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=7,ST_DATA_W=94,SUPPRESS_0_BYTEEN_CMD=0,USE_
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
instancePathKey="niosII:.:mm_interconnect_0"
kind="altera_mm_interconnect"
version="18.1"
name="niosII_mm_interconnect_0">
<parameter name="AUTO_DEVICE" value="EP4CE115F29C7" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
<parameter
name="COMPOSE_CONTENTS"
ram32ok
2022-12-22 22:27:05 +03:00
value="add_instance {cpu_data_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESS_W} {18};set_instance_parameter_value {cpu_data_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_data_master_translator} {UAV_ADDRESS_W} {18};set_instance_parameter_value {cpu_data_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_data_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_READ} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITE} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_DEBUGACCESS} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_data_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTBOUNDARIES} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_data_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_data_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_REGISTERINCOMINGSIGNALS} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_data_master_translator} {SYNC_RESET} {0};add_instance {cpu_instruction_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESS_W} {18};set_instance_parameter_value {cpu_instruction_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
&lt;address_map&gt;
&lt;slave
id=&quot;1&quot;
name=&quot;jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0&quot;
ram32ok
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start=&quot;0x0000000000021068&quot;
end=&quot;0x00000000000021070&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;4&quot;
name=&quot;sem_ctl_slave_translator.avalon_universal_slave_0&quot;
ram32ok
2022-12-22 22:27:05 +03:00
start=&quot;0x0000000000021060&quot;
end=&quot;0x00000000000021068&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;0&quot;
name=&quot;cpu_debug_mem_slave_translator.avalon_universal_slave_0&quot;
start=&quot;0x0000000000020800&quot;
end=&quot;0x00000000000021000&quot;
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;5&quot;
name=&quot;sem_ram_slave_translator.avalon_universal_slave_0&quot;
ram32ok
2022-12-22 22:27:05 +03:00
start=&quot;0x0000000000021000&quot;
end=&quot;0x00000000000021040&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;0&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;6&quot;
name=&quot;sys_clk_timer_s1_translator.avalon_universal_slave_0&quot;
ram32ok
2022-12-22 22:27:05 +03:00
start=&quot;0x0000000000021040&quot;
end=&quot;0x00000000000021060&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;3&quot;
name=&quot;mem_s2_translator.avalon_universal_slave_0&quot;
start=&quot;0x0000000000000000&quot;
end=&quot;0x00000000000020000&quot;
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {cpu_data_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_data_master_agent} {ID} {0};set_instance_parameter_value {cpu_data_master_agent} {BURSTWRAP_VALUE} {7};set_instance_parameter_value {cpu_data_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_data_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_data_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_agent} {USE_WRITERESPONSE} {0};add_instance {cpu_instruction_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_H} {74};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_L} {74};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_H} {72};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_L} {72};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_H} {71};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_L} {71};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_H} {70};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_L} {69};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_H} {88};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_L} {85};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_H} {81};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_L} {81};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_EXCLUSIVE} {59};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {cpu_instruction_master_agent} {ST_DATA_W} {94};set_instance_parameter_
&lt;address_map&gt;
&lt;slave
id=&quot;0&quot;
name=&quot;cpu_debug_mem_slave_translator.avalon_universal_slave_0&quot;
start=&quot;0x0000000000020800&quot;
end=&quot;0x00000000000021000&quot;
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;2&quot;
name=&quot;mem_s1_translator.avalon_universal_slave_0&quot;
start=&quot;0x0000000000000000&quot;
end=&quot;0x00000000000020000&quot;
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
ram32ok
2022-12-22 22:27:05 +03:00
};set_instance_parameter_value {cpu_instruction_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_instruction_master_agent} {ID} {1};set_instance_parameter_value {cpu_instruction_master_agent} {BURSTWRAP_VALUE} {3};set_instance_parameter_value {cpu_instruction_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_instruction_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {USE_WRITERESPONSE} {0};add_instance {jtag_uart_avalon_jtag_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURST_SIZE_H} {68};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURST_SIZE_L} {66};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_LOCK} {58};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BEGIN_BURST} {73};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURSTWRAP_H} {65};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURSTWRAP_L} {63};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTE_CNT_H} {62};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTE_CNT_L} {60};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ADDR_H} {53};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_COMPRESSED_READ} {54};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_POSTED} {55};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_WRITE} {56};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_READ} {57};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SRC_ID_H} {77};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SRC_ID_L} {75};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DEST_ID_H} {80};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DEST_ID_L} {78};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ST_CHANNEL_W} {7};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ST_DATA_W} {94};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0.v"
type="VERILOG" />
</generatedFiles>
<childGeneratedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_master_translator.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_slave_translator.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_master_agent.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_slave_agent.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_avalon_sc_fifo.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_001.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_002.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_004.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_008.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_demux.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v"
type="VERILOG" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
type="SYSTEM_VERILOG"
attributes="" />
</childGeneratedFiles>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
</sourceFiles>
<childSourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
</childSourceFiles>
<instantiator instantiator="niosII" as="mm_interconnect_0" />
<messages>
<message level="Debug" culprit="niosII">queue size: 3 starting:altera_mm_interconnect "submodules/niosII_mm_interconnect_0"</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug">Transform: CustomInstructionTransform</message>
<message level="Debug">No custom instruction connections, skipping transform </message>
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: MMTransform</message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InitialInterconnectTransform</message>
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
<message level="Debug">Transform: DefaultSlaveTransform</message>
<message level="Debug">Transform: TranslatorTransform</message>
<message level="Debug">No Avalon connections, skipping transform </message>
<message level="Debug">Transform: IDPadTransform</message>
<message level="Debug">Transform: DomainTransform</message>
<message level="Debug">Transform: RouterTransform</message>
<message level="Debug">Transform: TrafficLimiterTransform</message>
<message level="Debug">Transform: BurstTransform</message>
<message level="Debug">Transform: TreeTransform</message>
<message level="Debug">Transform: NetworkToSwitchTransform</message>
<message level="Debug">Transform: WidthTransform</message>
<message level="Debug">Transform: RouterTableTransform</message>
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
<message level="Debug">Transform: ClockCrossingTransform</message>
<message level="Debug">Transform: PipelineTransform</message>
<message level="Debug">Transform: SpotPipelineTransform</message>
<message level="Debug">Transform: PerformanceMonitorTransform</message>
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
<message level="Debug">Transform: HierarchyTransform</message>
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>54</b> modules, <b>178</b> connections]]></message>
<message level="Debug">Transform: InterruptMapperTransform</message>
<message level="Debug">Transform: InterruptSyncTransform</message>
<message level="Debug">Transform: InterruptFanoutTransform</message>
<message level="Debug">Transform: AvalonStreamingTransform</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Info" culprit="avalon_st_adapter">Inserting error_adapter: error_adapter_0</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Debug" culprit="avalon_st_adapter.clk_bridge_0">Timing: ELA:1/0.001s</message>
<message level="Debug" culprit="avalon_st_adapter.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
<message level="Debug" culprit="avalon_st_adapter.error_adapter_0">Timing: ELA:1/0.027s</message>
<message level="Debug" culprit="avalon_st_adapter">Timing: COM:3/0.052s/0.076s</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Info" culprit="avalon_st_adapter_001">Inserting error_adapter: error_adapter_0</message>
ram32ok
2022-12-22 22:27:05 +03:00
<message level="Debug" culprit="avalon_st_adapter_001.clk_bridge_0">Timing: ELA:1/0.001s</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Debug" culprit="avalon_st_adapter_001.rst_bridge_0">Timing: ELA:2/0.001s/0.002s</message>
<message level="Debug" culprit="avalon_st_adapter_001.error_adapter_0">Timing: ELA:1/0.011s</message>
<message level="Debug" culprit="avalon_st_adapter_001">Timing: COM:3/0.021s/0.022s</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Info" culprit="avalon_st_adapter_002">Inserting error_adapter: error_adapter_0</message>
<message level="Debug" culprit="avalon_st_adapter_002.clk_bridge_0">Timing: ELA:1/0.000s</message>
ram32ok
2022-12-22 22:27:05 +03:00
<message level="Debug" culprit="avalon_st_adapter_002.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Debug" culprit="avalon_st_adapter_002.error_adapter_0">Timing: ELA:1/0.009s</message>
<message level="Debug" culprit="avalon_st_adapter_002">Timing: COM:3/0.019s/0.025s</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Info" culprit="avalon_st_adapter_003">Inserting error_adapter: error_adapter_0</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Debug" culprit="avalon_st_adapter_003.clk_bridge_0">Timing: ELA:1/0.000s</message>
<message level="Debug" culprit="avalon_st_adapter_003.rst_bridge_0">Timing: ELA:2/0.001s/0.002s</message>
<message level="Debug" culprit="avalon_st_adapter_003.error_adapter_0">Timing: ELA:1/0.011s</message>
<message level="Debug" culprit="avalon_st_adapter_003">Timing: COM:3/0.021s/0.024s</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Info" culprit="avalon_st_adapter_004">Inserting error_adapter: error_adapter_0</message>
ram32ok
2022-12-22 22:27:05 +03:00
<message level="Debug" culprit="avalon_st_adapter_004.clk_bridge_0">Timing: ELA:1/0.001s</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Debug" culprit="avalon_st_adapter_004.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
<message level="Debug" culprit="avalon_st_adapter_004.error_adapter_0">Timing: ELA:1/0.010s</message>
<message level="Debug" culprit="avalon_st_adapter_004">Timing: COM:3/0.024s/0.032s</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Info" culprit="avalon_st_adapter_005">Inserting error_adapter: error_adapter_0</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Debug" culprit="avalon_st_adapter_005.clk_bridge_0">Timing: ELA:1/0.000s</message>
<message level="Debug" culprit="avalon_st_adapter_005.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
<message level="Debug" culprit="avalon_st_adapter_005.error_adapter_0">Timing: ELA:1/0.008s</message>
<message level="Debug" culprit="avalon_st_adapter_005">Timing: COM:3/0.019s/0.022s</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Info" culprit="avalon_st_adapter_006">Inserting error_adapter: error_adapter_0</message>
<message level="Debug" culprit="avalon_st_adapter_006.clk_bridge_0">Timing: ELA:1/0.000s</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Debug" culprit="avalon_st_adapter_006.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
<message level="Debug" culprit="avalon_st_adapter_006.error_adapter_0">Timing: ELA:1/0.011s</message>
<message level="Debug" culprit="avalon_st_adapter_006">Timing: COM:3/0.022s/0.028s</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message
level="Debug"
culprit="com_altera_sopcmodel_transforms_avalonst_AvalonStreamingTransform"><![CDATA[After transform: <b>61</b> modules, <b>199</b> connections]]></message>
<message level="Debug">Transform: ResetAdaptation</message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_001</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_002</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_002</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_004</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_002</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_002</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_002</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/niosII_mm_interconnect_0_router_008</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_demux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_demux_001</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_mux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_mux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_mux_002</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_mux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_mux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_mux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_mux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_demux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_demux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_cmd_demux_001</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_demux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_demux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_demux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_demux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_mux</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/niosII_mm_interconnect_0_rsp_mux_001</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
<message level="Info" culprit="mm_interconnect_0"><![CDATA["<b>niosII</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 58 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
<message level="Info" culprit="cpu_data_master_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>cpu_data_master_translator</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 56 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
<message level="Info" culprit="jtag_uart_avalon_jtag_slave_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>jtag_uart_avalon_jtag_slave_translator</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 49 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
<message level="Info" culprit="cpu_data_master_agent"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_agent</b> "<b>cpu_data_master_agent</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 47 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
<message level="Info" culprit="jtag_uart_avalon_jtag_slave_agent"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>jtag_uart_avalon_jtag_slave_agent</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 46 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
<message level="Info" culprit="jtag_uart_avalon_jtag_slave_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>jtag_uart_avalon_jtag_slave_agent_rsp_fifo</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 33 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router"</message>
<message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 32 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001"</message>
<message level="Info" culprit="router_001"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 31 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"</message>
<message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 29 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_004"</message>
<message level="Info" culprit="router_004"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_004</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 25 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_008"</message>
<message level="Info" culprit="router_008"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_008</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 24 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux"</message>
<message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 23 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001"</message>
<message level="Info" culprit="cmd_demux_001"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_001</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 22 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"</message>
<message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 20 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_002"</message>
<message level="Info" culprit="cmd_mux_002"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_002</b>"]]></message>
<message level="Info"><![CDATA[Reusing file <b>C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
<message level="Debug" culprit="niosII">queue size: 15 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"</message>
<message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 8 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux"</message>
<message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
<message level="Info"><![CDATA[Reusing file <b>C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
<message level="Debug" culprit="niosII">queue size: 7 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux_001"</message>
<message level="Info" culprit="rsp_mux_001"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_001</b>"]]></message>
<message level="Info"><![CDATA[Reusing file <b>C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
<message level="Debug" culprit="niosII">queue size: 6 starting:altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug">Transform: CustomInstructionTransform</message>
<message level="Debug">No custom instruction connections, skipping transform </message>
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
<message level="Debug">Transform: MMTransform</message>
<message level="Debug">Transform: InterruptMapperTransform</message>
<message level="Debug">Transform: InterruptSyncTransform</message>
<message level="Debug">Transform: InterruptFanoutTransform</message>
<message level="Debug">Transform: AvalonStreamingTransform</message>
<message level="Debug">Transform: ResetAdaptation</message>
<message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0</b>"]]></message>
<message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 0 starting:error_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0"</message>
<message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_irq_mapper:18.1:AUTO_DEVICE_FAMILY=Cyclone IV E,IRQ_MAP=0:0,1:1,NUM_RCVRS=2,SENDER_IRQ_WIDTH=32"
instancePathKey="niosII:.:irq_mapper"
kind="altera_irq_mapper"
version="18.1"
name="niosII_irq_mapper">
<parameter name="NUM_RCVRS" value="2" />
<parameter name="IRQ_MAP" value="0:0,1:1" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="SENDER_IRQ_WIDTH" value="32" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_irq_mapper.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_irq_mapper/altera_irq_mapper_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="niosII" as="irq_mapper" />
<messages>
<message level="Debug" culprit="niosII">queue size: 61 starting:altera_irq_mapper "submodules/niosII_irq_mapper"</message>
<message level="Info" culprit="irq_mapper"><![CDATA["<b>niosII</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_reset_controller:18.1:ADAPT_RESET_REQUEST=0,MIN_RST_ASSERTION_TIME=3,NUM_RESET_INPUTS=2,OUTPUT_RESET_SYNC_EDGES=deassert,RESET_REQUEST_PRESENT=1,RESET_REQ_EARLY_DSRT_TIME=1,RESET_REQ_WAIT_TIME=1,SYNC_DEPTH=2,USE_RESET_REQUEST_IN0=0,USE_RESET_REQUEST_IN1=0,USE_RESET_REQUEST_IN10=0,USE_RESET_REQUEST_IN11=0,USE_RESET_REQUEST_IN12=0,USE_RESET_REQUEST_IN13=0,USE_RESET_REQUEST_IN14=0,USE_RESET_REQUEST_IN15=0,USE_RESET_REQUEST_IN2=0,USE_RESET_REQUEST_IN3=0,USE_RESET_REQUEST_IN4=0,USE_RESET_REQUEST_IN5=0,USE_RESET_REQUEST_IN6=0,USE_RESET_REQUEST_IN7=0,USE_RESET_REQUEST_IN8=0,USE_RESET_REQUEST_IN9=0,USE_RESET_REQUEST_INPUT=0"
instancePathKey="niosII:.:rst_controller"
kind="altera_reset_controller"
version="18.1"
name="altera_reset_controller">
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_reset_controller.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_reset_synchronizer.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_reset_controller.sdc"
type="SDC"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="niosII" as="rst_controller" />
<messages>
<message level="Debug" culprit="niosII">queue size: 60 starting:altera_reset_controller "submodules/altera_reset_controller"</message>
<message level="Info" culprit="rst_controller"><![CDATA["<b>niosII</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
ram32ok
2022-12-22 22:27:05 +03:00
parameterizationKey="altera_nios2_gen2_unit:18.1:bht_ramBlockType=Automatic,breakAbsoluteAddr=133152,breakOffset=32,breakSlave=None,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,cpu_name=cpu,customInstSlavesSystemInfo=&lt;info/&gt;,dataAddrWidth=18,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=&lt;address-map&gt;&lt;slave name=&apos;mem.s2&apos; start=&apos;0x0&apos; end=&apos;0x20000&apos; type=&apos;altera_avalon_onchip_memory2.s2&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x20800&apos; end=&apos;0x21000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;sem.ram_slave&apos; start=&apos;0x21000&apos; end=&apos;0x21040&apos; type=&apos;sem.ram_slave&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x21040&apos; end=&apos;0x21060&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;sem.ctl_slave&apos; start=&apos;0x21060&apos; end=&apos;0x21068&apos; type=&apos;sem.ctl_slave&apos; /&gt;&lt;slave name=&apos;jtag_uart.avalon_jtag_slave&apos; start=&apos;0x21068&apos; end=&apos;0x21070&apos; type=&apos;altera_avalon_jtag_uart.avalon_jtag_slave&apos; /&gt;&lt;/address-map&gt;,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_top=0,data_master_paddr_base=0,data_master_paddr_top=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=0,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=Cyclone IV E,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_S
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
instancePathKey="niosII:.:cpu:.:cpu"
kind="altera_nios2_gen2_unit"
version="18.1"
name="niosII_cpu_cpu">
<parameter name="icache_burstType" value="None" />
<parameter name="setting_oci_version" value="1" />
<parameter name="mpx_enabled" value="false" />
<parameter name="ocimem_ramBlockType" value="Automatic" />
<parameter name="dcache_victim_buf_impl" value="ram" />
<parameter name="setting_exportPCB" value="false" />
<parameter name="setting_ic_ecc_present" value="true" />
<parameter name="dcache_size_derived" value="2048" />
<parameter name="mmu_udtlbNumEntries" value="6" />
<parameter name="tightly_coupled_instruction_master_3_paddr_top" value="0" />
<parameter
name="deviceFeaturesSystemInfo"
value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPO
<parameter name="bht_ramBlockType" value="Automatic" />
<parameter name="instruction_master_high_performance_paddr_base" value="0" />
<parameter name="mmu_TLBMissExcSlave" value="None" />
<parameter name="impl" value="Tiny" />
<parameter name="regfile_ramBlockType" value="Automatic" />
<parameter name="dcache_size" value="2048" />
<parameter name="tightly_coupled_data_master_0_paddr_top" value="0" />
<parameter name="breakOffset" value="32" />
<parameter name="breakSlave" value="None" />
<parameter name="setting_branchPredictionType" value="Dynamic" />
<parameter name="exceptionOffset" value="32" />
<parameter name="flash_instruction_master_paddr_top" value="0" />
<parameter name="tightlyCoupledDataMaster0MapParam" value="" />
<parameter name="cpu_name" value="cpu" />
<parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
<parameter name="breakAbsoluteAddr" value="133152" />
<parameter name="setting_activateTrace" value="false" />
<parameter name="debug_offchiptrace" value="false" />
<parameter name="setting_avalonDebugPortPresent" value="false" />
<parameter name="dcache_numTCDM" value="0" />
<parameter name="setting_ecc_sim_test_ports" value="false" />
<parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
<parameter name="setting_showUnpublishedSettings" value="false" />
<parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
<parameter name="debug_debugReqSignals" value="false" />
<parameter name="master_addr_map" value="false" />
<parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
<parameter name="mmu_processIDNumBits" value="8" />
<parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
<parameter name="debug_onchiptrace" value="false" />
<parameter name="setting_rf_ecc_present" value="true" />
<parameter name="resetAbsoluteAddr" value="0" />
<parameter name="tightly_coupled_data_master_1_paddr_top" value="0" />
<parameter name="ocimem_ramInit" value="false" />
<parameter name="internalIrqMaskSystemInfo" value="3" />
<parameter name="instruction_master_paddr_top" value="0" />
<parameter name="cpuArchRev" value="1" />
<parameter name="setting_dtcm_ecc_present" value="true" />
<parameter name="exceptionAbsoluteAddr" value="32" />
<parameter name="setting_interruptControllerType" value="Internal" />
<parameter name="dcache_tagramBlockType" value="Automatic" />
<parameter name="debug_insttrace" value="false" />
<parameter name="icache_size" value="4096" />
<parameter name="setting_itcm_ecc_present" value="true" />
<parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
<parameter
name="dataSlaveMapParam"
ram32ok
2022-12-22 22:27:05 +03:00
value="&lt;address-map&gt;&lt;slave name=&apos;mem.s2&apos; start=&apos;0x0&apos; end=&apos;0x20000&apos; type=&apos;altera_avalon_onchip_memory2.s2&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x20800&apos; end=&apos;0x21000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;slave name=&apos;sem.ram_slave&apos; start=&apos;0x21000&apos; end=&apos;0x21040&apos; type=&apos;sem.ram_slave&apos; /&gt;&lt;slave name=&apos;sys_clk_timer.s1&apos; start=&apos;0x21040&apos; end=&apos;0x21060&apos; type=&apos;altera_avalon_timer.s1&apos; /&gt;&lt;slave name=&apos;sem.ctl_slave&apos; start=&apos;0x21060&apos; end=&apos;0x21068&apos; type=&apos;sem.ctl_slave&apos; /&gt;&lt;slave name=&apos;jtag_uart.avalon_jtag_slave&apos; start=&apos;0x21068&apos; end=&apos;0x21070&apos; type=&apos;altera_avalon_jtag_uart.avalon_jtag_slave&apos; /&gt;&lt;/address-map&gt;" />
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<parameter name="mpu_enabled" value="false" />
<parameter name="setting_ecc_present" value="false" />
<parameter name="mmu_TLBMissExcAbsAddr" value="0" />
<parameter name="mpu_useLimit" value="false" />
<parameter name="stratix_dspblock_shift_mul" value="false" />
<parameter name="icache_numTCIM" value="0" />
<parameter name="setting_usedesignware" value="false" />
<parameter name="tightlyCoupledDataMaster3MapParam" value="" />
<parameter name="instruction_master_high_performance_paddr_top" value="0" />
<parameter name="setting_ioregionBypassDCache" value="false" />
<parameter name="mmu_TLBMissExcOffset" value="0" />
<parameter name="mmu_enabled" value="false" />
<parameter name="mmu_uitlbNumEntries" value="4" />
<parameter name="register_file_por" value="false" />
<parameter name="faAddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
<parameter name="tightly_coupled_data_master_3_paddr_top" value="0" />
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
<parameter name="setting_activateTestEndChecker" value="false" />
<parameter name="cpuID" value="0" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="setting_asic_enabled" value="false" />
<parameter name="exceptionSlave" value="mem.s1" />
<parameter name="setting_HDLSimCachesCleared" value="true" />
<parameter name="debug_triggerArming" value="true" />
<parameter name="debug_OCIOnchipTrace" value="_128" />
<parameter name="dataAddrWidth" value="18" />
<parameter name="setting_bit31BypassDCache" value="false" />
<parameter name="instAddrWidth" value="18" />
<parameter name="setting_asic_add_scan_mode_input" value="false" />
<parameter name="tightly_coupled_instruction_master_1_paddr_top" value="0" />
<parameter name="io_regionbase" value="0" />
<parameter name="setting_shadowRegisterSets" value="0" />
<parameter name="icache_ramBlockType" value="Automatic" />
<parameter name="data_master_paddr_top" value="0" />
<parameter name="translate_on" value=" &quot;synthesis translate_on&quot; " />
<parameter name="faSlaveMapParam" value="" />
<parameter name="setting_clearXBitsLDNonBypass" value="true" />
<parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
<parameter name="mmu_autoAssignTlbPtrSz" value="true" />
<parameter name="fa_cache_line" value="2" />
<parameter name="debug_assignJtagInstanceID" value="false" />
<parameter name="instruction_master_paddr_base" value="0" />
<parameter name="userDefinedSettings" value="" />
<parameter name="clockFrequency" value="50000000" />
<parameter name="setting_activateMonitors" value="true" />
<parameter name="resetOffset" value="0" />
<parameter name="dcache_ramBlockType" value="Automatic" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster2MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightly_coupled_instruction_master_0_paddr_top" value="0" />
<parameter name="setting_allow_break_inst" value="false" />
<parameter name="setting_asic_third_party_synthesis" value="false" />
<parameter name="io_regionsize" value="0" />
<parameter name="mpu_minInstRegionSize" value="12" />
<parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
<parameter name="translate_off" value=" &quot;synthesis translate_off&quot; " />
<parameter name="mpu_numOfInstRegion" value="8" />
<parameter name="flash_instruction_master_paddr_base" value="0" />
<parameter name="setting_exportdebuginfo" value="false" />
<parameter name="mmu_tlbPtrSz" value="7" />
<parameter name="cpuReset" value="false" />
<parameter name="resetSlave" value="mem.s1" />
<parameter name="dcache_bursts_derived" value="false" />
<parameter name="multiplierType" value="no_mul" />
<parameter name="setting_removeRAMinit" value="false" />
<parameter name="icache_tagramBlockType" value="Automatic" />
<parameter name="debug_traceStorage" value="onchip_trace" />
<parameter name="setting_preciseIllegalMemAccessException" value="false" />
<parameter name="fa_cache_linesize" value="0" />
<parameter name="setting_mmu_ecc_present" value="true" />
<parameter name="debug_datatrace" value="false" />
<parameter name="setting_HBreakTest" value="false" />
<parameter name="debug_hwbreakpoint" value="0" />
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
<parameter name="tightly_coupled_data_master_2_paddr_top" value="0" />
<parameter name="setting_disableocitrace" value="false" />
<parameter name="setting_bigEndian" value="false" />
<parameter name="mpu_minDataRegionSize" value="12" />
<parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
<parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
<parameter name="debug_jtagInstanceID" value="0" />
<parameter name="setting_showInternalSettings" value="false" />
<parameter name="setting_breakslaveoveride" value="false" />
<parameter name="debug_traceType" value="none" />
<parameter name="instructionMasterHighPerformanceMapParam" value="" />
<parameter name="tightly_coupled_instruction_master_2_paddr_top" value="0" />
<parameter name="setting_alwaysEncrypt" value="true" />
<parameter name="setting_oci_export_jtag_signals" value="false" />
<parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_top" value="0" />
<parameter name="dcache_lineSize_derived" value="32" />
<parameter name="deviceFamilyName" value="Cyclone IV E" />
<parameter name="debug_datatrigger" value="0" />
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
<parameter name="debug_enabled" value="true" />
<parameter name="setting_export_large_RAMs" value="false" />
<parameter name="tightlyCoupledDataMaster1MapParam" value="" />
<parameter name="setting_dc_ecc_present" value="true" />
<parameter name="setting_support31bitdcachebypass" value="true" />
<parameter
name="instSlaveMapParam"
value="&lt;address-map&gt;&lt;slave name=&apos;mem.s1&apos; start=&apos;0x0&apos; end=&apos;0x20000&apos; type=&apos;altera_avalon_onchip_memory2.s1&apos; /&gt;&lt;slave name=&apos;cpu.debug_mem_slave&apos; start=&apos;0x20800&apos; end=&apos;0x21000&apos; type=&apos;altera_nios2_gen2.debug_mem_slave&apos; /&gt;&lt;/address-map&gt;" />
<parameter name="dividerType" value="no_div" />
<parameter name="setting_bhtPtrSz" value="8" />
<parameter name="setting_exportvectors" value="false" />
<parameter name="tmr_enabled" value="false" />
<parameter name="data_master_paddr_base" value="0" />
<parameter name="breakSlave_derived" value="cpu.debug_mem_slave" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="mpu_numOfDataRegion" value="8" />
<parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
<parameter name="mmu_ramBlockType" value="Automatic" />
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="cdx_enabled" value="false" />
<parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
<parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
<parameter name="dcache_bursts" value="false" />
<parameter name="tracefilename" value="" />
<parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
<parameter name="setting_asic_synopsys_translate_on_off" value="false" />
<parameter name="setting_fast_register_read" value="false" />
<parameter name="mmu_tlbNumWays" value="16" />
<parameter name="shifterType" value="medium_le_shift" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu.sdc"
type="SDC"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_sysclk.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_tck.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_wrapper.v"
type="VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_ociram_default_contents.mif"
type="MIF"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_a.mif"
type="MIF"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_b.mif"
type="MIF"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v"
type="VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="niosII_cpu" as="cpu" />
<messages>
<message level="Debug" culprit="niosII">queue size: 59 starting:altera_nios2_gen2_unit "submodules/niosII_cpu_cpu"</message>
<message level="Info" culprit="cpu">Starting RTL generation for module 'niosII_cpu_cpu'</message>
simulated individual, looks ok
2022-12-24 02:08:20 +03:00
<message level="Info" culprit="cpu"> Generation command is [exec C:/Software/intelFPGA_lite/18.1/quartus/bin64//eperlcmd.exe -I C:/Software/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/software/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/software/intelfpga_lite/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=niosII_cpu_cpu --dir=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen/ --quartus_bindir=C:/Software/intelFPGA_lite/18.1/quartus/bin64/ --verilog --config=C:/Users/IVAN-I~1/AppData/Local/Temp/alt9349_7343411587542223325.dir/0037_cpu_gen//niosII_cpu_cpu_processor_configuration.pl --do_build_sim=0 ]</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:53 (*) Starting Nios II generation</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:53 (*) Checking for plaintext license.</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) Couldn't query license setup in Quartus directory C:/Software/intelFPGA_lite/18.1/quartus/bin64/</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) Defaulting to contents of LM_LICENSE_FILE environment variable</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) LM_LICENSE_FILE environment variable is empty</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) Plaintext license not found.</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) No license required to generate encrypted Nios II/e.</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) Elaborating CPU configuration settings</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:54 (*) Creating all objects for CPU</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:55 (*) Generating RTL from CPU objects</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:55 (*) Creating plain-text RTL</message>
<message level="Info" culprit="cpu"># 2022.12.24 01:16:56 (*) Done Nios II generation</message>
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<message level="Info" culprit="cpu">Done RTL generation for module 'niosII_cpu_cpu'</message>
<message level="Info" culprit="cpu"><![CDATA["<b>cpu</b>" instantiated <b>altera_nios2_gen2_unit</b> "<b>cpu</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_merlin_master_translator:18.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=18,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=1,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=1,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=18,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=1,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEDATA=1,USE_WRITERESPONSE=0"
instancePathKey="niosII:.:mm_interconnect_0:.:cpu_data_master_translator"
kind="altera_merlin_master_translator"
version="18.1"
name="altera_merlin_master_translator">
<parameter name="SYNC_RESET" value="0" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_master_translator.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator
instantiator="niosII_mm_interconnect_0"
as="cpu_data_master_translator,cpu_instruction_master_translator" />
<messages>
<message level="Debug" culprit="niosII">queue size: 58 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
<message level="Info" culprit="cpu_data_master_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>cpu_data_master_translator</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_merlin_slave_translator:18.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=1,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=1,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=18,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0"
instancePathKey="niosII:.:mm_interconnect_0:.:jtag_uart_avalon_jtag_slave_translator"
kind="altera_merlin_slave_translator"
version="18.1"
name="altera_merlin_slave_translator">
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_slave_translator.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator
instantiator="niosII_mm_interconnect_0"
as="jtag_uart_avalon_jtag_slave_translator,sem_ctl_slave_translator,cpu_debug_mem_slave_translator,sem_ram_slave_translator,sys_clk_timer_s1_translator,mem_s2_translator,mem_s1_translator" />
<messages>
<message level="Debug" culprit="niosII">queue size: 56 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
<message level="Info" culprit="jtag_uart_avalon_jtag_slave_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>jtag_uart_avalon_jtag_slave_translator</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_merlin_master_agent:18.1:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
&lt;slave
id=&quot;1&quot;
name=&quot;jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0&quot;
ram32ok
2022-12-22 22:27:05 +03:00
start=&quot;0x0000000000021068&quot;
end=&quot;0x00000000000021070&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;4&quot;
name=&quot;sem_ctl_slave_translator.avalon_universal_slave_0&quot;
ram32ok
2022-12-22 22:27:05 +03:00
start=&quot;0x0000000000021060&quot;
end=&quot;0x00000000000021068&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;0&quot;
name=&quot;cpu_debug_mem_slave_translator.avalon_universal_slave_0&quot;
start=&quot;0x0000000000020800&quot;
end=&quot;0x00000000000021000&quot;
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;5&quot;
name=&quot;sem_ram_slave_translator.avalon_universal_slave_0&quot;
ram32ok
2022-12-22 22:27:05 +03:00
start=&quot;0x0000000000021000&quot;
end=&quot;0x00000000000021040&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;0&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;6&quot;
name=&quot;sys_clk_timer_s1_translator.avalon_universal_slave_0&quot;
ram32ok
2022-12-22 22:27:05 +03:00
start=&quot;0x0000000000021040&quot;
end=&quot;0x00000000000021060&quot;
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;slave
id=&quot;3&quot;
name=&quot;mem_s2_translator.avalon_universal_slave_0&quot;
start=&quot;0x0000000000000000&quot;
end=&quot;0x00000000000020000&quot;
responds=&quot;1&quot;
user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
,AV_BURSTBOUNDARIES=1,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=7,CACHE_VALUE=0,ID=0,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),PKT_ADDR_H=53,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=71,PKT_ADDR_SIDEBAND_L=71,PKT_BEGIN_BURST=73,PKT_BURSTWRAP_H=65,PKT_BURSTWRAP_L=63,PKT_BURST_SIZE_H=68,PKT_BURST_SIZE_L=66,PKT_BURST_TYPE_H=70,PKT_BURST_TYPE_L=69,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=62,PKT_BYTE_CNT_L=60,PKT_CACHE_H=88,PKT_CACHE_L=85,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=72,PKT_DATA_SIDEBAND_L=72,PKT_DEST_ID_H=80,PKT_DEST_ID_L=78,PKT_ORI_BURST_SIZE_H=93,PKT_ORI_BURST_SIZE_L=91,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_QOS_H=74,PKT_QOS_L=74,PKT_RESPONSE_STATUS_H=90,PKT_RESPONSE_STATUS_L=89,PKT_SRC_ID_H=77,PKT_SRC_ID_L=75,PKT_THREAD_ID_H=81,PKT_THREAD_ID_L=81,PKT_TRANS_COMPRESSED_READ=54,PKT_TRANS_EXCLUSIVE=59,PKT_TRANS_LOCK=58,PKT_TRANS_POSTED=55,PKT_TRANS_READ=57,PKT_TRANS_WRITE=56,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=7,ST_DATA_W=94,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0"
instancePathKey="niosII:.:mm_interconnect_0:.:cpu_data_master_agent"
kind="altera_merlin_master_agent"
version="18.1"
name="altera_merlin_master_agent">
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_master_agent.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator
instantiator="niosII_mm_interconnect_0"
as="cpu_data_master_agent,cpu_instruction_master_agent" />
<messages>
<message level="Debug" culprit="niosII">queue size: 49 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
<message level="Info" culprit="cpu_data_master_agent"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_agent</b> "<b>cpu_data_master_agent</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_merlin_slave_agent:18.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=1,MAX_BURSTWRAP=7,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),PKT_ADDR_H=53,PKT_ADDR_L=36,PKT_BEGIN_BURST=73,PKT_BURSTWRAP_H=65,PKT_BURSTWRAP_L=63,PKT_BURST_SIZE_H=68,PKT_BURST_SIZE_L=66,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=62,PKT_BYTE_CNT_L=60,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=80,PKT_DEST_ID_L=78,PKT_ORI_BURST_SIZE_H=93,PKT_ORI_BURST_SIZE_L=91,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_RESPONSE_STATUS_H=90,PKT_RESPONSE_STATUS_L=89,PKT_SRC_ID_H=77,PKT_SRC_ID_L=75,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=54,PKT_TRANS_LOCK=58,PKT_TRANS_POSTED=55,PKT_TRANS_READ=57,PKT_TRANS_WRITE=56,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=7,ST_DATA_W=94,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0"
instancePathKey="niosII:.:mm_interconnect_0:.:jtag_uart_avalon_jtag_slave_agent"
kind="altera_merlin_slave_agent"
version="18.1"
name="altera_merlin_slave_agent">
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_slave_agent.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator
instantiator="niosII_mm_interconnect_0"
as="jtag_uart_avalon_jtag_slave_agent,sem_ctl_slave_agent,cpu_debug_mem_slave_agent,sem_ram_slave_agent,sys_clk_timer_s1_agent,mem_s2_agent,mem_s1_agent" />
<messages>
<message level="Debug" culprit="niosII">queue size: 47 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
<message level="Info" culprit="jtag_uart_avalon_jtag_slave_agent"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>jtag_uart_avalon_jtag_slave_agent</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_avalon_sc_fifo:18.1:BITS_PER_SYMBOL=95,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0"
instancePathKey="niosII:.:mm_interconnect_0:.:jtag_uart_avalon_jtag_slave_agent_rsp_fifo"
kind="altera_avalon_sc_fifo"
version="18.1"
name="altera_avalon_sc_fifo">
<parameter name="EXPLICIT_MAXCHANNEL" value="0" />
<parameter name="ENABLE_EXPLICIT_MAXCHANNEL" value="false" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_avalon_sc_fifo.v"
type="VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
</sourceFiles>
<childSourceFiles/>
<instantiator
instantiator="niosII_mm_interconnect_0"
as="jtag_uart_avalon_jtag_slave_agent_rsp_fifo,sem_ctl_slave_agent_rsp_fifo,cpu_debug_mem_slave_agent_rsp_fifo,sem_ram_slave_agent_rsp_fifo,sys_clk_timer_s1_agent_rsp_fifo,mem_s2_agent_rsp_fifo,mem_s1_agent_rsp_fifo" />
<messages>
<message level="Debug" culprit="niosII">queue size: 46 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
<message level="Info" culprit="jtag_uart_avalon_jtag_slave_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>jtag_uart_avalon_jtag_slave_agent_rsp_fifo</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
ram32ok
2022-12-22 22:27:05 +03:00
parameterizationKey="altera_merlin_router:18.1:CHANNEL_ID=100000,000100,001000,010000,000010,000001,DECODER_TYPE=0,DEFAULT_CHANNEL=5,DEFAULT_DESTID=3,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=3,0,5,6,4,1,END_ADDRESS=0x20000,0x21000,0x21040,0x21060,0x21068,0x21070,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,1,1,PKT_ADDR_H=53,PKT_ADDR_L=36,PKT_DEST_ID_H=80,PKT_DEST_ID_L=78,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_TRANS_READ=57,PKT_TRANS_WRITE=56,SECURED_RANGE_LIST=0,0,0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,0,0,SLAVES_INFO=3:100000:0x0:0x20000:both:1:0:0:1,0:000100:0x20800:0x21000:both:1:0:0:1,5:001000:0x21000:0x21040:write:1:0:0:1,6:010000:0x21040:0x21060:both:1:0:0:1,4:000010:0x21060:0x21068:both:1:0:0:1,1:000001:0x21068:0x21070:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x20800,0x21000,0x21040,0x21060,0x21068,ST_CHANNEL_W=7,ST_DATA_W=94,TYPE_OF_TRANSACTION=both,both,write,both,both,both"
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
instancePathKey="niosII:.:mm_interconnect_0:.:router"
kind="altera_merlin_router"
version="18.1"
name="niosII_mm_interconnect_0_router">
<parameter name="ST_CHANNEL_W" value="7" />
<parameter name="DEFAULT_WR_CHANNEL" value="-1" />
<parameter name="PKT_TRANS_READ" value="57" />
<parameter
name="START_ADDRESS"
ram32ok
2022-12-22 22:27:05 +03:00
value="0x0,0x20800,0x21000,0x21040,0x21060,0x21068" />
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<parameter name="DEFAULT_CHANNEL" value="5" />
<parameter name="MEMORY_ALIASING_DECODE" value="0" />
<parameter
name="SLAVES_INFO"
ram32ok
2022-12-22 22:27:05 +03:00
value="3:100000:0x0:0x20000:both:1:0:0:1,0:000100:0x20800:0x21000:both:1:0:0:1,5:001000:0x21000:0x21040:write:1:0:0:1,6:010000:0x21040:0x21060:both:1:0:0:1,4:000010:0x21060:0x21068:both:1:0:0:1,1:000001:0x21068:0x21070:both:1:0:0:1" />
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<parameter name="DEFAULT_RD_CHANNEL" value="-1" />
<parameter name="PKT_ADDR_H" value="53" />
<parameter name="PKT_DEST_ID_H" value="80" />
<parameter name="PKT_ADDR_L" value="36" />
<parameter name="PKT_DEST_ID_L" value="78" />
<parameter
name="MERLIN_PACKET_FORMAT"
value="ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)" />
ram32ok
2022-12-22 22:27:05 +03:00
<parameter name="CHANNEL_ID" value="100000,000100,001000,010000,000010,000001" />
<parameter name="TYPE_OF_TRANSACTION" value="both,both,write,both,both,both" />
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<parameter name="SECURED_RANGE_PAIRS" value="0,0,0,0,0,0" />
<parameter name="SPAN_OFFSET" value="" />
<parameter name="ST_DATA_W" value="94" />
<parameter name="SECURED_RANGE_LIST" value="0,0,0,0,0,0" />
<parameter name="DECODER_TYPE" value="0" />
<parameter name="PKT_PROTECTION_H" value="84" />
<parameter
name="END_ADDRESS"
ram32ok
2022-12-22 22:27:05 +03:00
value="0x20000,0x21000,0x21040,0x21060,0x21068,0x21070" />
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<parameter name="PKT_PROTECTION_L" value="82" />
<parameter name="PKT_TRANS_WRITE" value="56" />
<parameter name="DEFAULT_DESTID" value="3" />
ram32ok
2022-12-22 22:27:05 +03:00
<parameter name="DESTINATION_ID" value="3,0,5,6,4,1" />
pt2 done, qsys added, compiled successfully
2022-10-19 13:25:43 +03:00
<parameter name="NON_SECURED_TAG" value="1,1,1,1,1,1" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="niosII_mm_interconnect_0" as="router" />
<messages>
<message level="Debug" culprit="niosII">queue size: 33 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router"</message>
<message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_merlin_router:18.1:CHANNEL_ID=10,01,DECODER_TYPE=0,DEFAULT_CHANNEL=1,DEFAULT_DESTID=2,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=2,0,END_ADDRESS=0x20000,0x21000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=53,PKT_ADDR_L=36,PKT_DEST_ID_H=80,PKT_DEST_ID_L=78,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_TRANS_READ=57,PKT_TRANS_WRITE=56,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=2:10:0x0:0x20000:both:1:0:0:1,0:01:0x20800:0x21000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x20800,ST_CHANNEL_W=7,ST_DATA_W=94,TYPE_OF_TRANSACTION=both,both"
instancePathKey="niosII:.:mm_interconnect_0:.:router_001"
kind="altera_merlin_router"
version="18.1"
name="niosII_mm_interconnect_0_router_001">
<parameter name="ST_CHANNEL_W" value="7" />
<parameter name="DEFAULT_WR_CHANNEL" value="-1" />
<parameter name="PKT_TRANS_READ" value="57" />
<parameter name="START_ADDRESS" value="0x0,0x20800" />
<parameter name="DEFAULT_CHANNEL" value="1" />
<parameter name="MEMORY_ALIASING_DECODE" value="0" />
<parameter
name="SLAVES_INFO"
value="2:10:0x0:0x20000:both:1:0:0:1,0:01:0x20800:0x21000:both:1:0:0:1" />
<parameter name="DEFAULT_RD_CHANNEL" value="-1" />
<parameter name="PKT_ADDR_H" value="53" />
<parameter name="PKT_DEST_ID_H" value="80" />
<parameter name="PKT_ADDR_L" value="36" />
<parameter name="PKT_DEST_ID_L" value="78" />
<parameter
name="MERLIN_PACKET_FORMAT"
value="ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)" />
<parameter name="CHANNEL_ID" value="10,01" />
<parameter name="TYPE_OF_TRANSACTION" value="both,both" />
<parameter name="SECURED_RANGE_PAIRS" value="0,0" />
<parameter name="SPAN_OFFSET" value="" />
<parameter name="ST_DATA_W" value="94" />
<parameter name="SECURED_RANGE_LIST" value="0,0" />
<parameter name="DECODER_TYPE" value="0" />
<parameter name="PKT_PROTECTION_H" value="84" />
<parameter name="END_ADDRESS" value="0x20000,0x21000" />
<parameter name="PKT_PROTECTION_L" value="82" />
<parameter name="PKT_TRANS_WRITE" value="56" />
<parameter name="DEFAULT_DESTID" value="2" />
<parameter name="DESTINATION_ID" value="2,0" />
<parameter name="NON_SECURED_TAG" value="1,1" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_001.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="niosII_mm_interconnect_0" as="router_001" />
<messages>
<message level="Debug" culprit="niosII">queue size: 32 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_001"</message>
<message level="Info" culprit="router_001"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_merlin_router:18.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=53,PKT_ADDR_L=36,PKT_DEST_ID_H=80,PKT_DEST_ID_L=78,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_TRANS_READ=57,PKT_TRANS_WRITE=56,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=7,ST_DATA_W=94,TYPE_OF_TRANSACTION=both"
instancePathKey="niosII:.:mm_interconnect_0:.:router_002"
kind="altera_merlin_router"
version="18.1"
name="niosII_mm_interconnect_0_router_002">
<parameter name="ST_CHANNEL_W" value="7" />
<parameter name="DEFAULT_WR_CHANNEL" value="-1" />
<parameter name="PKT_TRANS_READ" value="57" />
<parameter name="START_ADDRESS" value="0x0" />
<parameter name="DEFAULT_CHANNEL" value="0" />
<parameter name="MEMORY_ALIASING_DECODE" value="0" />
<parameter name="SLAVES_INFO" value="0:1:0x0:0x0:both:1:0:0:1" />
<parameter name="DEFAULT_RD_CHANNEL" value="-1" />
<parameter name="PKT_ADDR_H" value="53" />
<parameter name="PKT_DEST_ID_H" value="80" />
<parameter name="PKT_ADDR_L" value="36" />
<parameter name="PKT_DEST_ID_L" value="78" />
<parameter
name="MERLIN_PACKET_FORMAT"
value="ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)" />
<parameter name="CHANNEL_ID" value="1" />
<parameter name="TYPE_OF_TRANSACTION" value="both" />
<parameter name="SECURED_RANGE_PAIRS" value="0" />
<parameter name="SPAN_OFFSET" value="" />
<parameter name="ST_DATA_W" value="94" />
<parameter name="SECURED_RANGE_LIST" value="0" />
<parameter name="DECODER_TYPE" value="1" />
<parameter name="PKT_PROTECTION_H" value="84" />
<parameter name="END_ADDRESS" value="0x0" />
<parameter name="PKT_PROTECTION_L" value="82" />
<parameter name="PKT_TRANS_WRITE" value="56" />
<parameter name="DEFAULT_DESTID" value="0" />
<parameter name="DESTINATION_ID" value="0" />
<parameter name="NON_SECURED_TAG" value="1" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_002.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator
instantiator="niosII_mm_interconnect_0"
as="router_002,router_003,router_005,router_006,router_007" />
<messages>
<message level="Debug" culprit="niosII">queue size: 31 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_002"</message>
<message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_merlin_router:18.1:CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=53,PKT_ADDR_L=36,PKT_DEST_ID_H=80,PKT_DEST_ID_L=78,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_TRANS_READ=57,PKT_TRANS_WRITE=56,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=0:01:0x0:0x0:both:1:0:0:1,1:10:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=7,ST_DATA_W=94,TYPE_OF_TRANSACTION=both,read"
instancePathKey="niosII:.:mm_interconnect_0:.:router_004"
kind="altera_merlin_router"
version="18.1"
name="niosII_mm_interconnect_0_router_004">
<parameter name="ST_CHANNEL_W" value="7" />
<parameter name="DEFAULT_WR_CHANNEL" value="-1" />
<parameter name="PKT_TRANS_READ" value="57" />
<parameter name="START_ADDRESS" value="0x0,0x0" />
<parameter name="DEFAULT_CHANNEL" value="0" />
<parameter name="MEMORY_ALIASING_DECODE" value="0" />
<parameter
name="SLAVES_INFO"
value="0:01:0x0:0x0:both:1:0:0:1,1:10:0x0:0x0:read:1:0:0:1" />
<parameter name="DEFAULT_RD_CHANNEL" value="-1" />
<parameter name="PKT_ADDR_H" value="53" />
<parameter name="PKT_DEST_ID_H" value="80" />
<parameter name="PKT_ADDR_L" value="36" />
<parameter name="PKT_DEST_ID_L" value="78" />
<parameter
name="MERLIN_PACKET_FORMAT"
value="ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)" />
<parameter name="CHANNEL_ID" value="01,10" />
<parameter name="TYPE_OF_TRANSACTION" value="both,read" />
<parameter name="SECURED_RANGE_PAIRS" value="0,0" />
<parameter name="SPAN_OFFSET" value="" />
<parameter name="ST_DATA_W" value="94" />
<parameter name="SECURED_RANGE_LIST" value="0,0" />
<parameter name="DECODER_TYPE" value="1" />
<parameter name="PKT_PROTECTION_H" value="84" />
<parameter name="END_ADDRESS" value="0x0,0x0" />
<parameter name="PKT_PROTECTION_L" value="82" />
<parameter name="PKT_TRANS_WRITE" value="56" />
<parameter name="DEFAULT_DESTID" value="0" />
<parameter name="DESTINATION_ID" value="0,1" />
<parameter name="NON_SECURED_TAG" value="1,1" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_004.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="niosII_mm_interconnect_0" as="router_004" />
<messages>
<message level="Debug" culprit="niosII">queue size: 29 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_004"</message>
<message level="Info" culprit="router_004"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_004</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_merlin_router:18.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=1,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=1,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=53,PKT_ADDR_L=36,PKT_DEST_ID_H=80,PKT_DEST_ID_L=78,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_TRANS_READ=57,PKT_TRANS_WRITE=56,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=1:1:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=7,ST_DATA_W=94,TYPE_OF_TRANSACTION=read"
instancePathKey="niosII:.:mm_interconnect_0:.:router_008"
kind="altera_merlin_router"
version="18.1"
name="niosII_mm_interconnect_0_router_008">
<parameter name="ST_CHANNEL_W" value="7" />
<parameter name="DEFAULT_WR_CHANNEL" value="-1" />
<parameter name="PKT_TRANS_READ" value="57" />
<parameter name="START_ADDRESS" value="0x0" />
<parameter name="DEFAULT_CHANNEL" value="0" />
<parameter name="MEMORY_ALIASING_DECODE" value="0" />
<parameter name="SLAVES_INFO" value="1:1:0x0:0x0:read:1:0:0:1" />
<parameter name="DEFAULT_RD_CHANNEL" value="-1" />
<parameter name="PKT_ADDR_H" value="53" />
<parameter name="PKT_DEST_ID_H" value="80" />
<parameter name="PKT_ADDR_L" value="36" />
<parameter name="PKT_DEST_ID_L" value="78" />
<parameter
name="MERLIN_PACKET_FORMAT"
value="ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)" />
<parameter name="CHANNEL_ID" value="1" />
<parameter name="TYPE_OF_TRANSACTION" value="read" />
<parameter name="SECURED_RANGE_PAIRS" value="0" />
<parameter name="SPAN_OFFSET" value="" />
<parameter name="ST_DATA_W" value="94" />
<parameter name="SECURED_RANGE_LIST" value="0" />
<parameter name="DECODER_TYPE" value="1" />
<parameter name="PKT_PROTECTION_H" value="84" />
<parameter name="END_ADDRESS" value="0x0" />
<parameter name="PKT_PROTECTION_L" value="82" />
<parameter name="PKT_TRANS_WRITE" value="56" />
<parameter name="DEFAULT_DESTID" value="1" />
<parameter name="DESTINATION_ID" value="1" />
<parameter name="NON_SECURED_TAG" value="1" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_008.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="niosII_mm_interconnect_0" as="router_008" />
<messages>
<message level="Debug" culprit="niosII">queue size: 25 starting:altera_merlin_router "submodules/niosII_mm_interconnect_0_router_008"</message>
<message level="Info" culprit="router_008"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_008</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_merlin_demultiplexer:18.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=Cyclone IV E,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),NUM_OUTPUTS=6,ST_CHANNEL_W=7,ST_DATA_W=94,VALID_WIDTH=1"
instancePathKey="niosII:.:mm_interconnect_0:.:cmd_demux"
kind="altera_merlin_demultiplexer"
version="18.1"
name="niosII_mm_interconnect_0_cmd_demux">
<parameter
name="MERLIN_PACKET_FORMAT"
value="ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)" />
<parameter name="ST_CHANNEL_W" value="7" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
<parameter name="VALID_WIDTH" value="1" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="ST_DATA_W" value="94" />
<parameter name="NUM_OUTPUTS" value="6" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="niosII_mm_interconnect_0" as="cmd_demux" />
<messages>
<message level="Debug" culprit="niosII">queue size: 24 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux"</message>
<message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_merlin_demultiplexer:18.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=Cyclone IV E,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=7,ST_DATA_W=94,VALID_WIDTH=1"
instancePathKey="niosII:.:mm_interconnect_0:.:cmd_demux_001"
kind="altera_merlin_demultiplexer"
version="18.1"
name="niosII_mm_interconnect_0_cmd_demux_001">
<parameter
name="MERLIN_PACKET_FORMAT"
value="ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)" />
<parameter name="ST_CHANNEL_W" value="7" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
<parameter name="VALID_WIDTH" value="1" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="ST_DATA_W" value="94" />
<parameter name="NUM_OUTPUTS" value="2" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator
instantiator="niosII_mm_interconnect_0"
as="cmd_demux_001,rsp_demux_002" />
<messages>
<message level="Debug" culprit="niosII">queue size: 23 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_cmd_demux_001"</message>
<message level="Info" culprit="cmd_demux_001"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_001</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_merlin_multiplexer:18.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=1,PKT_TRANS_LOCK=58,ST_CHANNEL_W=7,ST_DATA_W=94,USE_EXTERNAL_ARB=0"
instancePathKey="niosII:.:mm_interconnect_0:.:cmd_mux"
kind="altera_merlin_multiplexer"
version="18.1"
name="niosII_mm_interconnect_0_cmd_mux">
<parameter
name="MERLIN_PACKET_FORMAT"
value="ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)" />
<parameter name="ST_CHANNEL_W" value="7" />
<parameter name="ARBITRATION_SHARES" value="1" />
<parameter name="NUM_INPUTS" value="1" />
<parameter name="PIPELINE_ARB" value="1" />
<parameter name="ARBITRATION_SCHEME" value="round-robin" />
<parameter name="ST_DATA_W" value="94" />
<parameter name="USE_EXTERNAL_ARB" value="0" />
<parameter name="PKT_TRANS_LOCK" value="58" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator
instantiator="niosII_mm_interconnect_0"
as="cmd_mux,cmd_mux_001,cmd_mux_003,cmd_mux_004,cmd_mux_005,cmd_mux_006" />
<messages>
<message level="Debug" culprit="niosII">queue size: 22 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux"</message>
<message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_merlin_multiplexer:18.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=1,PKT_TRANS_LOCK=58,ST_CHANNEL_W=7,ST_DATA_W=94,USE_EXTERNAL_ARB=0"
instancePathKey="niosII:.:mm_interconnect_0:.:cmd_mux_002"
kind="altera_merlin_multiplexer"
version="18.1"
name="niosII_mm_interconnect_0_cmd_mux_002">
<parameter
name="MERLIN_PACKET_FORMAT"
value="ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)" />
<parameter name="ST_CHANNEL_W" value="7" />
<parameter name="ARBITRATION_SHARES" value="1,1" />
<parameter name="NUM_INPUTS" value="2" />
<parameter name="PIPELINE_ARB" value="1" />
<parameter name="ARBITRATION_SCHEME" value="round-robin" />
<parameter name="ST_DATA_W" value="94" />
<parameter name="USE_EXTERNAL_ARB" value="0" />
<parameter name="PKT_TRANS_LOCK" value="58" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="niosII_mm_interconnect_0" as="cmd_mux_002" />
<messages>
<message level="Debug" culprit="niosII">queue size: 20 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_cmd_mux_002"</message>
<message level="Info" culprit="cmd_mux_002"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_002</b>"]]></message>
<message level="Info"><![CDATA[Reusing file <b>C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_merlin_demultiplexer:18.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=Cyclone IV E,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=7,ST_DATA_W=94,VALID_WIDTH=1"
instancePathKey="niosII:.:mm_interconnect_0:.:rsp_demux"
kind="altera_merlin_demultiplexer"
version="18.1"
name="niosII_mm_interconnect_0_rsp_demux">
<parameter
name="MERLIN_PACKET_FORMAT"
value="ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)" />
<parameter name="ST_CHANNEL_W" value="7" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
<parameter name="VALID_WIDTH" value="1" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="ST_DATA_W" value="94" />
<parameter name="NUM_OUTPUTS" value="1" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_demux.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator
instantiator="niosII_mm_interconnect_0"
as="rsp_demux,rsp_demux_001,rsp_demux_003,rsp_demux_004,rsp_demux_005,rsp_demux_006" />
<messages>
<message level="Debug" culprit="niosII">queue size: 15 starting:altera_merlin_demultiplexer "submodules/niosII_mm_interconnect_0_rsp_demux"</message>
<message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_merlin_multiplexer:18.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,1,1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),NUM_INPUTS=6,PIPELINE_ARB=0,PKT_TRANS_LOCK=58,ST_CHANNEL_W=7,ST_DATA_W=94,USE_EXTERNAL_ARB=0"
instancePathKey="niosII:.:mm_interconnect_0:.:rsp_mux"
kind="altera_merlin_multiplexer"
version="18.1"
name="niosII_mm_interconnect_0_rsp_mux">
<parameter
name="MERLIN_PACKET_FORMAT"
value="ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)" />
<parameter name="ST_CHANNEL_W" value="7" />
<parameter name="ARBITRATION_SHARES" value="1,1,1,1,1,1" />
<parameter name="NUM_INPUTS" value="6" />
<parameter name="PIPELINE_ARB" value="0" />
<parameter name="ARBITRATION_SCHEME" value="no-arb" />
<parameter name="ST_DATA_W" value="94" />
<parameter name="USE_EXTERNAL_ARB" value="0" />
<parameter name="PKT_TRANS_LOCK" value="58" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="niosII_mm_interconnect_0" as="rsp_mux" />
<messages>
<message level="Debug" culprit="niosII">queue size: 8 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux"</message>
<message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
<message level="Info"><![CDATA[Reusing file <b>C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_merlin_multiplexer:18.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=58,ST_CHANNEL_W=7,ST_DATA_W=94,USE_EXTERNAL_ARB=0"
instancePathKey="niosII:.:mm_interconnect_0:.:rsp_mux_001"
kind="altera_merlin_multiplexer"
version="18.1"
name="niosII_mm_interconnect_0_rsp_mux_001">
<parameter
name="MERLIN_PACKET_FORMAT"
value="ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81) dest_id(80:78) src_id(77:75) qos(74) begin_burst(73) data_sideband(72) addr_sideband(71) burst_type(70:69) burst_size(68:66) burstwrap(65:63) byte_cnt(62:60) trans_exclusive(59) trans_lock(58) trans_read(57) trans_write(56) trans_posted(55) trans_compressed_read(54) addr(53:36) byteen(35:32) data(31:0)" />
<parameter name="ST_CHANNEL_W" value="7" />
<parameter name="ARBITRATION_SHARES" value="1,1" />
<parameter name="NUM_INPUTS" value="2" />
<parameter name="PIPELINE_ARB" value="0" />
<parameter name="ARBITRATION_SCHEME" value="no-arb" />
<parameter name="ST_DATA_W" value="94" />
<parameter name="USE_EXTERNAL_ARB" value="0" />
<parameter name="PKT_TRANS_LOCK" value="58" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv"
type="SYSTEM_VERILOG"
attributes="" />
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="niosII_mm_interconnect_0" as="rsp_mux_001" />
<messages>
<message level="Debug" culprit="niosII">queue size: 7 starting:altera_merlin_multiplexer "submodules/niosII_mm_interconnect_0_rsp_mux_001"</message>
<message level="Info" culprit="rsp_mux_001"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_001</b>"]]></message>
<message level="Info"><![CDATA[Reusing file <b>C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_avalon_st_adapter:18.1:AUTO_DEVICE=EP4CE115F29C7,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=,inBitsPerSymbol=34,inChannelWidth=0,inDataWidth=34,inEmptyWidth=1,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inUseEmptyPort=0,inUsePackets=0,inUseReady=1,inUseValid=1,outChannelWidth=0,outDataWidth=34,outEmptyWidth=1,outErrorDescriptor=,outErrorWidth=1,outMaxChannel=0,outReadyLatency=0,outUseEmptyPort=0,outUseReady=1,outUseValid=1(altera_clock_bridge:18.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:18.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(error_adapter:18.1:inBitsPerSymbol=34,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=1,inUseEmpty=false,inUseEmptyPort=NO,inUsePackets=false,inUseReady=true,outErrorDescriptor=,outErrorWidth=1)(clock:18.1:)(clock:18.1:)(reset:18.1:)"
instancePathKey="niosII:.:mm_interconnect_0:.:avalon_st_adapter"
kind="altera_avalon_st_adapter"
version="18.1"
name="niosII_mm_interconnect_0_avalon_st_adapter">
<parameter name="inUseValid" value="1" />
<parameter name="inBitsPerSymbol" value="34" />
<parameter name="outUseEmptyPort" value="0" />
<parameter name="inChannelWidth" value="0" />
<parameter name="outErrorWidth" value="1" />
<parameter name="outUseValid" value="1" />
<parameter name="outMaxChannel" value="0" />
<parameter name="inErrorDescriptor" value="" />
<parameter name="inUsePackets" value="0" />
<parameter name="inErrorWidth" value="0" />
<parameter name="inEmptyWidth" value="1" />
<parameter name="inUseReady" value="1" />
<parameter name="outReadyLatency" value="0" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="outDataWidth" value="34" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
<parameter name="inUseEmptyPort" value="0" />
<parameter name="outChannelWidth" value="0" />
<parameter name="inMaxChannel" value="0" />
<parameter name="outUseReady" value="1" />
<parameter name="inReadyLatency" value="0" />
<parameter name="AUTO_DEVICE" value="EP4CE115F29C7" />
<parameter name="inDataWidth" value="34" />
<parameter name="outErrorDescriptor" value="" />
<parameter name="outEmptyWidth" value="1" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v"
type="VERILOG" />
</generatedFiles>
<childGeneratedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
type="SYSTEM_VERILOG"
attributes="" />
</childGeneratedFiles>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
</sourceFiles>
<childSourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
</childSourceFiles>
<instantiator
instantiator="niosII_mm_interconnect_0"
as="avalon_st_adapter,avalon_st_adapter_001,avalon_st_adapter_002,avalon_st_adapter_003,avalon_st_adapter_004,avalon_st_adapter_005,avalon_st_adapter_006" />
<messages>
<message level="Debug" culprit="niosII">queue size: 6 starting:altera_avalon_st_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter"</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug">Transform: CustomInstructionTransform</message>
<message level="Debug">No custom instruction connections, skipping transform </message>
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
<message level="Debug">Transform: MMTransform</message>
<message level="Debug">Transform: InterruptMapperTransform</message>
<message level="Debug">Transform: InterruptSyncTransform</message>
<message level="Debug">Transform: InterruptFanoutTransform</message>
<message level="Debug">Transform: AvalonStreamingTransform</message>
<message level="Debug">Transform: ResetAdaptation</message>
<message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0</b>"]]></message>
<message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
<message level="Debug" culprit="niosII">queue size: 0 starting:error_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0"</message>
<message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="error_adapter:18.1:inBitsPerSymbol=34,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=1,inUseEmpty=false,inUseEmptyPort=NO,inUsePackets=false,inUseReady=true,outErrorDescriptor=,outErrorWidth=1"
instancePathKey="niosII:.:mm_interconnect_0:.:avalon_st_adapter:.:error_adapter_0"
kind="error_adapter"
version="18.1"
name="niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0">
<parameter name="inErrorWidth" value="0" />
<parameter name="inUseReady" value="true" />
<parameter name="inBitsPerSymbol" value="34" />
<parameter name="inChannelWidth" value="0" />
<parameter name="inSymbolsPerBeat" value="1" />
<parameter name="inUseEmptyPort" value="NO" />
<parameter name="outErrorWidth" value="1" />
<parameter name="inMaxChannel" value="0" />
<parameter name="inReadyLatency" value="0" />
<parameter name="outErrorDescriptor" value="" />
<parameter name="inUseEmpty" value="false" />
<parameter name="inErrorDescriptor" value="" />
<parameter name="inUsePackets" value="false" />
<generatedFiles>
<file
path="C:/Software/FPGA/iu3-31m/Lab2/Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="C:/software/intelfpga_lite/18.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator
instantiator="niosII_mm_interconnect_0_avalon_st_adapter"
as="error_adapter_0" />
<messages>
<message level="Debug" culprit="niosII">queue size: 0 starting:error_adapter "submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0"</message>
<message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
</messages>
</entity>
</deploy>