wip lab4, tested module
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@ -0,0 +1,23 @@
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module sdmod (
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input signed [7:0] val,
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input clk,
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input reset,
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output daco
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);
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logic out;
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logic signed [7:0] eps;
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logic signed [7:0] un;
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always_ff @(posedge clk, negedge reset) begin
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if (~reset) begin
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un <= 8'd0;
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end else begin
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un <= val - eps;
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end
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end
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assign daco = (un >= $signed(8'd0)) ? 1'd1 : 1'd0;
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assign eps = (un >= $signed(8'd0)) ? $signed(8'd126) - un : $signed(-8'd126) - un;
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endmodule
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@ -11,6 +11,19 @@ module sigdel
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output logic fout
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);
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logic [7:0] phinc_val, phase, sine;
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//control slave logic
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always_ff @ (posedge clk or negedge clr_n) begin
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if (!clr_n) begin
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phinc_val[7:0] <= 8'd0;
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end else begin
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if (!wr_n) begin
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phinc_val[7:0] <= wr_data[31:0];
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end
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end
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end
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phacc phacc_inst (.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
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defparam phacc_inst.WIDTH = PHACC_WIDTH;
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@ -18,4 +31,7 @@ module sigdel
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.address (phase), .clock (clk), .q(sine)
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);
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sdmod sdmod_inst (
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.val(sine), .clk(clk), .reset(clr_n), .daco(fout)
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);
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endmodule
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@ -0,0 +1,55 @@
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`timescale 1 ns/1 ns
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module lut_mod_tb();
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// Parameters
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localparam CLK_PRD = 20;
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localparam PHACC_WIDTH = 14;
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logic clk, clr_n, wr_n, daco;
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logic [7:0] phinc_val, phase, sine;
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// Instantiate UUT and connect used ports
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phacc phacc (
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.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase)
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);
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defparam phacc.WIDTH = PHACC_WIDTH;
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sinelut sinelut_inst (
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.address(phase), .clock(clk), .q(sine)
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);
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sdmod sdmod_inst (
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.val(sine), .clk(clk), .reset(clr_n), .daco(daco)
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// .val(8'd0), .clk(clk), .reset(clr_n), .daco(daco)
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// .val(8'd255), .clk(clk), .reset(clr_n), .daco(daco)
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);
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// Clock definition
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initial begin
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clk = 0;
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forever #(CLK_PRD/2) clk = ~clk;
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end
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// Reset and initial values definition
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initial begin
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clr_n = 0;
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#(CLK_PRD*5) clr_n = 1;
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end
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// Bus write transaction simulation
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initial begin
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// Wait until system is out of reset
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@(posedge clr_n);
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phinc_val=(2**(PHACC_WIDTH - 8));
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if ((phinc_val <= 255) && (phinc_val != 0)) begin
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#(CLK_PRD * 256 * 10) $stop;
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end else begin
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$display("Error: value of phase increment is out of range! Stopped simulation.");
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#1 $stop;
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end
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end
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endmodule
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@ -50,19 +50,28 @@ set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
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set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/phacc.sv
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name QIP_FILE ../../HDL/IP/sinelut.qip
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set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/sigdel.sv
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set_global_assignment -name SYSTEMVERILOG_FILE inc_lut_tb.sv
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
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set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH inc_lut_tb -section_id eda_simulation
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set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH sigdel_tb -section_id eda_simulation
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set_global_assignment -name EDA_TEST_BENCH_NAME inc_lut_tb -section_id eda_simulation
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id inc_lut_tb
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME inc_lut_tb -section_id inc_lut_tb
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set_global_assignment -name EDA_TEST_BENCH_NAME lut_mod_tb -section_id eda_simulation
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id lut_mod_tb
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME lut_mod_tb -section_id lut_mod_tb
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set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/phacc.sv
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set_global_assignment -name QIP_FILE ../../HDL/IP/sinelut.qip
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set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/sigdel.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/sdmod.sv
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set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT simulation/modelsim/wave.do -section_id eda_simulation
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set_global_assignment -name EDA_TEST_BENCH_FILE inc_lut_tb.sv -section_id inc_lut_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE lut_mod_tb.sv -section_id lut_mod_tb
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set_global_assignment -name EDA_TEST_BENCH_NAME sigdel_tb -section_id eda_simulation
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id sigdel_tb
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME sigdel_tb -section_id sigdel_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE sigdel_tb.sv -section_id sigdel_tb
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -0,0 +1,37 @@
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//top-level module
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module sigdel
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#(
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PHACC_WIDTH = 14
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) (
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//clock and reset
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input logic clk, clr_n,
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//control slave
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input logic [31:0] wr_data,
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input logic wr_n,
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output logic fout
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);
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logic [7:0] phinc_val;
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//control slave logic
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always_ff @ (posedge clk or negedge clr_n) begin
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if (!clr_n) begin
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phinc_val[7:0] <= 8'd0;
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end else begin
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if (!wr_n) begin
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phinc_val[7:0] <= wr_data[31:0];
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end
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end
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end
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phacc phacc_inst (.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
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defparam phacc_inst.WIDTH = PHACC_WIDTH;
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sinelut sinelut_inst (
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.address (phase), .clock (clk), .q(sine)
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);
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sdmod sdmod_inst (
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.val(sine), .clk(clk), .reset(clr_n), .daco(fout)
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);
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endmodule
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@ -0,0 +1,81 @@
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`timescale 1 ns/1 ns
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module sigdel_tb();
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// Parameters
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localparam CLK_PRD = 20;
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localparam SAMPLES_PRD = 256;
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localparam OVERSAMPLING = 4;
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localparam PHACC_WIDTH = 14;
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// Wires and variables to connect to UUT (unit under test)
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logic clk, clr_n, wr_n;
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logic [31:0] wr_data;
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logic [31:0] phinc_val;
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logic fout;
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// Instantiate UUT and connect used ports
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sigdel dut(.clk(clk), .clr_n(clr_n), .wr_n(wr_n), .wr_data(wr_data), .fout(fout));
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defparam dut.PHACC_WIDTH = PHACC_WIDTH;
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// Clock definition
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initial begin
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clk = 0;
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forever #(CLK_PRD/2) clk = ~clk;
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end
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// Reset and initial values definition
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initial begin
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clr_n = 0;
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wr_n = 1;
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wr_data = 'bx;
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#(CLK_PRD*5) clr_n = 1;
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end
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// Bus write transaction simulation
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initial begin
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// Wait until system is out of reset
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@(posedge clr_n);
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// Check if phase increment for required accumulator width
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// and oversamlpling ratio will fit in 8 bits
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phinc_val=(2**(PHACC_WIDTH-8))/OVERSAMPLING;
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if ((phinc_val <= 255) && (phinc_val != 0))
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begin
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// Write phase increment several clock cycles after reset
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#(CLK_PRD*3) write_transaction(phinc_val);
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// Wait for one sine period (for 14-bit phase accumulator case)
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#(CLK_PRD*SAMPLES_PRD*OVERSAMPLING)
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#(CLK_PRD*3) write_transaction(phinc_val*5);
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#(CLK_PRD*SAMPLES_PRD*OVERSAMPLING)
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$stop;
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end
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else
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begin
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//Output simulation error
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$display("Error: value of phase increment is out of range! Stopped simulation.");
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//Stop simulation (small delay needed for $display to work)
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#1 $stop;
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end
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end
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//Single write transaction task
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task write_transaction;
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//input signals
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input [31:0] val;
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//transaction implementation
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begin
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@(posedge clk);
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//assert signals for one clock cycle
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wr_n = 0;
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wr_data = val;
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@(posedge clk);
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//deassert signals
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wr_n = 1;
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wr_data = 'bx;
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end
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endtask
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endmodule
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