lab3 until board programming (pt1 p9)
This commit is contained in:
parent
b86b8e55dc
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2314259147
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@ -0,0 +1,88 @@
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module avalon_pwm
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(
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clk, wr_data, cs, wr_n, addr, clr_n, rd_data, pwm_out
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);
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input clk;
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input [31:0] wr_data;
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input cs;
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input wr_n;
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input addr;
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input clr_n;
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output [31:0] rd_data;
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output [7:0] pwm_out;
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/////////////////////////////////////////////////////////////////////
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// Registers and wires
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reg [31:0] div;
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reg [31:0] duty;
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reg [31:0] counter;
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reg off;
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reg [31:0] rd_data;
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wire div_en, duty_en;
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/////////////////////////////////////////////////////////////////////
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// Avalon slave interface
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//chip select and address decoder
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assign div_en = cs & !wr_n & !addr ;
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assign duty_en = cs & !wr_n & addr ;
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//register write
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always @(posedge clk or negedge clr_n)
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begin
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if (clr_n == 0)
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begin
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div <= 0;
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duty <= 0;
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end
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else
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begin
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if (div_en) div <= wr_data;
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if (duty_en) duty <= wr_data;
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end
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end
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//register read
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always @(*)
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begin
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if (addr == 0)
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rd_data = div;
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else
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rd_data = duty;
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end
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/////////////////////////////////////////////////////////////////////
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// PWM logic
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//PWM counter
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always @(posedge clk or negedge clr_n)
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begin
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if (clr_n == 0)
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counter <= 0;
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else
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if (counter >= div)
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counter <= 0;
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else
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counter <= counter + 1;
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end
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//PWM compare
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always @(posedge clk or negedge clr_n)
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begin
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if (clr_n == 0)
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off <= 0;
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else
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if (counter >= duty)
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off <= 1;
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else
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if (counter == 0)
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off <= 0;
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else
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off <= off;
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end
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assign pwm_out = {8{!off}};
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endmodule
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@ -0,0 +1,17 @@
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module countones(din,ones);
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input [31:0] din;
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output reg [31:0] ones;
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integer i;
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always @(*)
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begin
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ones=0;
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for (i = 0; i<32; i=i+1)
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begin
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if (din[i]) ones=ones+1;
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end
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end
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endmodule
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@ -0,0 +1,70 @@
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# TCL File Generated by Component Editor 18.1
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# Sat Dec 24 22:54:47 MSK 2022
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# DO NOT MODIFY
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#
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# countones_ci "countones_ci" v1.0
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# 2022.12.24.22:54:47
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#
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#
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#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module countones_ci
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME countones_ci
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP "Custom Instruction Modules"
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME countones_ci
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL countones
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file countones.v VERILOG PATH ../HDL/countones.v TOP_LEVEL_FILE
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point nios_custom_instruction_slave
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#
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add_interface nios_custom_instruction_slave nios_custom_instruction end
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set_interface_property nios_custom_instruction_slave clockCycle 0
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set_interface_property nios_custom_instruction_slave operands 1
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set_interface_property nios_custom_instruction_slave ENABLED true
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set_interface_property nios_custom_instruction_slave EXPORT_OF ""
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set_interface_property nios_custom_instruction_slave PORT_NAME_MAP ""
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set_interface_property nios_custom_instruction_slave CMSIS_SVD_VARIABLES ""
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set_interface_property nios_custom_instruction_slave SVD_ADDRESS_GROUP ""
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add_interface_port nios_custom_instruction_slave din dataa Input 32
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add_interface_port nios_custom_instruction_slave ones result Output 32
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105
Top/niosII.qsys
105
Top/niosII.qsys
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@ -17,6 +17,14 @@
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type = "int";
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}
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}
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element countones
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{
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datum _sortIndex
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{
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value = "2";
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type = "int";
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}
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}
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element cpu
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{
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datum _sortIndex
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{
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datum _sortIndex
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{
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value = "3";
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value = "4";
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type = "int";
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}
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}
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{
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datum baseAddress
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{
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value = "135272";
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value = "135336";
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type = "String";
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}
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}
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{
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datum _sortIndex
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{
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value = "2";
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value = "3";
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type = "int";
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}
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}
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type = "String";
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}
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}
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element sem
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element perf_counter
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{
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datum _sortIndex
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{
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value = "5";
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value = "7";
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type = "int";
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}
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}
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element sem.ctl_slave
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{
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datum baseAddress
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{
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value = "135264";
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type = "String";
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}
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}
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element sem.ram_slave
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element perf_counter.control_slave
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{
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datum baseAddress
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{
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type = "String";
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}
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}
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element sem
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{
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datum _sortIndex
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{
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value = "6";
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type = "int";
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}
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}
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element sem.ctl_slave
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{
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datum baseAddress
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{
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value = "135328";
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type = "String";
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}
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}
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element sem.ram_slave
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{
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datum baseAddress
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{
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value = "135232";
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type = "String";
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}
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}
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element sys_clk_timer
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{
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datum _sortIndex
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{
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value = "4";
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value = "5";
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type = "int";
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}
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}
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{
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datum baseAddress
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{
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value = "135232";
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value = "135296";
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type = "String";
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}
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}
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<parameter name="inputClockFrequency" value="0" />
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<parameter name="resetSynchronousEdges" value="NONE" />
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</module>
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<module name="countones" kind="countones_ci" version="1.0" enabled="1" />
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<module name="cpu" kind="altera_nios2_gen2" version="18.1" enabled="1">
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<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
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<parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
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<parameter name="cpuArchRev" value="1" />
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<parameter name="cpuID" value="0" />
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<parameter name="cpuReset" value="false" />
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<parameter name="customInstSlavesSystemInfo" value="<info/>" />
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<parameter name="customInstSlavesSystemInfo"><![CDATA[<info><slave name="countones" baseAddress="0" addressSpan="1" clockCycleType="COMBINATORIAL" /></info>]]></parameter>
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<parameter name="customInstSlavesSystemInfo_nios_a" value="<info/>" />
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<parameter name="customInstSlavesSystemInfo_nios_b" value="<info/>" />
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<parameter name="customInstSlavesSystemInfo_nios_c" value="<info/>" />
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<parameter name="dataAddrWidth" value="18" />
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<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
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<parameter name="dataMasterHighPerformanceMapParam" value="" />
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<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
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<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='perf_counter.control_slave' start='0x21000' end='0x21040' type='altera_avalon_performance_counter.control_slave' /><slave name='sem.ram_slave' start='0x21040' end='0x21080' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21080' end='0x210A0' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x210A0' end='0x210A8' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x210A8' end='0x210B0' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
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<parameter name="data_master_high_performance_paddr_base" value="0" />
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<parameter name="data_master_high_performance_paddr_size" value="0" />
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<parameter name="data_master_paddr_base" value="0" />
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<parameter name="useShallowMemBlocks" value="false" />
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<parameter name="writable" value="true" />
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</module>
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<module
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name="perf_counter"
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kind="altera_avalon_performance_counter"
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version="18.1"
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enabled="1">
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<parameter name="numberOfSections" value="3" />
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</module>
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<module name="sem" kind="sem" version="1.1" enabled="1">
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<parameter name="m" value="32" />
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</module>
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@ -429,7 +461,16 @@
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start="cpu.data_master"
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end="jtag_uart.avalon_jtag_slave">
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="baseAddress" value="0x00021068" />
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<parameter name="baseAddress" value="0x000210a8" />
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<parameter name="defaultConnection" value="false" />
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</connection>
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<connection
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kind="avalon"
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version="18.1"
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start="cpu.data_master"
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end="perf_counter.control_slave">
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="baseAddress" value="0x00021000" />
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<parameter name="defaultConnection" value="false" />
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</connection>
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<connection
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@ -438,7 +479,7 @@
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start="cpu.data_master"
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end="sem.ctl_slave">
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="baseAddress" value="0x00021060" />
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<parameter name="baseAddress" value="0x000210a0" />
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<parameter name="defaultConnection" value="false" />
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</connection>
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<connection
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@ -456,7 +497,7 @@
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start="cpu.data_master"
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end="sem.ram_slave">
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="baseAddress" value="0x00021000" />
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<parameter name="baseAddress" value="0x00021040" />
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<parameter name="defaultConnection" value="false" />
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</connection>
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<connection
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@ -465,7 +506,7 @@
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start="cpu.data_master"
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end="sys_clk_timer.s1">
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="baseAddress" value="0x00021040" />
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<parameter name="baseAddress" value="0x00021080" />
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<parameter name="defaultConnection" value="false" />
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</connection>
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<connection kind="avalon" version="18.1" start="cpu.data_master" end="mem.s2">
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@ -494,6 +535,7 @@
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<connection kind="clock" version="18.1" start="clk.clk" end="cpu.clk" />
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<connection kind="clock" version="18.1" start="clk.clk" end="jtag_uart.clk" />
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<connection kind="clock" version="18.1" start="clk.clk" end="sys_clk_timer.clk" />
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<connection kind="clock" version="18.1" start="clk.clk" end="perf_counter.clk" />
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<connection kind="clock" version="18.1" start="clk.clk" end="mem.clk1" />
|
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<connection kind="clock" version="18.1" start="clk.clk" end="sem.clock" />
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<connection
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|
|
@ -506,6 +548,15 @@
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<connection kind="interrupt" version="18.1" start="cpu.irq" end="jtag_uart.irq">
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<parameter name="irqNumber" value="1" />
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</connection>
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<connection
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kind="nios_custom_instruction"
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version="18.1"
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start="cpu.custom_instruction_master"
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end="countones.nios_custom_instruction_slave">
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<parameter name="CIName" value="countones" />
|
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="baseAddress" value="0" />
|
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</connection>
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<connection kind="reset" version="18.1" start="clk.clk_reset" end="cpu.reset" />
|
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<connection
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kind="reset"
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|
|
@ -517,6 +568,11 @@
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version="18.1"
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start="clk.clk_reset"
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end="sys_clk_timer.reset" />
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<connection
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kind="reset"
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version="18.1"
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start="clk.clk_reset"
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end="perf_counter.reset" />
|
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<connection kind="reset" version="18.1" start="clk.clk_reset" end="mem.reset1" />
|
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<connection kind="reset" version="18.1" start="clk.clk_reset" end="sem.reset_n" />
|
||||
<connection
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|
|
@ -534,6 +590,11 @@
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version="18.1"
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start="cpu.debug_reset_request"
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end="sys_clk_timer.reset" />
|
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<connection
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kind="reset"
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version="18.1"
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start="cpu.debug_reset_request"
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end="perf_counter.reset" />
|
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<connection
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kind="reset"
|
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version="18.1"
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|
|
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1000
Top/niosII.sopcinfo
1000
Top/niosII.sopcinfo
File diff suppressed because it is too large
Load Diff
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@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
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</table>
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<table class="blueBar">
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<tr>
|
||||
<td class="l">2022.12.24.02:16:30</td>
|
||||
<td class="l">2022.12.24.23:18:51</td>
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<td class="r">Datasheet</td>
|
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</tr>
|
||||
</table>
|
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|
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@ -100,6 +100,9 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
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<a href="#module_mem"><b>mem</b>
|
||||
</a> altera_avalon_onchip_memory2 18.1
|
||||
<br/>  
|
||||
<a href="#module_perf_counter"><b>perf_counter</b>
|
||||
</a> altera_avalon_performance_counter 18.1
|
||||
<br/>  
|
||||
<a href="#module_sem"><b>sem</b>
|
||||
</a> sem 1.1
|
||||
<br/>  
|
||||
|
|
@ -144,7 +147,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
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</tr>
|
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<tr>
|
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<td class="slaveb">avalon_jtag_slave </td>
|
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<td class="addr"><span style="color:#989898">0x</span>00021068</td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>000210a8</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
|
|
@ -165,6 +168,19 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<td class="addr"><span style="color:#989898">0x</span>00000000</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavemodule"> 
|
||||
<a href="#module_perf_counter"><b>perf_counter</b>
|
||||
</a>
|
||||
</td>
|
||||
<td class="empty"></td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slaveb">control_slave </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavemodule"> 
|
||||
<a href="#module_sem"><b>sem</b>
|
||||
|
|
@ -175,12 +191,12 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">ctl_slave </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021060</td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>000210a0</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavem">ram_slave </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021040</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
|
|
@ -193,7 +209,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="slaveb">s1 </td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021040</td>
|
||||
<td class="addr"><span style="color:#989898">0x</span>00021080</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
</table>
|
||||
|
|
@ -244,6 +260,51 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_countones"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>countones</h2>countones_ci v1.0
|
||||
<br/>
|
||||
<div class="greydiv">
|
||||
<table class="connectionboxes">
|
||||
<tr>
|
||||
<td class="neighbor" rowspan="2">
|
||||
<a href="#module_cpu">cpu</a>
|
||||
</td>
|
||||
<td class="from">custom_instruction_master  </td>
|
||||
<td class="main" rowspan="2">countones</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  nios_custom_instruction_slave</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_cpu"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
|
|
@ -256,7 +317,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<a href="#module_clk">clk</a>
|
||||
</td>
|
||||
<td class="from">clk  </td>
|
||||
<td class="main" rowspan="31">cpu</td>
|
||||
<td class="main" rowspan="39">cpu</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  clk</td>
|
||||
|
|
@ -303,6 +364,32 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="from">data_master  </td>
|
||||
<td class="neighbor" rowspan="4">
|
||||
<a href="#module_perf_counter">perf_counter</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  control_slave</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="from">debug_reset_request  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  reset</td>
|
||||
</tr>
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
|
|
@ -408,6 +495,22 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<td></td>
|
||||
<td class="to">  reset1</td>
|
||||
</tr>
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="from">custom_instruction_master  </td>
|
||||
<td class="neighbor" rowspan="2">
|
||||
<a href="#module_countones">countones</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  nios_custom_instruction_slave</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<br/>
|
||||
|
|
@ -1107,7 +1210,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">dataSlaveMapParam</td>
|
||||
<td class="parametervalue"><address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map></td>
|
||||
<td class="parametervalue"><address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='perf_counter.control_slave' start='0x21000' end='0x21040' type='altera_avalon_performance_counter.control_slave' /><slave name='sem.ram_slave' start='0x21040' end='0x21080' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21080' end='0x210A0' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x210A0' end='0x210A8' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x210A8' end='0x210B0' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
|
||||
|
|
@ -1163,7 +1266,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">customInstSlavesSystemInfo</td>
|
||||
<td class="parametervalue"><info/></td>
|
||||
<td class="parametervalue"><info><slave name="countones" baseAddress="0" addressSpan="1" clockCycleType="COMBINATORIAL" /></info></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">customInstSlavesSystemInfo_nios_a</td>
|
||||
|
|
@ -1763,6 +1866,90 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_perf_counter"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>perf_counter</h2>altera_avalon_performance_counter v18.1
|
||||
<br/>
|
||||
<div class="greydiv">
|
||||
<table class="connectionboxes">
|
||||
<tr>
|
||||
<td class="neighbor" rowspan="4">
|
||||
<a href="#module_cpu">cpu</a>
|
||||
</td>
|
||||
<td class="from">data_master  </td>
|
||||
<td class="main" rowspan="9">perf_counter</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  control_slave</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="from">debug_reset_request  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  reset</td>
|
||||
</tr>
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="neighbor" rowspan="4">
|
||||
<a href="#module_clk">clk</a>
|
||||
</td>
|
||||
<td class="from">clk  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  clk</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="from">clk_reset  </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  reset</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">numberOfSections</td>
|
||||
<td class="parametervalue">3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">control_slave_address_width</td>
|
||||
<td class="parametervalue">4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">HOW_MANY_SECTIONS</td>
|
||||
<td class="parametervalue">3</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_sem"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
|
|
@ -2038,8 +2225,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0,00 seconds</td>
|
||||
<td class="r">rendering took 0,03 seconds</td>
|
||||
<td class="l">generation took 0,02 seconds</td>
|
||||
<td class="r">rendering took 0,09 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
|
|
|
|||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
|
@ -12,6 +12,44 @@ module niosII (
|
|||
output wire sem_export_green // .green
|
||||
);
|
||||
|
||||
wire cpu_custom_instruction_master_readra; // cpu:D_ci_readra -> cpu_custom_instruction_master_translator:ci_slave_readra
|
||||
wire [4:0] cpu_custom_instruction_master_a; // cpu:D_ci_a -> cpu_custom_instruction_master_translator:ci_slave_a
|
||||
wire [4:0] cpu_custom_instruction_master_b; // cpu:D_ci_b -> cpu_custom_instruction_master_translator:ci_slave_b
|
||||
wire [4:0] cpu_custom_instruction_master_c; // cpu:D_ci_c -> cpu_custom_instruction_master_translator:ci_slave_c
|
||||
wire cpu_custom_instruction_master_readrb; // cpu:D_ci_readrb -> cpu_custom_instruction_master_translator:ci_slave_readrb
|
||||
wire [31:0] cpu_custom_instruction_master_ipending; // cpu:W_ci_ipending -> cpu_custom_instruction_master_translator:ci_slave_ipending
|
||||
wire [7:0] cpu_custom_instruction_master_n; // cpu:D_ci_n -> cpu_custom_instruction_master_translator:ci_slave_n
|
||||
wire [31:0] cpu_custom_instruction_master_result; // cpu_custom_instruction_master_translator:ci_slave_result -> cpu:E_ci_result
|
||||
wire cpu_custom_instruction_master_estatus; // cpu:W_ci_estatus -> cpu_custom_instruction_master_translator:ci_slave_estatus
|
||||
wire [31:0] cpu_custom_instruction_master_datab; // cpu:E_ci_datab -> cpu_custom_instruction_master_translator:ci_slave_datab
|
||||
wire [31:0] cpu_custom_instruction_master_dataa; // cpu:E_ci_dataa -> cpu_custom_instruction_master_translator:ci_slave_dataa
|
||||
wire cpu_custom_instruction_master_writerc; // cpu:D_ci_writerc -> cpu_custom_instruction_master_translator:ci_slave_writerc
|
||||
wire [31:0] cpu_custom_instruction_master_translator_comb_ci_master_result; // cpu_custom_instruction_master_comb_xconnect:ci_slave_result -> cpu_custom_instruction_master_translator:comb_ci_master_result
|
||||
wire cpu_custom_instruction_master_translator_comb_ci_master_readra; // cpu_custom_instruction_master_translator:comb_ci_master_readra -> cpu_custom_instruction_master_comb_xconnect:ci_slave_readra
|
||||
wire [4:0] cpu_custom_instruction_master_translator_comb_ci_master_a; // cpu_custom_instruction_master_translator:comb_ci_master_a -> cpu_custom_instruction_master_comb_xconnect:ci_slave_a
|
||||
wire [4:0] cpu_custom_instruction_master_translator_comb_ci_master_b; // cpu_custom_instruction_master_translator:comb_ci_master_b -> cpu_custom_instruction_master_comb_xconnect:ci_slave_b
|
||||
wire cpu_custom_instruction_master_translator_comb_ci_master_readrb; // cpu_custom_instruction_master_translator:comb_ci_master_readrb -> cpu_custom_instruction_master_comb_xconnect:ci_slave_readrb
|
||||
wire [4:0] cpu_custom_instruction_master_translator_comb_ci_master_c; // cpu_custom_instruction_master_translator:comb_ci_master_c -> cpu_custom_instruction_master_comb_xconnect:ci_slave_c
|
||||
wire cpu_custom_instruction_master_translator_comb_ci_master_estatus; // cpu_custom_instruction_master_translator:comb_ci_master_estatus -> cpu_custom_instruction_master_comb_xconnect:ci_slave_estatus
|
||||
wire [31:0] cpu_custom_instruction_master_translator_comb_ci_master_ipending; // cpu_custom_instruction_master_translator:comb_ci_master_ipending -> cpu_custom_instruction_master_comb_xconnect:ci_slave_ipending
|
||||
wire [31:0] cpu_custom_instruction_master_translator_comb_ci_master_datab; // cpu_custom_instruction_master_translator:comb_ci_master_datab -> cpu_custom_instruction_master_comb_xconnect:ci_slave_datab
|
||||
wire [31:0] cpu_custom_instruction_master_translator_comb_ci_master_dataa; // cpu_custom_instruction_master_translator:comb_ci_master_dataa -> cpu_custom_instruction_master_comb_xconnect:ci_slave_dataa
|
||||
wire cpu_custom_instruction_master_translator_comb_ci_master_writerc; // cpu_custom_instruction_master_translator:comb_ci_master_writerc -> cpu_custom_instruction_master_comb_xconnect:ci_slave_writerc
|
||||
wire [7:0] cpu_custom_instruction_master_translator_comb_ci_master_n; // cpu_custom_instruction_master_translator:comb_ci_master_n -> cpu_custom_instruction_master_comb_xconnect:ci_slave_n
|
||||
wire [31:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_result; // cpu_custom_instruction_master_comb_slave_translator0:ci_slave_result -> cpu_custom_instruction_master_comb_xconnect:ci_master0_result
|
||||
wire cpu_custom_instruction_master_comb_xconnect_ci_master0_readra; // cpu_custom_instruction_master_comb_xconnect:ci_master0_readra -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_readra
|
||||
wire [4:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_a; // cpu_custom_instruction_master_comb_xconnect:ci_master0_a -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_a
|
||||
wire [4:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_b; // cpu_custom_instruction_master_comb_xconnect:ci_master0_b -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_b
|
||||
wire cpu_custom_instruction_master_comb_xconnect_ci_master0_readrb; // cpu_custom_instruction_master_comb_xconnect:ci_master0_readrb -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_readrb
|
||||
wire [4:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_c; // cpu_custom_instruction_master_comb_xconnect:ci_master0_c -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_c
|
||||
wire cpu_custom_instruction_master_comb_xconnect_ci_master0_estatus; // cpu_custom_instruction_master_comb_xconnect:ci_master0_estatus -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_estatus
|
||||
wire [31:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_ipending; // cpu_custom_instruction_master_comb_xconnect:ci_master0_ipending -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_ipending
|
||||
wire [31:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_datab; // cpu_custom_instruction_master_comb_xconnect:ci_master0_datab -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_datab
|
||||
wire [31:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_dataa; // cpu_custom_instruction_master_comb_xconnect:ci_master0_dataa -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_dataa
|
||||
wire cpu_custom_instruction_master_comb_xconnect_ci_master0_writerc; // cpu_custom_instruction_master_comb_xconnect:ci_master0_writerc -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_writerc
|
||||
wire [7:0] cpu_custom_instruction_master_comb_xconnect_ci_master0_n; // cpu_custom_instruction_master_comb_xconnect:ci_master0_n -> cpu_custom_instruction_master_comb_slave_translator0:ci_slave_n
|
||||
wire [31:0] cpu_custom_instruction_master_comb_slave_translator0_ci_master_result; // countones:ones -> cpu_custom_instruction_master_comb_slave_translator0:ci_master_result
|
||||
wire [31:0] cpu_custom_instruction_master_comb_slave_translator0_ci_master_dataa; // cpu_custom_instruction_master_comb_slave_translator0:ci_master_dataa -> countones:din
|
||||
wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata
|
||||
wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest
|
||||
wire cpu_data_master_debugaccess; // cpu:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess
|
||||
|
|
@ -31,6 +69,11 @@ module niosII (
|
|||
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
|
||||
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
|
||||
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
|
||||
wire [31:0] mm_interconnect_0_perf_counter_control_slave_readdata; // perf_counter:readdata -> mm_interconnect_0:perf_counter_control_slave_readdata
|
||||
wire [3:0] mm_interconnect_0_perf_counter_control_slave_address; // mm_interconnect_0:perf_counter_control_slave_address -> perf_counter:address
|
||||
wire mm_interconnect_0_perf_counter_control_slave_begintransfer; // mm_interconnect_0:perf_counter_control_slave_begintransfer -> perf_counter:begintransfer
|
||||
wire mm_interconnect_0_perf_counter_control_slave_write; // mm_interconnect_0:perf_counter_control_slave_write -> perf_counter:write
|
||||
wire [31:0] mm_interconnect_0_perf_counter_control_slave_writedata; // mm_interconnect_0:perf_counter_control_slave_writedata -> perf_counter:writedata
|
||||
wire [31:0] mm_interconnect_0_sem_ctl_slave_readdata; // sem:ctl_rddata -> mm_interconnect_0:sem_ctl_slave_readdata
|
||||
wire [0:0] mm_interconnect_0_sem_ctl_slave_address; // mm_interconnect_0:sem_ctl_slave_address -> sem:ctl_addr
|
||||
wire mm_interconnect_0_sem_ctl_slave_read; // mm_interconnect_0:sem_ctl_slave_read -> sem:ctl_rd
|
||||
|
|
@ -69,10 +112,15 @@ module niosII (
|
|||
wire irq_mapper_receiver0_irq; // sys_clk_timer:irq -> irq_mapper:receiver0_irq
|
||||
wire irq_mapper_receiver1_irq; // jtag_uart:av_irq -> irq_mapper:receiver1_irq
|
||||
wire [31:0] cpu_irq_irq; // irq_mapper:sender_irq -> cpu:irq
|
||||
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [cpu:reset_n, irq_mapper:reset, jtag_uart:rst_n, mem:reset, mm_interconnect_0:cpu_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sem:clrn, sys_clk_timer:reset_n]
|
||||
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [cpu:reset_n, irq_mapper:reset, jtag_uart:rst_n, mem:reset, mm_interconnect_0:cpu_reset_reset_bridge_in_reset_reset, perf_counter:reset_n, rst_translator:in_reset, sem:clrn, sys_clk_timer:reset_n]
|
||||
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [cpu:reset_req, mem:reset_req, rst_translator:reset_req_in]
|
||||
wire cpu_debug_reset_request_reset; // cpu:debug_reset_request -> rst_controller:reset_in1
|
||||
|
||||
countones countones (
|
||||
.din (cpu_custom_instruction_master_comb_slave_translator0_ci_master_dataa), // nios_custom_instruction_slave.dataa
|
||||
.ones (cpu_custom_instruction_master_comb_slave_translator0_ci_master_result) // .result
|
||||
);
|
||||
|
||||
niosII_cpu cpu (
|
||||
.clk (clk_clk), // clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
||||
|
|
@ -99,7 +147,21 @@ module niosII (
|
|||
.debug_mem_slave_waitrequest (mm_interconnect_0_cpu_debug_mem_slave_waitrequest), // .waitrequest
|
||||
.debug_mem_slave_write (mm_interconnect_0_cpu_debug_mem_slave_write), // .write
|
||||
.debug_mem_slave_writedata (mm_interconnect_0_cpu_debug_mem_slave_writedata), // .writedata
|
||||
.dummy_ci_port () // custom_instruction_master.readra
|
||||
.E_ci_result (cpu_custom_instruction_master_result), // custom_instruction_master.result
|
||||
.D_ci_a (cpu_custom_instruction_master_a), // .a
|
||||
.D_ci_b (cpu_custom_instruction_master_b), // .b
|
||||
.D_ci_c (cpu_custom_instruction_master_c), // .c
|
||||
.D_ci_n (cpu_custom_instruction_master_n), // .n
|
||||
.D_ci_readra (cpu_custom_instruction_master_readra), // .readra
|
||||
.D_ci_readrb (cpu_custom_instruction_master_readrb), // .readrb
|
||||
.D_ci_writerc (cpu_custom_instruction_master_writerc), // .writerc
|
||||
.E_ci_dataa (cpu_custom_instruction_master_dataa), // .dataa
|
||||
.E_ci_datab (cpu_custom_instruction_master_datab), // .datab
|
||||
.E_ci_multi_clock (), // .clk
|
||||
.E_ci_multi_reset (), // .reset
|
||||
.E_ci_multi_reset_req (), // .reset_req
|
||||
.W_ci_estatus (cpu_custom_instruction_master_estatus), // .estatus
|
||||
.W_ci_ipending (cpu_custom_instruction_master_ipending) // .ipending
|
||||
);
|
||||
|
||||
niosII_jtag_uart jtag_uart (
|
||||
|
|
@ -136,6 +198,16 @@ module niosII (
|
|||
.freeze (1'b0) // (terminated)
|
||||
);
|
||||
|
||||
niosII_perf_counter perf_counter (
|
||||
.clk (clk_clk), // clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
||||
.address (mm_interconnect_0_perf_counter_control_slave_address), // control_slave.address
|
||||
.begintransfer (mm_interconnect_0_perf_counter_control_slave_begintransfer), // .begintransfer
|
||||
.readdata (mm_interconnect_0_perf_counter_control_slave_readdata), // .readdata
|
||||
.write (mm_interconnect_0_perf_counter_control_slave_write), // .write
|
||||
.writedata (mm_interconnect_0_perf_counter_control_slave_writedata) // .writedata
|
||||
);
|
||||
|
||||
dec #(
|
||||
.m (32)
|
||||
) sem (
|
||||
|
|
@ -166,6 +238,137 @@ module niosII (
|
|||
.irq (irq_mapper_receiver0_irq) // irq.irq
|
||||
);
|
||||
|
||||
altera_customins_master_translator #(
|
||||
.SHARED_COMB_AND_MULTI (1)
|
||||
) cpu_custom_instruction_master_translator (
|
||||
.ci_slave_dataa (cpu_custom_instruction_master_dataa), // ci_slave.dataa
|
||||
.ci_slave_datab (cpu_custom_instruction_master_datab), // .datab
|
||||
.ci_slave_result (cpu_custom_instruction_master_result), // .result
|
||||
.ci_slave_n (cpu_custom_instruction_master_n), // .n
|
||||
.ci_slave_readra (cpu_custom_instruction_master_readra), // .readra
|
||||
.ci_slave_readrb (cpu_custom_instruction_master_readrb), // .readrb
|
||||
.ci_slave_writerc (cpu_custom_instruction_master_writerc), // .writerc
|
||||
.ci_slave_a (cpu_custom_instruction_master_a), // .a
|
||||
.ci_slave_b (cpu_custom_instruction_master_b), // .b
|
||||
.ci_slave_c (cpu_custom_instruction_master_c), // .c
|
||||
.ci_slave_ipending (cpu_custom_instruction_master_ipending), // .ipending
|
||||
.ci_slave_estatus (cpu_custom_instruction_master_estatus), // .estatus
|
||||
.comb_ci_master_dataa (cpu_custom_instruction_master_translator_comb_ci_master_dataa), // comb_ci_master.dataa
|
||||
.comb_ci_master_datab (cpu_custom_instruction_master_translator_comb_ci_master_datab), // .datab
|
||||
.comb_ci_master_result (cpu_custom_instruction_master_translator_comb_ci_master_result), // .result
|
||||
.comb_ci_master_n (cpu_custom_instruction_master_translator_comb_ci_master_n), // .n
|
||||
.comb_ci_master_readra (cpu_custom_instruction_master_translator_comb_ci_master_readra), // .readra
|
||||
.comb_ci_master_readrb (cpu_custom_instruction_master_translator_comb_ci_master_readrb), // .readrb
|
||||
.comb_ci_master_writerc (cpu_custom_instruction_master_translator_comb_ci_master_writerc), // .writerc
|
||||
.comb_ci_master_a (cpu_custom_instruction_master_translator_comb_ci_master_a), // .a
|
||||
.comb_ci_master_b (cpu_custom_instruction_master_translator_comb_ci_master_b), // .b
|
||||
.comb_ci_master_c (cpu_custom_instruction_master_translator_comb_ci_master_c), // .c
|
||||
.comb_ci_master_ipending (cpu_custom_instruction_master_translator_comb_ci_master_ipending), // .ipending
|
||||
.comb_ci_master_estatus (cpu_custom_instruction_master_translator_comb_ci_master_estatus), // .estatus
|
||||
.ci_slave_multi_clk (1'b0), // (terminated)
|
||||
.ci_slave_multi_reset (1'b0), // (terminated)
|
||||
.ci_slave_multi_clken (1'b0), // (terminated)
|
||||
.ci_slave_multi_reset_req (1'b0), // (terminated)
|
||||
.ci_slave_multi_start (1'b0), // (terminated)
|
||||
.ci_slave_multi_done (), // (terminated)
|
||||
.ci_slave_multi_dataa (32'b00000000000000000000000000000000), // (terminated)
|
||||
.ci_slave_multi_datab (32'b00000000000000000000000000000000), // (terminated)
|
||||
.ci_slave_multi_result (), // (terminated)
|
||||
.ci_slave_multi_n (8'b00000000), // (terminated)
|
||||
.ci_slave_multi_readra (1'b0), // (terminated)
|
||||
.ci_slave_multi_readrb (1'b0), // (terminated)
|
||||
.ci_slave_multi_writerc (1'b0), // (terminated)
|
||||
.ci_slave_multi_a (5'b00000), // (terminated)
|
||||
.ci_slave_multi_b (5'b00000), // (terminated)
|
||||
.ci_slave_multi_c (5'b00000), // (terminated)
|
||||
.multi_ci_master_clk (), // (terminated)
|
||||
.multi_ci_master_reset (), // (terminated)
|
||||
.multi_ci_master_clken (), // (terminated)
|
||||
.multi_ci_master_reset_req (), // (terminated)
|
||||
.multi_ci_master_start (), // (terminated)
|
||||
.multi_ci_master_done (1'b0), // (terminated)
|
||||
.multi_ci_master_dataa (), // (terminated)
|
||||
.multi_ci_master_datab (), // (terminated)
|
||||
.multi_ci_master_result (32'b00000000000000000000000000000000), // (terminated)
|
||||
.multi_ci_master_n (), // (terminated)
|
||||
.multi_ci_master_readra (), // (terminated)
|
||||
.multi_ci_master_readrb (), // (terminated)
|
||||
.multi_ci_master_writerc (), // (terminated)
|
||||
.multi_ci_master_a (), // (terminated)
|
||||
.multi_ci_master_b (), // (terminated)
|
||||
.multi_ci_master_c () // (terminated)
|
||||
);
|
||||
|
||||
niosII_cpu_custom_instruction_master_comb_xconnect cpu_custom_instruction_master_comb_xconnect (
|
||||
.ci_slave_dataa (cpu_custom_instruction_master_translator_comb_ci_master_dataa), // ci_slave.dataa
|
||||
.ci_slave_datab (cpu_custom_instruction_master_translator_comb_ci_master_datab), // .datab
|
||||
.ci_slave_result (cpu_custom_instruction_master_translator_comb_ci_master_result), // .result
|
||||
.ci_slave_n (cpu_custom_instruction_master_translator_comb_ci_master_n), // .n
|
||||
.ci_slave_readra (cpu_custom_instruction_master_translator_comb_ci_master_readra), // .readra
|
||||
.ci_slave_readrb (cpu_custom_instruction_master_translator_comb_ci_master_readrb), // .readrb
|
||||
.ci_slave_writerc (cpu_custom_instruction_master_translator_comb_ci_master_writerc), // .writerc
|
||||
.ci_slave_a (cpu_custom_instruction_master_translator_comb_ci_master_a), // .a
|
||||
.ci_slave_b (cpu_custom_instruction_master_translator_comb_ci_master_b), // .b
|
||||
.ci_slave_c (cpu_custom_instruction_master_translator_comb_ci_master_c), // .c
|
||||
.ci_slave_ipending (cpu_custom_instruction_master_translator_comb_ci_master_ipending), // .ipending
|
||||
.ci_slave_estatus (cpu_custom_instruction_master_translator_comb_ci_master_estatus), // .estatus
|
||||
.ci_master0_dataa (cpu_custom_instruction_master_comb_xconnect_ci_master0_dataa), // ci_master0.dataa
|
||||
.ci_master0_datab (cpu_custom_instruction_master_comb_xconnect_ci_master0_datab), // .datab
|
||||
.ci_master0_result (cpu_custom_instruction_master_comb_xconnect_ci_master0_result), // .result
|
||||
.ci_master0_n (cpu_custom_instruction_master_comb_xconnect_ci_master0_n), // .n
|
||||
.ci_master0_readra (cpu_custom_instruction_master_comb_xconnect_ci_master0_readra), // .readra
|
||||
.ci_master0_readrb (cpu_custom_instruction_master_comb_xconnect_ci_master0_readrb), // .readrb
|
||||
.ci_master0_writerc (cpu_custom_instruction_master_comb_xconnect_ci_master0_writerc), // .writerc
|
||||
.ci_master0_a (cpu_custom_instruction_master_comb_xconnect_ci_master0_a), // .a
|
||||
.ci_master0_b (cpu_custom_instruction_master_comb_xconnect_ci_master0_b), // .b
|
||||
.ci_master0_c (cpu_custom_instruction_master_comb_xconnect_ci_master0_c), // .c
|
||||
.ci_master0_ipending (cpu_custom_instruction_master_comb_xconnect_ci_master0_ipending), // .ipending
|
||||
.ci_master0_estatus (cpu_custom_instruction_master_comb_xconnect_ci_master0_estatus) // .estatus
|
||||
);
|
||||
|
||||
altera_customins_slave_translator #(
|
||||
.N_WIDTH (8),
|
||||
.USE_DONE (0),
|
||||
.NUM_FIXED_CYCLES (0)
|
||||
) cpu_custom_instruction_master_comb_slave_translator0 (
|
||||
.ci_slave_dataa (cpu_custom_instruction_master_comb_xconnect_ci_master0_dataa), // ci_slave.dataa
|
||||
.ci_slave_datab (cpu_custom_instruction_master_comb_xconnect_ci_master0_datab), // .datab
|
||||
.ci_slave_result (cpu_custom_instruction_master_comb_xconnect_ci_master0_result), // .result
|
||||
.ci_slave_n (cpu_custom_instruction_master_comb_xconnect_ci_master0_n), // .n
|
||||
.ci_slave_readra (cpu_custom_instruction_master_comb_xconnect_ci_master0_readra), // .readra
|
||||
.ci_slave_readrb (cpu_custom_instruction_master_comb_xconnect_ci_master0_readrb), // .readrb
|
||||
.ci_slave_writerc (cpu_custom_instruction_master_comb_xconnect_ci_master0_writerc), // .writerc
|
||||
.ci_slave_a (cpu_custom_instruction_master_comb_xconnect_ci_master0_a), // .a
|
||||
.ci_slave_b (cpu_custom_instruction_master_comb_xconnect_ci_master0_b), // .b
|
||||
.ci_slave_c (cpu_custom_instruction_master_comb_xconnect_ci_master0_c), // .c
|
||||
.ci_slave_ipending (cpu_custom_instruction_master_comb_xconnect_ci_master0_ipending), // .ipending
|
||||
.ci_slave_estatus (cpu_custom_instruction_master_comb_xconnect_ci_master0_estatus), // .estatus
|
||||
.ci_master_dataa (cpu_custom_instruction_master_comb_slave_translator0_ci_master_dataa), // ci_master.dataa
|
||||
.ci_master_result (cpu_custom_instruction_master_comb_slave_translator0_ci_master_result), // .result
|
||||
.ci_master_datab (), // (terminated)
|
||||
.ci_master_n (), // (terminated)
|
||||
.ci_master_readra (), // (terminated)
|
||||
.ci_master_readrb (), // (terminated)
|
||||
.ci_master_writerc (), // (terminated)
|
||||
.ci_master_a (), // (terminated)
|
||||
.ci_master_b (), // (terminated)
|
||||
.ci_master_c (), // (terminated)
|
||||
.ci_master_ipending (), // (terminated)
|
||||
.ci_master_estatus (), // (terminated)
|
||||
.ci_master_clk (), // (terminated)
|
||||
.ci_master_clken (), // (terminated)
|
||||
.ci_master_reset_req (), // (terminated)
|
||||
.ci_master_reset (), // (terminated)
|
||||
.ci_master_start (), // (terminated)
|
||||
.ci_master_done (1'b0), // (terminated)
|
||||
.ci_slave_clk (1'b0), // (terminated)
|
||||
.ci_slave_clken (1'b0), // (terminated)
|
||||
.ci_slave_reset_req (1'b0), // (terminated)
|
||||
.ci_slave_reset (1'b0), // (terminated)
|
||||
.ci_slave_start (1'b0), // (terminated)
|
||||
.ci_slave_done () // (terminated)
|
||||
);
|
||||
|
||||
niosII_mm_interconnect_0 mm_interconnect_0 (
|
||||
.clk_clk_clk (clk_clk), // clk_clk.clk
|
||||
.cpu_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // cpu_reset_reset_bridge_in_reset.reset
|
||||
|
|
@ -210,6 +413,11 @@ module niosII (
|
|||
.mem_s2_byteenable (mm_interconnect_0_mem_s2_byteenable), // .byteenable
|
||||
.mem_s2_chipselect (mm_interconnect_0_mem_s2_chipselect), // .chipselect
|
||||
.mem_s2_clken (mm_interconnect_0_mem_s2_clken), // .clken
|
||||
.perf_counter_control_slave_address (mm_interconnect_0_perf_counter_control_slave_address), // perf_counter_control_slave.address
|
||||
.perf_counter_control_slave_write (mm_interconnect_0_perf_counter_control_slave_write), // .write
|
||||
.perf_counter_control_slave_readdata (mm_interconnect_0_perf_counter_control_slave_readdata), // .readdata
|
||||
.perf_counter_control_slave_writedata (mm_interconnect_0_perf_counter_control_slave_writedata), // .writedata
|
||||
.perf_counter_control_slave_begintransfer (mm_interconnect_0_perf_counter_control_slave_begintransfer), // .begintransfer
|
||||
.sem_ctl_slave_address (mm_interconnect_0_sem_ctl_slave_address), // sem_ctl_slave.address
|
||||
.sem_ctl_slave_write (mm_interconnect_0_sem_ctl_slave_write), // .write
|
||||
.sem_ctl_slave_read (mm_interconnect_0_sem_ctl_slave_read), // .read
|
||||
|
|
|
|||
|
|
@ -32,7 +32,21 @@ module niosII_cpu (
|
|||
output wire debug_mem_slave_waitrequest, // .waitrequest
|
||||
input wire debug_mem_slave_write, // .write
|
||||
input wire [31:0] debug_mem_slave_writedata, // .writedata
|
||||
output wire dummy_ci_port // custom_instruction_master.readra
|
||||
input wire [31:0] E_ci_result, // custom_instruction_master.result
|
||||
output wire [4:0] D_ci_a, // .a
|
||||
output wire [4:0] D_ci_b, // .b
|
||||
output wire [4:0] D_ci_c, // .c
|
||||
output wire [7:0] D_ci_n, // .n
|
||||
output wire D_ci_readra, // .readra
|
||||
output wire D_ci_readrb, // .readrb
|
||||
output wire D_ci_writerc, // .writerc
|
||||
output wire [31:0] E_ci_dataa, // .dataa
|
||||
output wire [31:0] E_ci_datab, // .datab
|
||||
output wire E_ci_multi_clock, // .clk
|
||||
output wire E_ci_multi_reset, // .reset
|
||||
output wire E_ci_multi_reset_req, // .reset_req
|
||||
output wire W_ci_estatus, // .estatus
|
||||
output wire [31:0] W_ci_ipending // .ipending
|
||||
);
|
||||
|
||||
niosII_cpu_cpu cpu (
|
||||
|
|
@ -61,7 +75,21 @@ module niosII_cpu (
|
|||
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
|
||||
.debug_mem_slave_write (debug_mem_slave_write), // .write
|
||||
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
|
||||
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
|
||||
.E_ci_result (E_ci_result), // custom_instruction_master.result
|
||||
.D_ci_a (D_ci_a), // .a
|
||||
.D_ci_b (D_ci_b), // .b
|
||||
.D_ci_c (D_ci_c), // .c
|
||||
.D_ci_n (D_ci_n), // .n
|
||||
.D_ci_readra (D_ci_readra), // .readra
|
||||
.D_ci_readrb (D_ci_readrb), // .readrb
|
||||
.D_ci_writerc (D_ci_writerc), // .writerc
|
||||
.E_ci_dataa (E_ci_dataa), // .dataa
|
||||
.E_ci_datab (E_ci_datab), // .datab
|
||||
.E_ci_multi_clock (E_ci_multi_clock), // .clk
|
||||
.E_ci_multi_reset (E_ci_multi_reset), // .reset
|
||||
.E_ci_multi_reset_req (E_ci_multi_reset_req), // .reset_req
|
||||
.W_ci_estatus (W_ci_estatus), // .estatus
|
||||
.W_ci_ipending (W_ci_ipending) // .ipending
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -2833,6 +2833,7 @@ endmodule
|
|||
|
||||
module niosII_cpu_cpu (
|
||||
// inputs:
|
||||
E_ci_result,
|
||||
clk,
|
||||
d_readdata,
|
||||
d_waitrequest,
|
||||
|
|
@ -2849,6 +2850,21 @@ module niosII_cpu_cpu (
|
|||
reset_req,
|
||||
|
||||
// outputs:
|
||||
D_ci_a,
|
||||
D_ci_b,
|
||||
D_ci_c,
|
||||
D_ci_n,
|
||||
D_ci_readra,
|
||||
D_ci_readrb,
|
||||
D_ci_writerc,
|
||||
E_ci_dataa,
|
||||
E_ci_datab,
|
||||
E_ci_multi_clock,
|
||||
E_ci_multi_reset,
|
||||
E_ci_multi_reset_req,
|
||||
W_ci_estatus,
|
||||
W_ci_ipending,
|
||||
W_ci_status,
|
||||
d_address,
|
||||
d_byteenable,
|
||||
d_read,
|
||||
|
|
@ -2858,12 +2874,26 @@ module niosII_cpu_cpu (
|
|||
debug_mem_slave_readdata,
|
||||
debug_mem_slave_waitrequest,
|
||||
debug_reset_request,
|
||||
dummy_ci_port,
|
||||
i_address,
|
||||
i_read
|
||||
)
|
||||
;
|
||||
|
||||
output [ 4: 0] D_ci_a;
|
||||
output [ 4: 0] D_ci_b;
|
||||
output [ 4: 0] D_ci_c;
|
||||
output [ 7: 0] D_ci_n;
|
||||
output D_ci_readra;
|
||||
output D_ci_readrb;
|
||||
output D_ci_writerc;
|
||||
output [ 31: 0] E_ci_dataa;
|
||||
output [ 31: 0] E_ci_datab;
|
||||
output E_ci_multi_clock;
|
||||
output E_ci_multi_reset;
|
||||
output E_ci_multi_reset_req;
|
||||
output W_ci_estatus;
|
||||
output [ 31: 0] W_ci_ipending;
|
||||
output W_ci_status;
|
||||
output [ 17: 0] d_address;
|
||||
output [ 3: 0] d_byteenable;
|
||||
output d_read;
|
||||
|
|
@ -2873,9 +2903,9 @@ module niosII_cpu_cpu (
|
|||
output [ 31: 0] debug_mem_slave_readdata;
|
||||
output debug_mem_slave_waitrequest;
|
||||
output debug_reset_request;
|
||||
output dummy_ci_port;
|
||||
output [ 17: 0] i_address;
|
||||
output i_read;
|
||||
input [ 31: 0] E_ci_result;
|
||||
input clk;
|
||||
input [ 31: 0] d_readdata;
|
||||
input d_waitrequest;
|
||||
|
|
@ -2893,6 +2923,13 @@ module niosII_cpu_cpu (
|
|||
|
||||
|
||||
reg A_valid_from_M /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
|
||||
wire [ 4: 0] D_ci_a;
|
||||
wire [ 4: 0] D_ci_b;
|
||||
wire [ 4: 0] D_ci_c;
|
||||
wire [ 7: 0] D_ci_n;
|
||||
wire D_ci_readra;
|
||||
wire D_ci_readrb;
|
||||
wire D_ci_writerc;
|
||||
wire [ 1: 0] D_compare_op;
|
||||
wire D_ctrl_alu_force_and;
|
||||
wire D_ctrl_alu_force_xor;
|
||||
|
|
@ -2942,7 +2979,7 @@ wire D_ctrl_uncond_cti_non_br;
|
|||
wire D_ctrl_unsigned_lo_imm16;
|
||||
wire D_ctrl_wrctl_inst;
|
||||
wire [ 4: 0] D_dst_regnum;
|
||||
wire [ 55: 0] D_inst;
|
||||
wire [ 71: 0] D_inst;
|
||||
wire D_is_opx_inst;
|
||||
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
|
||||
wire [ 4: 0] D_iw_a;
|
||||
|
|
@ -2993,6 +3030,7 @@ wire D_op_cmpltu;
|
|||
wire D_op_cmpltui;
|
||||
wire D_op_cmpne;
|
||||
wire D_op_cmpnei;
|
||||
wire D_op_countones;
|
||||
wire D_op_crst;
|
||||
wire D_op_custom;
|
||||
wire D_op_div;
|
||||
|
|
@ -3100,8 +3138,12 @@ reg E_alu_sub;
|
|||
wire [ 32: 0] E_arith_result;
|
||||
wire [ 31: 0] E_arith_src1;
|
||||
wire [ 31: 0] E_arith_src2;
|
||||
wire [ 31: 0] E_ci_dataa;
|
||||
wire [ 31: 0] E_ci_datab;
|
||||
wire E_ci_multi_clock;
|
||||
wire E_ci_multi_reset;
|
||||
wire E_ci_multi_reset_req;
|
||||
wire E_ci_multi_stall;
|
||||
wire [ 31: 0] E_ci_result;
|
||||
wire E_cmp_result;
|
||||
wire [ 31: 0] E_control_rd_data;
|
||||
wire E_eq;
|
||||
|
|
@ -3154,7 +3196,7 @@ wire [ 5: 0] F_av_iw_opx;
|
|||
wire F_av_mem16;
|
||||
wire F_av_mem32;
|
||||
wire F_av_mem8;
|
||||
wire [ 55: 0] F_inst;
|
||||
wire [ 71: 0] F_inst;
|
||||
wire F_is_opx_inst;
|
||||
wire [ 31: 0] F_iw;
|
||||
wire [ 4: 0] F_iw_a;
|
||||
|
|
@ -3202,6 +3244,7 @@ wire F_op_cmpltu;
|
|||
wire F_op_cmpltui;
|
||||
wire F_op_cmpne;
|
||||
wire F_op_cmpnei;
|
||||
wire F_op_countones;
|
||||
wire F_op_crst;
|
||||
wire F_op_custom;
|
||||
wire F_op_div;
|
||||
|
|
@ -3432,6 +3475,9 @@ reg W_bstatus_reg;
|
|||
wire W_bstatus_reg_inst_nxt;
|
||||
wire W_bstatus_reg_nxt;
|
||||
reg [ 31: 0] W_cdsr_reg;
|
||||
wire W_ci_estatus;
|
||||
wire [ 31: 0] W_ci_ipending;
|
||||
wire W_ci_status;
|
||||
reg W_cmp_result;
|
||||
reg [ 31: 0] W_control_rd_data;
|
||||
wire [ 31: 0] W_cpuid_reg;
|
||||
|
|
@ -3496,7 +3542,6 @@ wire [ 31: 0] debug_mem_slave_readdata;
|
|||
wire debug_mem_slave_reset;
|
||||
wire debug_mem_slave_waitrequest;
|
||||
wire debug_reset_request;
|
||||
wire dummy_ci_port;
|
||||
reg hbreak_enabled;
|
||||
reg hbreak_pending;
|
||||
wire hbreak_pending_nxt;
|
||||
|
|
@ -3722,6 +3767,7 @@ reg wait_for_one_post_bret_inst;
|
|||
assign F_op_intr = (F_iw_opx == 61) & F_is_opx_inst;
|
||||
assign F_op_crst = (F_iw_opx == 62) & F_is_opx_inst;
|
||||
assign F_op_opx_rsv63 = (F_iw_opx == 63) & F_is_opx_inst;
|
||||
assign F_op_countones = F_op_custom & 1'b1;
|
||||
assign F_is_opx_inst = F_iw_op == 58;
|
||||
assign D_op_call = D_iw_op == 0;
|
||||
assign D_op_jmpi = D_iw_op == 1;
|
||||
|
|
@ -3850,11 +3896,25 @@ reg wait_for_one_post_bret_inst;
|
|||
assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
|
||||
assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
|
||||
assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
|
||||
assign D_op_countones = D_op_custom & 1'b1;
|
||||
assign D_is_opx_inst = D_iw_op == 58;
|
||||
assign R_en = 1'b1;
|
||||
assign E_ci_result = 0;
|
||||
assign E_ci_dataa = E_src1;
|
||||
assign E_ci_datab = E_src2;
|
||||
assign W_ci_ipending = W_ipending_reg;
|
||||
assign W_ci_status = W_status_reg;
|
||||
assign W_ci_estatus = W_estatus_reg;
|
||||
assign D_ci_n = D_iw_custom_n;
|
||||
assign D_ci_a = D_iw_a;
|
||||
assign D_ci_b = D_iw_b;
|
||||
assign D_ci_c = D_iw_c;
|
||||
assign D_ci_readra = D_iw_custom_readra;
|
||||
assign D_ci_readrb = D_iw_custom_readrb;
|
||||
assign D_ci_writerc = D_iw_custom_writerc;
|
||||
assign E_ci_multi_clock = clk;
|
||||
assign E_ci_multi_reset = ~reset_n;
|
||||
assign E_ci_multi_reset_req = reset_req;
|
||||
//custom_instruction_master, which is an e_custom_instruction_master
|
||||
assign dummy_ci_port = 1'b0;
|
||||
assign E_ci_multi_stall = 1'b0;
|
||||
assign iactive = irq[31 : 0] & 32'b00000000000000000000000000000011;
|
||||
assign F_pc_sel_nxt = (R_ctrl_exception | W_rf_ecc_unrecoverable_valid) ? 2'b00 :
|
||||
|
|
@ -4577,7 +4637,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex"
|
|||
//debug_mem_slave, which is an e_avalon_slave
|
||||
assign debug_mem_slave_clk = clk;
|
||||
assign debug_mem_slave_reset = ~reset_n;
|
||||
assign D_ctrl_custom = 1'b0;
|
||||
assign D_ctrl_custom = D_op_countones;
|
||||
assign R_ctrl_custom_nxt = D_ctrl_custom;
|
||||
always @(posedge clk or negedge reset_n)
|
||||
begin
|
||||
|
|
@ -5226,7 +5286,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex"
|
|||
end
|
||||
|
||||
|
||||
assign D_ctrl_b_is_dst = D_op_addi|
|
||||
assign D_ctrl_b_is_dst = (D_op_addi|
|
||||
D_op_andhi|
|
||||
D_op_orhi|
|
||||
D_op_xorhi|
|
||||
|
|
@ -5254,7 +5314,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex"
|
|||
D_op_initd|
|
||||
D_op_initda|
|
||||
D_op_flushd|
|
||||
D_op_flushda;
|
||||
D_op_flushda) & ~D_op_custom;
|
||||
|
||||
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
|
||||
always @(posedge clk or negedge reset_n)
|
||||
|
|
@ -5266,7 +5326,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex"
|
|||
end
|
||||
|
||||
|
||||
assign D_ctrl_ignore_dst = D_op_br|
|
||||
assign D_ctrl_ignore_dst = (D_op_br|
|
||||
D_op_bge|
|
||||
D_op_blt|
|
||||
D_op_bne|
|
||||
|
|
@ -5279,7 +5339,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex"
|
|||
D_op_stbio|
|
||||
D_op_sthio|
|
||||
D_op_stwio|
|
||||
D_op_jmpi;
|
||||
D_op_jmpi) | (D_op_custom & ~D_iw_custom_writerc);
|
||||
|
||||
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
|
||||
always @(posedge clk or negedge reset_n)
|
||||
|
|
@ -5466,183 +5526,185 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex"
|
|||
|
||||
//synthesis translate_off
|
||||
//////////////// SIMULATION-ONLY CONTENTS
|
||||
assign F_inst = (F_op_call)? 56'h20202063616c6c :
|
||||
(F_op_jmpi)? 56'h2020206a6d7069 :
|
||||
(F_op_ldbu)? 56'h2020206c646275 :
|
||||
(F_op_addi)? 56'h20202061646469 :
|
||||
(F_op_stb)? 56'h20202020737462 :
|
||||
(F_op_br)? 56'h20202020206272 :
|
||||
(F_op_ldb)? 56'h202020206c6462 :
|
||||
(F_op_cmpgei)? 56'h20636d70676569 :
|
||||
(F_op_ldhu)? 56'h2020206c646875 :
|
||||
(F_op_andi)? 56'h202020616e6469 :
|
||||
(F_op_sth)? 56'h20202020737468 :
|
||||
(F_op_bge)? 56'h20202020626765 :
|
||||
(F_op_ldh)? 56'h202020206c6468 :
|
||||
(F_op_cmplti)? 56'h20636d706c7469 :
|
||||
(F_op_initda)? 56'h20696e69746461 :
|
||||
(F_op_ori)? 56'h202020206f7269 :
|
||||
(F_op_stw)? 56'h20202020737477 :
|
||||
(F_op_blt)? 56'h20202020626c74 :
|
||||
(F_op_ldw)? 56'h202020206c6477 :
|
||||
(F_op_cmpnei)? 56'h20636d706e6569 :
|
||||
(F_op_flushda)? 56'h666c7573686461 :
|
||||
(F_op_xori)? 56'h202020786f7269 :
|
||||
(F_op_bne)? 56'h20202020626e65 :
|
||||
(F_op_cmpeqi)? 56'h20636d70657169 :
|
||||
(F_op_ldbuio)? 56'h206c646275696f :
|
||||
(F_op_muli)? 56'h2020206d756c69 :
|
||||
(F_op_stbio)? 56'h2020737462696f :
|
||||
(F_op_beq)? 56'h20202020626571 :
|
||||
(F_op_ldbio)? 56'h20206c6462696f :
|
||||
(F_op_cmpgeui)? 56'h636d7067657569 :
|
||||
(F_op_ldhuio)? 56'h206c646875696f :
|
||||
(F_op_andhi)? 56'h2020616e646869 :
|
||||
(F_op_sthio)? 56'h2020737468696f :
|
||||
(F_op_bgeu)? 56'h20202062676575 :
|
||||
(F_op_ldhio)? 56'h20206c6468696f :
|
||||
(F_op_cmpltui)? 56'h636d706c747569 :
|
||||
(F_op_custom)? 56'h20637573746f6d :
|
||||
(F_op_initd)? 56'h2020696e697464 :
|
||||
(F_op_orhi)? 56'h2020206f726869 :
|
||||
(F_op_stwio)? 56'h2020737477696f :
|
||||
(F_op_bltu)? 56'h202020626c7475 :
|
||||
(F_op_ldwio)? 56'h20206c6477696f :
|
||||
(F_op_flushd)? 56'h20666c75736864 :
|
||||
(F_op_xorhi)? 56'h2020786f726869 :
|
||||
(F_op_eret)? 56'h20202065726574 :
|
||||
(F_op_roli)? 56'h202020726f6c69 :
|
||||
(F_op_rol)? 56'h20202020726f6c :
|
||||
(F_op_flushp)? 56'h20666c75736870 :
|
||||
(F_op_ret)? 56'h20202020726574 :
|
||||
(F_op_nor)? 56'h202020206e6f72 :
|
||||
(F_op_mulxuu)? 56'h206d756c787575 :
|
||||
(F_op_cmpge)? 56'h2020636d706765 :
|
||||
(F_op_bret)? 56'h20202062726574 :
|
||||
(F_op_ror)? 56'h20202020726f72 :
|
||||
(F_op_flushi)? 56'h20666c75736869 :
|
||||
(F_op_jmp)? 56'h202020206a6d70 :
|
||||
(F_op_and)? 56'h20202020616e64 :
|
||||
(F_op_cmplt)? 56'h2020636d706c74 :
|
||||
(F_op_slli)? 56'h202020736c6c69 :
|
||||
(F_op_sll)? 56'h20202020736c6c :
|
||||
(F_op_or)? 56'h20202020206f72 :
|
||||
(F_op_mulxsu)? 56'h206d756c787375 :
|
||||
(F_op_cmpne)? 56'h2020636d706e65 :
|
||||
(F_op_srli)? 56'h20202073726c69 :
|
||||
(F_op_srl)? 56'h2020202073726c :
|
||||
(F_op_nextpc)? 56'h206e6578747063 :
|
||||
(F_op_callr)? 56'h202063616c6c72 :
|
||||
(F_op_xor)? 56'h20202020786f72 :
|
||||
(F_op_mulxss)? 56'h206d756c787373 :
|
||||
(F_op_cmpeq)? 56'h2020636d706571 :
|
||||
(F_op_divu)? 56'h20202064697675 :
|
||||
(F_op_div)? 56'h20202020646976 :
|
||||
(F_op_rdctl)? 56'h2020726463746c :
|
||||
(F_op_mul)? 56'h202020206d756c :
|
||||
(F_op_cmpgeu)? 56'h20636d70676575 :
|
||||
(F_op_initi)? 56'h2020696e697469 :
|
||||
(F_op_trap)? 56'h20202074726170 :
|
||||
(F_op_wrctl)? 56'h2020777263746c :
|
||||
(F_op_cmpltu)? 56'h20636d706c7475 :
|
||||
(F_op_add)? 56'h20202020616464 :
|
||||
(F_op_break)? 56'h2020627265616b :
|
||||
(F_op_hbreak)? 56'h2068627265616b :
|
||||
(F_op_sync)? 56'h20202073796e63 :
|
||||
(F_op_sub)? 56'h20202020737562 :
|
||||
(F_op_srai)? 56'h20202073726169 :
|
||||
(F_op_sra)? 56'h20202020737261 :
|
||||
(F_op_intr)? 56'h202020696e7472 :
|
||||
56'h20202020424144;
|
||||
assign F_inst = (F_op_call)? 72'h202020202063616c6c :
|
||||
(F_op_jmpi)? 72'h20202020206a6d7069 :
|
||||
(F_op_ldbu)? 72'h20202020206c646275 :
|
||||
(F_op_addi)? 72'h202020202061646469 :
|
||||
(F_op_stb)? 72'h202020202020737462 :
|
||||
(F_op_br)? 72'h202020202020206272 :
|
||||
(F_op_ldb)? 72'h2020202020206c6462 :
|
||||
(F_op_cmpgei)? 72'h202020636d70676569 :
|
||||
(F_op_ldhu)? 72'h20202020206c646875 :
|
||||
(F_op_andi)? 72'h2020202020616e6469 :
|
||||
(F_op_sth)? 72'h202020202020737468 :
|
||||
(F_op_bge)? 72'h202020202020626765 :
|
||||
(F_op_ldh)? 72'h2020202020206c6468 :
|
||||
(F_op_cmplti)? 72'h202020636d706c7469 :
|
||||
(F_op_initda)? 72'h202020696e69746461 :
|
||||
(F_op_ori)? 72'h2020202020206f7269 :
|
||||
(F_op_stw)? 72'h202020202020737477 :
|
||||
(F_op_blt)? 72'h202020202020626c74 :
|
||||
(F_op_ldw)? 72'h2020202020206c6477 :
|
||||
(F_op_cmpnei)? 72'h202020636d706e6569 :
|
||||
(F_op_flushda)? 72'h2020666c7573686461 :
|
||||
(F_op_xori)? 72'h2020202020786f7269 :
|
||||
(F_op_bne)? 72'h202020202020626e65 :
|
||||
(F_op_cmpeqi)? 72'h202020636d70657169 :
|
||||
(F_op_ldbuio)? 72'h2020206c646275696f :
|
||||
(F_op_muli)? 72'h20202020206d756c69 :
|
||||
(F_op_stbio)? 72'h20202020737462696f :
|
||||
(F_op_beq)? 72'h202020202020626571 :
|
||||
(F_op_ldbio)? 72'h202020206c6462696f :
|
||||
(F_op_cmpgeui)? 72'h2020636d7067657569 :
|
||||
(F_op_ldhuio)? 72'h2020206c646875696f :
|
||||
(F_op_andhi)? 72'h20202020616e646869 :
|
||||
(F_op_sthio)? 72'h20202020737468696f :
|
||||
(F_op_bgeu)? 72'h202020202062676575 :
|
||||
(F_op_ldhio)? 72'h202020206c6468696f :
|
||||
(F_op_cmpltui)? 72'h2020636d706c747569 :
|
||||
(F_op_custom)? 72'h202020637573746f6d :
|
||||
(F_op_initd)? 72'h20202020696e697464 :
|
||||
(F_op_orhi)? 72'h20202020206f726869 :
|
||||
(F_op_stwio)? 72'h20202020737477696f :
|
||||
(F_op_bltu)? 72'h2020202020626c7475 :
|
||||
(F_op_ldwio)? 72'h202020206c6477696f :
|
||||
(F_op_flushd)? 72'h202020666c75736864 :
|
||||
(F_op_xorhi)? 72'h20202020786f726869 :
|
||||
(F_op_eret)? 72'h202020202065726574 :
|
||||
(F_op_roli)? 72'h2020202020726f6c69 :
|
||||
(F_op_rol)? 72'h202020202020726f6c :
|
||||
(F_op_flushp)? 72'h202020666c75736870 :
|
||||
(F_op_ret)? 72'h202020202020726574 :
|
||||
(F_op_nor)? 72'h2020202020206e6f72 :
|
||||
(F_op_mulxuu)? 72'h2020206d756c787575 :
|
||||
(F_op_cmpge)? 72'h20202020636d706765 :
|
||||
(F_op_bret)? 72'h202020202062726574 :
|
||||
(F_op_ror)? 72'h202020202020726f72 :
|
||||
(F_op_flushi)? 72'h202020666c75736869 :
|
||||
(F_op_jmp)? 72'h2020202020206a6d70 :
|
||||
(F_op_and)? 72'h202020202020616e64 :
|
||||
(F_op_cmplt)? 72'h20202020636d706c74 :
|
||||
(F_op_slli)? 72'h2020202020736c6c69 :
|
||||
(F_op_sll)? 72'h202020202020736c6c :
|
||||
(F_op_or)? 72'h202020202020206f72 :
|
||||
(F_op_mulxsu)? 72'h2020206d756c787375 :
|
||||
(F_op_cmpne)? 72'h20202020636d706e65 :
|
||||
(F_op_srli)? 72'h202020202073726c69 :
|
||||
(F_op_srl)? 72'h20202020202073726c :
|
||||
(F_op_nextpc)? 72'h2020206e6578747063 :
|
||||
(F_op_callr)? 72'h2020202063616c6c72 :
|
||||
(F_op_xor)? 72'h202020202020786f72 :
|
||||
(F_op_mulxss)? 72'h2020206d756c787373 :
|
||||
(F_op_cmpeq)? 72'h20202020636d706571 :
|
||||
(F_op_divu)? 72'h202020202064697675 :
|
||||
(F_op_div)? 72'h202020202020646976 :
|
||||
(F_op_rdctl)? 72'h20202020726463746c :
|
||||
(F_op_mul)? 72'h2020202020206d756c :
|
||||
(F_op_cmpgeu)? 72'h202020636d70676575 :
|
||||
(F_op_initi)? 72'h20202020696e697469 :
|
||||
(F_op_trap)? 72'h202020202074726170 :
|
||||
(F_op_wrctl)? 72'h20202020777263746c :
|
||||
(F_op_cmpltu)? 72'h202020636d706c7475 :
|
||||
(F_op_add)? 72'h202020202020616464 :
|
||||
(F_op_break)? 72'h20202020627265616b :
|
||||
(F_op_hbreak)? 72'h20202068627265616b :
|
||||
(F_op_sync)? 72'h202020202073796e63 :
|
||||
(F_op_sub)? 72'h202020202020737562 :
|
||||
(F_op_srai)? 72'h202020202073726169 :
|
||||
(F_op_sra)? 72'h202020202020737261 :
|
||||
(F_op_intr)? 72'h2020202020696e7472 :
|
||||
(F_op_countones)? 72'h636f756e746f6e6573 :
|
||||
72'h202020202020424144;
|
||||
|
||||
assign D_inst = (D_op_call)? 56'h20202063616c6c :
|
||||
(D_op_jmpi)? 56'h2020206a6d7069 :
|
||||
(D_op_ldbu)? 56'h2020206c646275 :
|
||||
(D_op_addi)? 56'h20202061646469 :
|
||||
(D_op_stb)? 56'h20202020737462 :
|
||||
(D_op_br)? 56'h20202020206272 :
|
||||
(D_op_ldb)? 56'h202020206c6462 :
|
||||
(D_op_cmpgei)? 56'h20636d70676569 :
|
||||
(D_op_ldhu)? 56'h2020206c646875 :
|
||||
(D_op_andi)? 56'h202020616e6469 :
|
||||
(D_op_sth)? 56'h20202020737468 :
|
||||
(D_op_bge)? 56'h20202020626765 :
|
||||
(D_op_ldh)? 56'h202020206c6468 :
|
||||
(D_op_cmplti)? 56'h20636d706c7469 :
|
||||
(D_op_initda)? 56'h20696e69746461 :
|
||||
(D_op_ori)? 56'h202020206f7269 :
|
||||
(D_op_stw)? 56'h20202020737477 :
|
||||
(D_op_blt)? 56'h20202020626c74 :
|
||||
(D_op_ldw)? 56'h202020206c6477 :
|
||||
(D_op_cmpnei)? 56'h20636d706e6569 :
|
||||
(D_op_flushda)? 56'h666c7573686461 :
|
||||
(D_op_xori)? 56'h202020786f7269 :
|
||||
(D_op_bne)? 56'h20202020626e65 :
|
||||
(D_op_cmpeqi)? 56'h20636d70657169 :
|
||||
(D_op_ldbuio)? 56'h206c646275696f :
|
||||
(D_op_muli)? 56'h2020206d756c69 :
|
||||
(D_op_stbio)? 56'h2020737462696f :
|
||||
(D_op_beq)? 56'h20202020626571 :
|
||||
(D_op_ldbio)? 56'h20206c6462696f :
|
||||
(D_op_cmpgeui)? 56'h636d7067657569 :
|
||||
(D_op_ldhuio)? 56'h206c646875696f :
|
||||
(D_op_andhi)? 56'h2020616e646869 :
|
||||
(D_op_sthio)? 56'h2020737468696f :
|
||||
(D_op_bgeu)? 56'h20202062676575 :
|
||||
(D_op_ldhio)? 56'h20206c6468696f :
|
||||
(D_op_cmpltui)? 56'h636d706c747569 :
|
||||
(D_op_custom)? 56'h20637573746f6d :
|
||||
(D_op_initd)? 56'h2020696e697464 :
|
||||
(D_op_orhi)? 56'h2020206f726869 :
|
||||
(D_op_stwio)? 56'h2020737477696f :
|
||||
(D_op_bltu)? 56'h202020626c7475 :
|
||||
(D_op_ldwio)? 56'h20206c6477696f :
|
||||
(D_op_flushd)? 56'h20666c75736864 :
|
||||
(D_op_xorhi)? 56'h2020786f726869 :
|
||||
(D_op_eret)? 56'h20202065726574 :
|
||||
(D_op_roli)? 56'h202020726f6c69 :
|
||||
(D_op_rol)? 56'h20202020726f6c :
|
||||
(D_op_flushp)? 56'h20666c75736870 :
|
||||
(D_op_ret)? 56'h20202020726574 :
|
||||
(D_op_nor)? 56'h202020206e6f72 :
|
||||
(D_op_mulxuu)? 56'h206d756c787575 :
|
||||
(D_op_cmpge)? 56'h2020636d706765 :
|
||||
(D_op_bret)? 56'h20202062726574 :
|
||||
(D_op_ror)? 56'h20202020726f72 :
|
||||
(D_op_flushi)? 56'h20666c75736869 :
|
||||
(D_op_jmp)? 56'h202020206a6d70 :
|
||||
(D_op_and)? 56'h20202020616e64 :
|
||||
(D_op_cmplt)? 56'h2020636d706c74 :
|
||||
(D_op_slli)? 56'h202020736c6c69 :
|
||||
(D_op_sll)? 56'h20202020736c6c :
|
||||
(D_op_or)? 56'h20202020206f72 :
|
||||
(D_op_mulxsu)? 56'h206d756c787375 :
|
||||
(D_op_cmpne)? 56'h2020636d706e65 :
|
||||
(D_op_srli)? 56'h20202073726c69 :
|
||||
(D_op_srl)? 56'h2020202073726c :
|
||||
(D_op_nextpc)? 56'h206e6578747063 :
|
||||
(D_op_callr)? 56'h202063616c6c72 :
|
||||
(D_op_xor)? 56'h20202020786f72 :
|
||||
(D_op_mulxss)? 56'h206d756c787373 :
|
||||
(D_op_cmpeq)? 56'h2020636d706571 :
|
||||
(D_op_divu)? 56'h20202064697675 :
|
||||
(D_op_div)? 56'h20202020646976 :
|
||||
(D_op_rdctl)? 56'h2020726463746c :
|
||||
(D_op_mul)? 56'h202020206d756c :
|
||||
(D_op_cmpgeu)? 56'h20636d70676575 :
|
||||
(D_op_initi)? 56'h2020696e697469 :
|
||||
(D_op_trap)? 56'h20202074726170 :
|
||||
(D_op_wrctl)? 56'h2020777263746c :
|
||||
(D_op_cmpltu)? 56'h20636d706c7475 :
|
||||
(D_op_add)? 56'h20202020616464 :
|
||||
(D_op_break)? 56'h2020627265616b :
|
||||
(D_op_hbreak)? 56'h2068627265616b :
|
||||
(D_op_sync)? 56'h20202073796e63 :
|
||||
(D_op_sub)? 56'h20202020737562 :
|
||||
(D_op_srai)? 56'h20202073726169 :
|
||||
(D_op_sra)? 56'h20202020737261 :
|
||||
(D_op_intr)? 56'h202020696e7472 :
|
||||
56'h20202020424144;
|
||||
assign D_inst = (D_op_call)? 72'h202020202063616c6c :
|
||||
(D_op_jmpi)? 72'h20202020206a6d7069 :
|
||||
(D_op_ldbu)? 72'h20202020206c646275 :
|
||||
(D_op_addi)? 72'h202020202061646469 :
|
||||
(D_op_stb)? 72'h202020202020737462 :
|
||||
(D_op_br)? 72'h202020202020206272 :
|
||||
(D_op_ldb)? 72'h2020202020206c6462 :
|
||||
(D_op_cmpgei)? 72'h202020636d70676569 :
|
||||
(D_op_ldhu)? 72'h20202020206c646875 :
|
||||
(D_op_andi)? 72'h2020202020616e6469 :
|
||||
(D_op_sth)? 72'h202020202020737468 :
|
||||
(D_op_bge)? 72'h202020202020626765 :
|
||||
(D_op_ldh)? 72'h2020202020206c6468 :
|
||||
(D_op_cmplti)? 72'h202020636d706c7469 :
|
||||
(D_op_initda)? 72'h202020696e69746461 :
|
||||
(D_op_ori)? 72'h2020202020206f7269 :
|
||||
(D_op_stw)? 72'h202020202020737477 :
|
||||
(D_op_blt)? 72'h202020202020626c74 :
|
||||
(D_op_ldw)? 72'h2020202020206c6477 :
|
||||
(D_op_cmpnei)? 72'h202020636d706e6569 :
|
||||
(D_op_flushda)? 72'h2020666c7573686461 :
|
||||
(D_op_xori)? 72'h2020202020786f7269 :
|
||||
(D_op_bne)? 72'h202020202020626e65 :
|
||||
(D_op_cmpeqi)? 72'h202020636d70657169 :
|
||||
(D_op_ldbuio)? 72'h2020206c646275696f :
|
||||
(D_op_muli)? 72'h20202020206d756c69 :
|
||||
(D_op_stbio)? 72'h20202020737462696f :
|
||||
(D_op_beq)? 72'h202020202020626571 :
|
||||
(D_op_ldbio)? 72'h202020206c6462696f :
|
||||
(D_op_cmpgeui)? 72'h2020636d7067657569 :
|
||||
(D_op_ldhuio)? 72'h2020206c646875696f :
|
||||
(D_op_andhi)? 72'h20202020616e646869 :
|
||||
(D_op_sthio)? 72'h20202020737468696f :
|
||||
(D_op_bgeu)? 72'h202020202062676575 :
|
||||
(D_op_ldhio)? 72'h202020206c6468696f :
|
||||
(D_op_cmpltui)? 72'h2020636d706c747569 :
|
||||
(D_op_custom)? 72'h202020637573746f6d :
|
||||
(D_op_initd)? 72'h20202020696e697464 :
|
||||
(D_op_orhi)? 72'h20202020206f726869 :
|
||||
(D_op_stwio)? 72'h20202020737477696f :
|
||||
(D_op_bltu)? 72'h2020202020626c7475 :
|
||||
(D_op_ldwio)? 72'h202020206c6477696f :
|
||||
(D_op_flushd)? 72'h202020666c75736864 :
|
||||
(D_op_xorhi)? 72'h20202020786f726869 :
|
||||
(D_op_eret)? 72'h202020202065726574 :
|
||||
(D_op_roli)? 72'h2020202020726f6c69 :
|
||||
(D_op_rol)? 72'h202020202020726f6c :
|
||||
(D_op_flushp)? 72'h202020666c75736870 :
|
||||
(D_op_ret)? 72'h202020202020726574 :
|
||||
(D_op_nor)? 72'h2020202020206e6f72 :
|
||||
(D_op_mulxuu)? 72'h2020206d756c787575 :
|
||||
(D_op_cmpge)? 72'h20202020636d706765 :
|
||||
(D_op_bret)? 72'h202020202062726574 :
|
||||
(D_op_ror)? 72'h202020202020726f72 :
|
||||
(D_op_flushi)? 72'h202020666c75736869 :
|
||||
(D_op_jmp)? 72'h2020202020206a6d70 :
|
||||
(D_op_and)? 72'h202020202020616e64 :
|
||||
(D_op_cmplt)? 72'h20202020636d706c74 :
|
||||
(D_op_slli)? 72'h2020202020736c6c69 :
|
||||
(D_op_sll)? 72'h202020202020736c6c :
|
||||
(D_op_or)? 72'h202020202020206f72 :
|
||||
(D_op_mulxsu)? 72'h2020206d756c787375 :
|
||||
(D_op_cmpne)? 72'h20202020636d706e65 :
|
||||
(D_op_srli)? 72'h202020202073726c69 :
|
||||
(D_op_srl)? 72'h20202020202073726c :
|
||||
(D_op_nextpc)? 72'h2020206e6578747063 :
|
||||
(D_op_callr)? 72'h2020202063616c6c72 :
|
||||
(D_op_xor)? 72'h202020202020786f72 :
|
||||
(D_op_mulxss)? 72'h2020206d756c787373 :
|
||||
(D_op_cmpeq)? 72'h20202020636d706571 :
|
||||
(D_op_divu)? 72'h202020202064697675 :
|
||||
(D_op_div)? 72'h202020202020646976 :
|
||||
(D_op_rdctl)? 72'h20202020726463746c :
|
||||
(D_op_mul)? 72'h2020202020206d756c :
|
||||
(D_op_cmpgeu)? 72'h202020636d70676575 :
|
||||
(D_op_initi)? 72'h20202020696e697469 :
|
||||
(D_op_trap)? 72'h202020202074726170 :
|
||||
(D_op_wrctl)? 72'h20202020777263746c :
|
||||
(D_op_cmpltu)? 72'h202020636d706c7475 :
|
||||
(D_op_add)? 72'h202020202020616464 :
|
||||
(D_op_break)? 72'h20202020627265616b :
|
||||
(D_op_hbreak)? 72'h20202068627265616b :
|
||||
(D_op_sync)? 72'h202020202073796e63 :
|
||||
(D_op_sub)? 72'h202020202020737562 :
|
||||
(D_op_srai)? 72'h202020202073726169 :
|
||||
(D_op_sra)? 72'h202020202020737261 :
|
||||
(D_op_intr)? 72'h2020202020696e7472 :
|
||||
(D_op_countones)? 72'h636f756e746f6e6573 :
|
||||
72'h202020202020424144;
|
||||
|
||||
assign F_vinst = F_valid ? F_inst : {9{8'h2d}};
|
||||
assign D_vinst = D_valid ? D_inst : {9{8'h2d}};
|
||||
|
|
|
|||
|
|
@ -110,6 +110,7 @@ wire D_op_cmpltu;
|
|||
wire D_op_cmpltui;
|
||||
wire D_op_cmpne;
|
||||
wire D_op_cmpnei;
|
||||
wire D_op_countones;
|
||||
wire D_op_crst;
|
||||
wire D_op_custom;
|
||||
wire D_op_div;
|
||||
|
|
@ -370,6 +371,7 @@ wire test_has_ended;
|
|||
assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
|
||||
assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
|
||||
assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
|
||||
assign D_op_countones = D_op_custom & 1'b1;
|
||||
assign D_is_opx_inst = D_iw_op == 58;
|
||||
assign test_has_ended = 1'b0;
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -29,8 +29,8 @@
|
|||
// Generation parameters:
|
||||
// output_name: niosII_mm_interconnect_0_cmd_demux
|
||||
// ST_DATA_W: 94
|
||||
// ST_CHANNEL_W: 7
|
||||
// NUM_OUTPUTS: 6
|
||||
// ST_CHANNEL_W: 8
|
||||
// NUM_OUTPUTS: 7
|
||||
// VALID_WIDTH: 1
|
||||
// ------------------------------------------
|
||||
|
||||
|
|
@ -47,7 +47,7 @@ module niosII_mm_interconnect_0_cmd_demux
|
|||
// -------------------
|
||||
input [1-1 : 0] sink_valid,
|
||||
input [94-1 : 0] sink_data, // ST_DATA_W=94
|
||||
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
|
||||
input [8-1 : 0] sink_channel, // ST_CHANNEL_W=8
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
output sink_ready,
|
||||
|
|
@ -57,46 +57,53 @@ module niosII_mm_interconnect_0_cmd_demux
|
|||
// -------------------
|
||||
output reg src0_valid,
|
||||
output reg [94-1 : 0] src0_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
|
||||
output reg [8-1 : 0] src0_channel, // ST_CHANNEL_W=8
|
||||
output reg src0_startofpacket,
|
||||
output reg src0_endofpacket,
|
||||
input src0_ready,
|
||||
|
||||
output reg src1_valid,
|
||||
output reg [94-1 : 0] src1_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
|
||||
output reg [8-1 : 0] src1_channel, // ST_CHANNEL_W=8
|
||||
output reg src1_startofpacket,
|
||||
output reg src1_endofpacket,
|
||||
input src1_ready,
|
||||
|
||||
output reg src2_valid,
|
||||
output reg [94-1 : 0] src2_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src2_channel, // ST_CHANNEL_W=7
|
||||
output reg [8-1 : 0] src2_channel, // ST_CHANNEL_W=8
|
||||
output reg src2_startofpacket,
|
||||
output reg src2_endofpacket,
|
||||
input src2_ready,
|
||||
|
||||
output reg src3_valid,
|
||||
output reg [94-1 : 0] src3_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src3_channel, // ST_CHANNEL_W=7
|
||||
output reg [8-1 : 0] src3_channel, // ST_CHANNEL_W=8
|
||||
output reg src3_startofpacket,
|
||||
output reg src3_endofpacket,
|
||||
input src3_ready,
|
||||
|
||||
output reg src4_valid,
|
||||
output reg [94-1 : 0] src4_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src4_channel, // ST_CHANNEL_W=7
|
||||
output reg [8-1 : 0] src4_channel, // ST_CHANNEL_W=8
|
||||
output reg src4_startofpacket,
|
||||
output reg src4_endofpacket,
|
||||
input src4_ready,
|
||||
|
||||
output reg src5_valid,
|
||||
output reg [94-1 : 0] src5_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src5_channel, // ST_CHANNEL_W=7
|
||||
output reg [8-1 : 0] src5_channel, // ST_CHANNEL_W=8
|
||||
output reg src5_startofpacket,
|
||||
output reg src5_endofpacket,
|
||||
input src5_ready,
|
||||
|
||||
output reg src6_valid,
|
||||
output reg [94-1 : 0] src6_data, // ST_DATA_W=94
|
||||
output reg [8-1 : 0] src6_channel, // ST_CHANNEL_W=8
|
||||
output reg src6_startofpacket,
|
||||
output reg src6_endofpacket,
|
||||
input src6_ready,
|
||||
|
||||
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
|
|
@ -108,7 +115,7 @@ module niosII_mm_interconnect_0_cmd_demux
|
|||
|
||||
);
|
||||
|
||||
localparam NUM_OUTPUTS = 6;
|
||||
localparam NUM_OUTPUTS = 7;
|
||||
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
|
||||
|
||||
// -------------------
|
||||
|
|
@ -157,6 +164,13 @@ module niosII_mm_interconnect_0_cmd_demux
|
|||
|
||||
src5_valid = sink_channel[5] && sink_valid;
|
||||
|
||||
src6_data = sink_data;
|
||||
src6_startofpacket = sink_startofpacket;
|
||||
src6_endofpacket = sink_endofpacket;
|
||||
src6_channel = sink_channel >> NUM_OUTPUTS;
|
||||
|
||||
src6_valid = sink_channel[6] && sink_valid;
|
||||
|
||||
end
|
||||
|
||||
// -------------------
|
||||
|
|
@ -168,6 +182,7 @@ module niosII_mm_interconnect_0_cmd_demux
|
|||
assign ready_vector[3] = src3_ready;
|
||||
assign ready_vector[4] = src4_ready;
|
||||
assign ready_vector[5] = src5_ready;
|
||||
assign ready_vector[6] = src6_ready;
|
||||
|
||||
assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@
|
|||
// Generation parameters:
|
||||
// output_name: niosII_mm_interconnect_0_cmd_demux_001
|
||||
// ST_DATA_W: 94
|
||||
// ST_CHANNEL_W: 7
|
||||
// ST_CHANNEL_W: 8
|
||||
// NUM_OUTPUTS: 2
|
||||
// VALID_WIDTH: 1
|
||||
// ------------------------------------------
|
||||
|
|
@ -47,7 +47,7 @@ module niosII_mm_interconnect_0_cmd_demux_001
|
|||
// -------------------
|
||||
input [1-1 : 0] sink_valid,
|
||||
input [94-1 : 0] sink_data, // ST_DATA_W=94
|
||||
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
|
||||
input [8-1 : 0] sink_channel, // ST_CHANNEL_W=8
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
output sink_ready,
|
||||
|
|
@ -57,14 +57,14 @@ module niosII_mm_interconnect_0_cmd_demux_001
|
|||
// -------------------
|
||||
output reg src0_valid,
|
||||
output reg [94-1 : 0] src0_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
|
||||
output reg [8-1 : 0] src0_channel, // ST_CHANNEL_W=8
|
||||
output reg src0_startofpacket,
|
||||
output reg src0_endofpacket,
|
||||
input src0_ready,
|
||||
|
||||
output reg src1_valid,
|
||||
output reg [94-1 : 0] src1_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
|
||||
output reg [8-1 : 0] src1_channel, // ST_CHANNEL_W=8
|
||||
output reg src1_startofpacket,
|
||||
output reg src1_endofpacket,
|
||||
input src1_ready,
|
||||
|
|
@ -109,7 +109,7 @@ module niosII_mm_interconnect_0_cmd_demux_001
|
|||
assign ready_vector[0] = src0_ready;
|
||||
assign ready_vector[1] = src1_ready;
|
||||
|
||||
assign sink_ready = |(sink_channel & {{5{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
|
||||
assign sink_ready = |(sink_channel & {{6{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
// PIPELINE_ARB: 1
|
||||
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
|
||||
// ST_DATA_W: 94
|
||||
// ST_CHANNEL_W: 7
|
||||
// ST_CHANNEL_W: 8
|
||||
// ------------------------------------------
|
||||
|
||||
module niosII_mm_interconnect_0_cmd_mux
|
||||
|
|
@ -55,7 +55,7 @@ module niosII_mm_interconnect_0_cmd_mux
|
|||
// ----------------------
|
||||
input sink0_valid,
|
||||
input [94-1 : 0] sink0_data,
|
||||
input [7-1: 0] sink0_channel,
|
||||
input [8-1: 0] sink0_channel,
|
||||
input sink0_startofpacket,
|
||||
input sink0_endofpacket,
|
||||
output sink0_ready,
|
||||
|
|
@ -66,7 +66,7 @@ module niosII_mm_interconnect_0_cmd_mux
|
|||
// ----------------------
|
||||
output src_valid,
|
||||
output [94-1 : 0] src_data,
|
||||
output [7-1 : 0] src_channel,
|
||||
output [8-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready,
|
||||
|
|
@ -77,12 +77,12 @@ module niosII_mm_interconnect_0_cmd_mux
|
|||
input clk,
|
||||
input reset
|
||||
);
|
||||
localparam PAYLOAD_W = 94 + 7 + 2;
|
||||
localparam PAYLOAD_W = 94 + 8 + 2;
|
||||
localparam NUM_INPUTS = 1;
|
||||
localparam SHARE_COUNTER_W = 1;
|
||||
localparam PIPELINE_ARB = 1;
|
||||
localparam ST_DATA_W = 94;
|
||||
localparam ST_CHANNEL_W = 7;
|
||||
localparam ST_CHANNEL_W = 8;
|
||||
localparam PKT_TRANS_LOCK = 58;
|
||||
|
||||
assign src_valid = sink0_valid;
|
||||
|
|
|
|||
|
|
@ -44,15 +44,15 @@
|
|||
|
||||
module niosII_mm_interconnect_0_router_default_decode
|
||||
#(
|
||||
parameter DEFAULT_CHANNEL = 5,
|
||||
parameter DEFAULT_CHANNEL = 6,
|
||||
DEFAULT_WR_CHANNEL = -1,
|
||||
DEFAULT_RD_CHANNEL = -1,
|
||||
DEFAULT_DESTID = 3
|
||||
)
|
||||
(output [80 - 78 : 0] default_destination_id,
|
||||
output [7-1 : 0] default_wr_channel,
|
||||
output [7-1 : 0] default_rd_channel,
|
||||
output [7-1 : 0] default_src_channel
|
||||
output [8-1 : 0] default_wr_channel,
|
||||
output [8-1 : 0] default_rd_channel,
|
||||
output [8-1 : 0] default_src_channel
|
||||
);
|
||||
|
||||
assign default_destination_id =
|
||||
|
|
@ -63,7 +63,7 @@ module niosII_mm_interconnect_0_router_default_decode
|
|||
assign default_src_channel = '0;
|
||||
end
|
||||
else begin : default_channel_assignment
|
||||
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
|
||||
assign default_src_channel = 8'b1 << DEFAULT_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_default_decode
|
|||
assign default_rd_channel = '0;
|
||||
end
|
||||
else begin : default_rw_channel_assignment
|
||||
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
|
||||
assign default_wr_channel = 8'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 8'b1 << DEFAULT_RD_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
@ -103,7 +103,7 @@ module niosII_mm_interconnect_0_router
|
|||
// -------------------
|
||||
output src_valid,
|
||||
output reg [94-1 : 0] src_data,
|
||||
output reg [7-1 : 0] src_channel,
|
||||
output reg [8-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready
|
||||
|
|
@ -119,7 +119,7 @@ module niosII_mm_interconnect_0_router
|
|||
localparam PKT_PROTECTION_H = 84;
|
||||
localparam PKT_PROTECTION_L = 82;
|
||||
localparam ST_DATA_W = 94;
|
||||
localparam ST_CHANNEL_W = 7;
|
||||
localparam ST_CHANNEL_W = 8;
|
||||
localparam DECODER_TYPE = 0;
|
||||
|
||||
localparam PKT_TRANS_WRITE = 56;
|
||||
|
|
@ -137,15 +137,16 @@ module niosII_mm_interconnect_0_router
|
|||
localparam PAD0 = log2ceil(64'h20000 - 64'h0);
|
||||
localparam PAD1 = log2ceil(64'h21000 - 64'h20800);
|
||||
localparam PAD2 = log2ceil(64'h21040 - 64'h21000);
|
||||
localparam PAD3 = log2ceil(64'h21060 - 64'h21040);
|
||||
localparam PAD4 = log2ceil(64'h21068 - 64'h21060);
|
||||
localparam PAD5 = log2ceil(64'h21070 - 64'h21068);
|
||||
localparam PAD3 = log2ceil(64'h21080 - 64'h21040);
|
||||
localparam PAD4 = log2ceil(64'h210a0 - 64'h21080);
|
||||
localparam PAD5 = log2ceil(64'h210a8 - 64'h210a0);
|
||||
localparam PAD6 = log2ceil(64'h210b0 - 64'h210a8);
|
||||
// -------------------------------------------------------
|
||||
// Work out which address bits are significant based on the
|
||||
// address range of the slaves. If the required width is too
|
||||
// large or too small, we use the address field width instead.
|
||||
// -------------------------------------------------------
|
||||
localparam ADDR_RANGE = 64'h21070;
|
||||
localparam ADDR_RANGE = 64'h210b0;
|
||||
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
|
||||
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
|
||||
(RANGE_ADDR_WIDTH == 0) ?
|
||||
|
|
@ -169,7 +170,7 @@ module niosII_mm_interconnect_0_router
|
|||
assign src_startofpacket = sink_startofpacket;
|
||||
assign src_endofpacket = sink_endofpacket;
|
||||
wire [PKT_DEST_ID_W-1:0] default_destid;
|
||||
wire [7-1 : 0] default_src_channel;
|
||||
wire [8-1 : 0] default_src_channel;
|
||||
|
||||
|
||||
|
||||
|
|
@ -200,37 +201,43 @@ module niosII_mm_interconnect_0_router
|
|||
|
||||
// ( 0x0 .. 0x20000 )
|
||||
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0 ) begin
|
||||
src_channel = 7'b100000;
|
||||
src_channel = 8'b1000000;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
|
||||
end
|
||||
|
||||
// ( 0x20800 .. 0x21000 )
|
||||
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800 ) begin
|
||||
src_channel = 7'b000100;
|
||||
src_channel = 8'b0001000;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
|
||||
end
|
||||
|
||||
// ( 0x21000 .. 0x21040 )
|
||||
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h21000 && write_transaction ) begin
|
||||
src_channel = 7'b001000;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
|
||||
end
|
||||
|
||||
// ( 0x21040 .. 0x21060 )
|
||||
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h21040 ) begin
|
||||
src_channel = 7'b010000;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
|
||||
end
|
||||
|
||||
// ( 0x21060 .. 0x21068 )
|
||||
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h21060 ) begin
|
||||
src_channel = 7'b000010;
|
||||
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h21000 ) begin
|
||||
src_channel = 8'b0000010;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
|
||||
end
|
||||
|
||||
// ( 0x21068 .. 0x21070 )
|
||||
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 18'h21068 ) begin
|
||||
src_channel = 7'b000001;
|
||||
// ( 0x21040 .. 0x21080 )
|
||||
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h21040 && write_transaction ) begin
|
||||
src_channel = 8'b0010000;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
|
||||
end
|
||||
|
||||
// ( 0x21080 .. 0x210a0 )
|
||||
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h21080 ) begin
|
||||
src_channel = 8'b0100000;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
|
||||
end
|
||||
|
||||
// ( 0x210a0 .. 0x210a8 )
|
||||
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 18'h210a0 ) begin
|
||||
src_channel = 8'b0000100;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
|
||||
end
|
||||
|
||||
// ( 0x210a8 .. 0x210b0 )
|
||||
if ( {address[RG:PAD6],{PAD6{1'b0}}} == 18'h210a8 ) begin
|
||||
src_channel = 8'b0000001;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -50,9 +50,9 @@ module niosII_mm_interconnect_0_router_001_default_decode
|
|||
DEFAULT_DESTID = 2
|
||||
)
|
||||
(output [80 - 78 : 0] default_destination_id,
|
||||
output [7-1 : 0] default_wr_channel,
|
||||
output [7-1 : 0] default_rd_channel,
|
||||
output [7-1 : 0] default_src_channel
|
||||
output [8-1 : 0] default_wr_channel,
|
||||
output [8-1 : 0] default_rd_channel,
|
||||
output [8-1 : 0] default_src_channel
|
||||
);
|
||||
|
||||
assign default_destination_id =
|
||||
|
|
@ -63,7 +63,7 @@ module niosII_mm_interconnect_0_router_001_default_decode
|
|||
assign default_src_channel = '0;
|
||||
end
|
||||
else begin : default_channel_assignment
|
||||
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
|
||||
assign default_src_channel = 8'b1 << DEFAULT_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_001_default_decode
|
|||
assign default_rd_channel = '0;
|
||||
end
|
||||
else begin : default_rw_channel_assignment
|
||||
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
|
||||
assign default_wr_channel = 8'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 8'b1 << DEFAULT_RD_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
@ -103,7 +103,7 @@ module niosII_mm_interconnect_0_router_001
|
|||
// -------------------
|
||||
output src_valid,
|
||||
output reg [94-1 : 0] src_data,
|
||||
output reg [7-1 : 0] src_channel,
|
||||
output reg [8-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready
|
||||
|
|
@ -119,7 +119,7 @@ module niosII_mm_interconnect_0_router_001
|
|||
localparam PKT_PROTECTION_H = 84;
|
||||
localparam PKT_PROTECTION_L = 82;
|
||||
localparam ST_DATA_W = 94;
|
||||
localparam ST_CHANNEL_W = 7;
|
||||
localparam ST_CHANNEL_W = 8;
|
||||
localparam DECODER_TYPE = 0;
|
||||
|
||||
localparam PKT_TRANS_WRITE = 56;
|
||||
|
|
@ -165,7 +165,7 @@ module niosII_mm_interconnect_0_router_001
|
|||
assign src_startofpacket = sink_startofpacket;
|
||||
assign src_endofpacket = sink_endofpacket;
|
||||
wire [PKT_DEST_ID_W-1:0] default_destid;
|
||||
wire [7-1 : 0] default_src_channel;
|
||||
wire [8-1 : 0] default_src_channel;
|
||||
|
||||
|
||||
|
||||
|
|
@ -191,13 +191,13 @@ module niosII_mm_interconnect_0_router_001
|
|||
|
||||
// ( 0x0 .. 0x20000 )
|
||||
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0 ) begin
|
||||
src_channel = 7'b10;
|
||||
src_channel = 8'b10;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
|
||||
end
|
||||
|
||||
// ( 0x20800 .. 0x21000 )
|
||||
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800 ) begin
|
||||
src_channel = 7'b01;
|
||||
src_channel = 8'b01;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -50,9 +50,9 @@ module niosII_mm_interconnect_0_router_002_default_decode
|
|||
DEFAULT_DESTID = 0
|
||||
)
|
||||
(output [80 - 78 : 0] default_destination_id,
|
||||
output [7-1 : 0] default_wr_channel,
|
||||
output [7-1 : 0] default_rd_channel,
|
||||
output [7-1 : 0] default_src_channel
|
||||
output [8-1 : 0] default_wr_channel,
|
||||
output [8-1 : 0] default_rd_channel,
|
||||
output [8-1 : 0] default_src_channel
|
||||
);
|
||||
|
||||
assign default_destination_id =
|
||||
|
|
@ -63,7 +63,7 @@ module niosII_mm_interconnect_0_router_002_default_decode
|
|||
assign default_src_channel = '0;
|
||||
end
|
||||
else begin : default_channel_assignment
|
||||
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
|
||||
assign default_src_channel = 8'b1 << DEFAULT_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_002_default_decode
|
|||
assign default_rd_channel = '0;
|
||||
end
|
||||
else begin : default_rw_channel_assignment
|
||||
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
|
||||
assign default_wr_channel = 8'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 8'b1 << DEFAULT_RD_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
@ -103,7 +103,7 @@ module niosII_mm_interconnect_0_router_002
|
|||
// -------------------
|
||||
output src_valid,
|
||||
output reg [94-1 : 0] src_data,
|
||||
output reg [7-1 : 0] src_channel,
|
||||
output reg [8-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready
|
||||
|
|
@ -119,7 +119,7 @@ module niosII_mm_interconnect_0_router_002
|
|||
localparam PKT_PROTECTION_H = 84;
|
||||
localparam PKT_PROTECTION_L = 82;
|
||||
localparam ST_DATA_W = 94;
|
||||
localparam ST_CHANNEL_W = 7;
|
||||
localparam ST_CHANNEL_W = 8;
|
||||
localparam DECODER_TYPE = 1;
|
||||
|
||||
localparam PKT_TRANS_WRITE = 56;
|
||||
|
|
@ -158,7 +158,7 @@ module niosII_mm_interconnect_0_router_002
|
|||
assign src_valid = sink_valid;
|
||||
assign src_startofpacket = sink_startofpacket;
|
||||
assign src_endofpacket = sink_endofpacket;
|
||||
wire [7-1 : 0] default_src_channel;
|
||||
wire [8-1 : 0] default_src_channel;
|
||||
|
||||
|
||||
|
||||
|
|
@ -185,7 +185,7 @@ module niosII_mm_interconnect_0_router_002
|
|||
|
||||
|
||||
if (destid == 0 ) begin
|
||||
src_channel = 7'b1;
|
||||
src_channel = 8'b1;
|
||||
end
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@
|
|||
// Generation parameters:
|
||||
// output_name: niosII_mm_interconnect_0_rsp_demux
|
||||
// ST_DATA_W: 94
|
||||
// ST_CHANNEL_W: 7
|
||||
// ST_CHANNEL_W: 8
|
||||
// NUM_OUTPUTS: 1
|
||||
// VALID_WIDTH: 1
|
||||
// ------------------------------------------
|
||||
|
|
@ -47,7 +47,7 @@ module niosII_mm_interconnect_0_rsp_demux
|
|||
// -------------------
|
||||
input [1-1 : 0] sink_valid,
|
||||
input [94-1 : 0] sink_data, // ST_DATA_W=94
|
||||
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
|
||||
input [8-1 : 0] sink_channel, // ST_CHANNEL_W=8
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
output sink_ready,
|
||||
|
|
@ -57,7 +57,7 @@ module niosII_mm_interconnect_0_rsp_demux
|
|||
// -------------------
|
||||
output reg src0_valid,
|
||||
output reg [94-1 : 0] src0_data, // ST_DATA_W=94
|
||||
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
|
||||
output reg [8-1 : 0] src0_channel, // ST_CHANNEL_W=8
|
||||
output reg src0_startofpacket,
|
||||
output reg src0_endofpacket,
|
||||
input src0_ready,
|
||||
|
|
@ -94,7 +94,7 @@ module niosII_mm_interconnect_0_rsp_demux
|
|||
// -------------------
|
||||
assign ready_vector[0] = src0_ready;
|
||||
|
||||
assign sink_ready = |(sink_channel & {{6{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
|
||||
assign sink_ready = |(sink_channel & {{7{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -39,13 +39,13 @@
|
|||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: niosII_mm_interconnect_0_rsp_mux
|
||||
// NUM_INPUTS: 6
|
||||
// ARBITRATION_SHARES: 1 1 1 1 1 1
|
||||
// NUM_INPUTS: 7
|
||||
// ARBITRATION_SHARES: 1 1 1 1 1 1 1
|
||||
// ARBITRATION_SCHEME "no-arb"
|
||||
// PIPELINE_ARB: 0
|
||||
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
|
||||
// ST_DATA_W: 94
|
||||
// ST_CHANNEL_W: 7
|
||||
// ST_CHANNEL_W: 8
|
||||
// ------------------------------------------
|
||||
|
||||
module niosII_mm_interconnect_0_rsp_mux
|
||||
|
|
@ -55,53 +55,60 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
// ----------------------
|
||||
input sink0_valid,
|
||||
input [94-1 : 0] sink0_data,
|
||||
input [7-1: 0] sink0_channel,
|
||||
input [8-1: 0] sink0_channel,
|
||||
input sink0_startofpacket,
|
||||
input sink0_endofpacket,
|
||||
output sink0_ready,
|
||||
|
||||
input sink1_valid,
|
||||
input [94-1 : 0] sink1_data,
|
||||
input [7-1: 0] sink1_channel,
|
||||
input [8-1: 0] sink1_channel,
|
||||
input sink1_startofpacket,
|
||||
input sink1_endofpacket,
|
||||
output sink1_ready,
|
||||
|
||||
input sink2_valid,
|
||||
input [94-1 : 0] sink2_data,
|
||||
input [7-1: 0] sink2_channel,
|
||||
input [8-1: 0] sink2_channel,
|
||||
input sink2_startofpacket,
|
||||
input sink2_endofpacket,
|
||||
output sink2_ready,
|
||||
|
||||
input sink3_valid,
|
||||
input [94-1 : 0] sink3_data,
|
||||
input [7-1: 0] sink3_channel,
|
||||
input [8-1: 0] sink3_channel,
|
||||
input sink3_startofpacket,
|
||||
input sink3_endofpacket,
|
||||
output sink3_ready,
|
||||
|
||||
input sink4_valid,
|
||||
input [94-1 : 0] sink4_data,
|
||||
input [7-1: 0] sink4_channel,
|
||||
input [8-1: 0] sink4_channel,
|
||||
input sink4_startofpacket,
|
||||
input sink4_endofpacket,
|
||||
output sink4_ready,
|
||||
|
||||
input sink5_valid,
|
||||
input [94-1 : 0] sink5_data,
|
||||
input [7-1: 0] sink5_channel,
|
||||
input [8-1: 0] sink5_channel,
|
||||
input sink5_startofpacket,
|
||||
input sink5_endofpacket,
|
||||
output sink5_ready,
|
||||
|
||||
input sink6_valid,
|
||||
input [94-1 : 0] sink6_data,
|
||||
input [8-1: 0] sink6_channel,
|
||||
input sink6_startofpacket,
|
||||
input sink6_endofpacket,
|
||||
output sink6_ready,
|
||||
|
||||
|
||||
// ----------------------
|
||||
// Source
|
||||
// ----------------------
|
||||
output src_valid,
|
||||
output [94-1 : 0] src_data,
|
||||
output [7-1 : 0] src_channel,
|
||||
output [8-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready,
|
||||
|
|
@ -112,12 +119,12 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
input clk,
|
||||
input reset
|
||||
);
|
||||
localparam PAYLOAD_W = 94 + 7 + 2;
|
||||
localparam NUM_INPUTS = 6;
|
||||
localparam PAYLOAD_W = 94 + 8 + 2;
|
||||
localparam NUM_INPUTS = 7;
|
||||
localparam SHARE_COUNTER_W = 1;
|
||||
localparam PIPELINE_ARB = 0;
|
||||
localparam ST_DATA_W = 94;
|
||||
localparam ST_CHANNEL_W = 7;
|
||||
localparam ST_CHANNEL_W = 8;
|
||||
localparam PKT_TRANS_LOCK = 58;
|
||||
|
||||
// ------------------------------------------
|
||||
|
|
@ -139,6 +146,7 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
wire [PAYLOAD_W - 1 : 0] sink3_payload;
|
||||
wire [PAYLOAD_W - 1 : 0] sink4_payload;
|
||||
wire [PAYLOAD_W - 1 : 0] sink5_payload;
|
||||
wire [PAYLOAD_W - 1 : 0] sink6_payload;
|
||||
|
||||
assign valid[0] = sink0_valid;
|
||||
assign valid[1] = sink1_valid;
|
||||
|
|
@ -146,6 +154,7 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
assign valid[3] = sink3_valid;
|
||||
assign valid[4] = sink4_valid;
|
||||
assign valid[5] = sink5_valid;
|
||||
assign valid[6] = sink6_valid;
|
||||
|
||||
|
||||
// ------------------------------------------
|
||||
|
|
@ -161,6 +170,7 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
lock[3] = sink3_data[58];
|
||||
lock[4] = sink4_data[58];
|
||||
lock[5] = sink5_data[58];
|
||||
lock[6] = sink6_data[58];
|
||||
end
|
||||
|
||||
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
|
||||
|
|
@ -197,12 +207,14 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
// 3 | 1 | 0
|
||||
// 4 | 1 | 0
|
||||
// 5 | 1 | 0
|
||||
// 6 | 1 | 0
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0;
|
||||
|
||||
// ------------------------------------------
|
||||
// Choose the share value corresponding to the grant.
|
||||
|
|
@ -215,7 +227,8 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
|
||||
share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
|
||||
share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
|
||||
share_5 & { SHARE_COUNTER_W {next_grant[5]} };
|
||||
share_5 & { SHARE_COUNTER_W {next_grant[5]} } |
|
||||
share_6 & { SHARE_COUNTER_W {next_grant[6]} };
|
||||
end
|
||||
|
||||
// ------------------------------------------
|
||||
|
|
@ -289,11 +302,14 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
|
||||
wire final_packet_5 = 1'b1;
|
||||
|
||||
wire final_packet_6 = 1'b1;
|
||||
|
||||
|
||||
// ------------------------------------------
|
||||
// Concatenate all final_packet signals (wire or reg) into a handy vector.
|
||||
// ------------------------------------------
|
||||
wire [NUM_INPUTS - 1 : 0] final_packet = {
|
||||
final_packet_6,
|
||||
final_packet_5,
|
||||
final_packet_4,
|
||||
final_packet_3,
|
||||
|
|
@ -389,6 +405,7 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
assign sink3_ready = src_ready && grant[3];
|
||||
assign sink4_ready = src_ready && grant[4];
|
||||
assign sink5_ready = src_ready && grant[5];
|
||||
assign sink6_ready = src_ready && grant[6];
|
||||
|
||||
assign src_valid = |(grant & valid);
|
||||
|
||||
|
|
@ -399,7 +416,8 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
sink2_payload & {PAYLOAD_W {grant[2]} } |
|
||||
sink3_payload & {PAYLOAD_W {grant[3]} } |
|
||||
sink4_payload & {PAYLOAD_W {grant[4]} } |
|
||||
sink5_payload & {PAYLOAD_W {grant[5]} };
|
||||
sink5_payload & {PAYLOAD_W {grant[5]} } |
|
||||
sink6_payload & {PAYLOAD_W {grant[6]} };
|
||||
end
|
||||
|
||||
// ------------------------------------------
|
||||
|
|
@ -418,6 +436,8 @@ module niosII_mm_interconnect_0_rsp_mux
|
|||
sink4_startofpacket,sink4_endofpacket};
|
||||
assign sink5_payload = {sink5_channel,sink5_data,
|
||||
sink5_startofpacket,sink5_endofpacket};
|
||||
assign sink6_payload = {sink6_channel,sink6_data,
|
||||
sink6_startofpacket,sink6_endofpacket};
|
||||
|
||||
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
// PIPELINE_ARB: 0
|
||||
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
|
||||
// ST_DATA_W: 94
|
||||
// ST_CHANNEL_W: 7
|
||||
// ST_CHANNEL_W: 8
|
||||
// ------------------------------------------
|
||||
|
||||
module niosII_mm_interconnect_0_rsp_mux_001
|
||||
|
|
@ -55,14 +55,14 @@ module niosII_mm_interconnect_0_rsp_mux_001
|
|||
// ----------------------
|
||||
input sink0_valid,
|
||||
input [94-1 : 0] sink0_data,
|
||||
input [7-1: 0] sink0_channel,
|
||||
input [8-1: 0] sink0_channel,
|
||||
input sink0_startofpacket,
|
||||
input sink0_endofpacket,
|
||||
output sink0_ready,
|
||||
|
||||
input sink1_valid,
|
||||
input [94-1 : 0] sink1_data,
|
||||
input [7-1: 0] sink1_channel,
|
||||
input [8-1: 0] sink1_channel,
|
||||
input sink1_startofpacket,
|
||||
input sink1_endofpacket,
|
||||
output sink1_ready,
|
||||
|
|
@ -73,7 +73,7 @@ module niosII_mm_interconnect_0_rsp_mux_001
|
|||
// ----------------------
|
||||
output src_valid,
|
||||
output [94-1 : 0] src_data,
|
||||
output [7-1 : 0] src_channel,
|
||||
output [8-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready,
|
||||
|
|
@ -84,12 +84,12 @@ module niosII_mm_interconnect_0_rsp_mux_001
|
|||
input clk,
|
||||
input reset
|
||||
);
|
||||
localparam PAYLOAD_W = 94 + 7 + 2;
|
||||
localparam PAYLOAD_W = 94 + 8 + 2;
|
||||
localparam NUM_INPUTS = 2;
|
||||
localparam SHARE_COUNTER_W = 1;
|
||||
localparam PIPELINE_ARB = 0;
|
||||
localparam ST_DATA_W = 94;
|
||||
localparam ST_CHANNEL_W = 7;
|
||||
localparam ST_CHANNEL_W = 8;
|
||||
localparam PKT_TRANS_LOCK = 58;
|
||||
|
||||
// ------------------------------------------
|
||||
|
|
|
|||
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Reference in New Issue