wip lab4, phase inc+sine
This commit is contained in:
parent
77e2cf25d3
commit
3b13bb1166
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@ -2,6 +2,8 @@
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*.rpt
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*.bak
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.#*
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#*.*#
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.*~
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/db
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/incremental_db
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@ -19,11 +21,15 @@ drivers/
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HAL/
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Part_test/
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.metadata/
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.settings/
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RemoteSystemsTempFiles/
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aldec/
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cadence/
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synopsys/
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db/
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incremental_db/
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*.xml
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/testbenches/*.bak
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/common_uart/*.bak
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WIDTH = 8;
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DEPTH = 256;
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ADDRESS_RADIX = DEC;
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DATA_RADIX = HEX;
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CONTENT BEGIN
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END;
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@ -0,0 +1,5 @@
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set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
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set_global_assignment -name IP_TOOL_VERSION "18.1"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sinelut.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sinelut_bb.v"]
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@ -0,0 +1,159 @@
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// megafunction wizard: %ROM: 1-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: sinelut.v
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// Megafunction Name(s):
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// altsyncram
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
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||||
// ************************************************************
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||||
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//Copyright (C) 2018 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
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||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
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||||
//to the terms and conditions of the Intel Program License
|
||||
//Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
//the Intel FPGA IP License Agreement, or other applicable license
|
||||
//agreement, including, without limitation, that your use is for
|
||||
//the sole purpose of programming logic devices manufactured by
|
||||
//Intel and sold by Intel or its authorized distributors. Please
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||||
//refer to the applicable agreement for further details.
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||||
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module sinelut (
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address,
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clock,
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q);
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input [7:0] address;
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input clock;
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output [7:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [7:0] sub_wire0;
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wire [7:0] q = sub_wire0[7:0];
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altsyncram altsyncram_component (
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.address_a (address),
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.clock0 (clock),
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.q_a (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.address_b (1'b1),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_a ({8{1'b1}}),
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.data_b (1'b1),
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.eccstatus (),
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.q_b (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_a (1'b0),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_a = "NONE",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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altsyncram_component.init_file = "sine256.mif",
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altsyncram_component.intended_device_family = "Cyclone IV E",
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altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 256,
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altsyncram_component.operation_mode = "ROM",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_reg_a = "CLOCK0",
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altsyncram_component.widthad_a = 8,
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altsyncram_component.width_a = 8,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
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// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
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// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: Clken NUMERIC "0"
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// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING "sine256.mif"
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// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
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// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
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// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
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// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
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// Retrieval info: PRIVATE: WidthData NUMERIC "8"
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// Retrieval info: PRIVATE: rden NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: INIT_FILE STRING "sine256.mif"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
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||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
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// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.v TRUE
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||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.inc FALSE
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||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.cmp FALSE
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||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.bsf FALSE
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||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_inst.v FALSE
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||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_bb.v TRUE
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// Retrieval info: LIB_FILE: altera_mf
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|
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@ -0,0 +1,110 @@
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// megafunction wizard: %ROM: 1-PORT%VBB%
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||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
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||||
// MODULE: altsyncram
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||||
|
||||
// ============================================================
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||||
// File Name: sinelut.v
|
||||
// Megafunction Name(s):
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||||
// altsyncram
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||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
//Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Intel Program License
|
||||
//Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
//the Intel FPGA IP License Agreement, or other applicable license
|
||||
//agreement, including, without limitation, that your use is for
|
||||
//the sole purpose of programming logic devices manufactured by
|
||||
//Intel and sold by Intel or its authorized distributors. Please
|
||||
//refer to the applicable agreement for further details.
|
||||
|
||||
module sinelut (
|
||||
address,
|
||||
clock,
|
||||
q);
|
||||
|
||||
input [7:0] address;
|
||||
input clock;
|
||||
output [7:0] q;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri1 clock;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clken NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MIFfilename STRING "sine256.mif"
|
||||
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: INIT_FILE STRING "sine256.mif"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
||||
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
|
||||
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
|
||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_bb.v TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
sinelut sinelut_inst (
|
||||
.address ( address_sig ),
|
||||
.clock ( clock_sig ),
|
||||
.q ( q_sig )
|
||||
);
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
module phacc
|
||||
#(
|
||||
parameter unsigned WIDTH = 14
|
||||
) (
|
||||
input logic [7:0] phinc,
|
||||
input clk,
|
||||
input reset,
|
||||
output [7:0] phase
|
||||
);
|
||||
|
||||
logic [WIDTH - 1 : 0] sum;
|
||||
|
||||
always_ff @(posedge clk, negedge reset) begin
|
||||
if (~reset) begin
|
||||
sum <= 0;
|
||||
end else begin
|
||||
sum <= sum + phinc;
|
||||
end
|
||||
end
|
||||
|
||||
assign phase = sum[WIDTH - 1 : WIDTH - 8];
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
//top-level module
|
||||
module sigdel
|
||||
#(
|
||||
PHACC_WIDTH = 14
|
||||
) (
|
||||
//clock and reset
|
||||
input logic clk, clr_n,
|
||||
//control slave
|
||||
input logic [31:0] wr_data,
|
||||
input logic wr_n,
|
||||
output logic fout
|
||||
);
|
||||
|
||||
phacc phacc_inst (.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
|
||||
defparam phacc_inst.WIDTH = PHACC_WIDTH;
|
||||
|
||||
sinelut sinelut_inst (
|
||||
.address (phase), .clock (clk), .q(sine)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,128 +0,0 @@
|
|||
`timescale 1 ns/1 ns
|
||||
|
||||
module dec_tb();
|
||||
|
||||
// Wires and variables to connect to UUT (unit under test)
|
||||
logic clk, clrn, train;
|
||||
logic r, y, g;
|
||||
logic [1:0] div;
|
||||
logic ctl_wr, ctl_rd;
|
||||
logic ctl_addr;
|
||||
logic [31:0] ctl_wrdata;
|
||||
logic [31:0] ctl_rddata;
|
||||
logic ram_wr;
|
||||
logic [3:0] ram_addr;
|
||||
logic [31:0] ram_wrdata;
|
||||
|
||||
logic [31:0] divisor[3:0] = {
|
||||
{8'd10, 8'd70, 8'd50, 8'd20},
|
||||
{8'd10, 8'd30, 8'd40, 8'd30},
|
||||
{8'd10, 8'd30, 8'd10, 8'd100},
|
||||
{8'd10, 8'd60, 8'd80, 8'd50}
|
||||
};
|
||||
|
||||
// Instantiate UUT
|
||||
dec my_sem(
|
||||
.clk(clk), .clrn(clrn),
|
||||
.ctl_wr(ctl_wr), .ctl_rd(ctl_rd),
|
||||
.ctl_addr(ctl_addr), .ctl_wrdata(ctl_wrdata), .ctl_rddata(ctl_rddata),
|
||||
.ram_wr(ram_wr),
|
||||
.ram_addr(ram_addr), .ram_wrdata(ram_wrdata),
|
||||
.train(train), .red(r), .yellow(y), .green(g)
|
||||
);
|
||||
|
||||
// Clock definition
|
||||
initial begin
|
||||
clk = 0;
|
||||
forever #10 clk = ~clk;
|
||||
end
|
||||
|
||||
// Divisor and train definition
|
||||
initial begin
|
||||
//initial reset
|
||||
clrn = 0;
|
||||
div = 0;
|
||||
train = 0;
|
||||
//take reset off
|
||||
@(negedge clk) clrn = 1;
|
||||
//configure semaphore
|
||||
for (int i=0; i<4; i++) write_ram_transaction(i,divisor[i]); //write divisor RAM
|
||||
write_reg_transaction(1,div); //write initial divisor
|
||||
write_reg_transaction(0,1); //enable semaphore
|
||||
//run trains
|
||||
repeat (4)
|
||||
begin
|
||||
repeat (10) @(posedge clk);
|
||||
train=1;
|
||||
repeat (4) @(posedge clk);
|
||||
train=0;
|
||||
wait ({r,y,g}==3'b001);
|
||||
repeat (10) @(posedge clk);
|
||||
write_reg_transaction(1,div);
|
||||
div=div+1;
|
||||
end
|
||||
//wait a little
|
||||
repeat (10) @(posedge clk);
|
||||
$stop;
|
||||
end
|
||||
|
||||
//Single register write transaction task
|
||||
task write_reg_transaction;
|
||||
//input signals
|
||||
input [1:0] offs;
|
||||
input [31:0] val;
|
||||
//transaction implementation
|
||||
begin
|
||||
@(posedge clk);
|
||||
//assert signals for one clock cycle
|
||||
ctl_wr = 1;
|
||||
ctl_addr = offs;
|
||||
ctl_wrdata = val;
|
||||
@(posedge clk);
|
||||
//deassert signals
|
||||
ctl_wr = 0;
|
||||
ctl_addr = 'bx;
|
||||
ctl_wrdata = 'bx;
|
||||
end
|
||||
endtask
|
||||
|
||||
//Single register read transaction task
|
||||
task read_reg_transaction;
|
||||
//input signals
|
||||
input [1:0] offs;
|
||||
output [31:0] val;
|
||||
//transaction implementation
|
||||
begin
|
||||
@(posedge clk);
|
||||
//assert signals for one clock cycle
|
||||
ctl_rd = 1;
|
||||
ctl_addr = offs;
|
||||
@(posedge clk);
|
||||
val = ctl_rddata;
|
||||
//deassert signals
|
||||
ctl_rd = 0;
|
||||
ctl_addr = 'bx;
|
||||
end
|
||||
endtask
|
||||
|
||||
//RAM write transaction task
|
||||
task write_ram_transaction;
|
||||
//input signals
|
||||
input [1:0] offs;
|
||||
input [31:0] val;
|
||||
//transaction implementation
|
||||
begin
|
||||
@(posedge clk);
|
||||
//assert signals for one clock cycle
|
||||
ram_wr = 1;
|
||||
ram_addr = offs;
|
||||
ram_wrdata = val;
|
||||
@(posedge clk);
|
||||
//deassert signals
|
||||
ram_wr = 0;
|
||||
ram_addr = 'bx;
|
||||
ram_wrdata = 'bx;
|
||||
end
|
||||
endtask
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673520674097 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 12 13:51:13 2023 " "Processing started: Thu Jan 12 13:51:13 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674097 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674098 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
|
||||
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"\[\"; expecting an operand sigdel.sv(14) " "Verilog HDL syntax error at sigdel.sv(14) near text: \"\[\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 14 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
|
||||
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "sigdel sigdel.sv(1) " "Ignored design unit \"sigdel\" at sigdel.sv(1) due to previous errors" { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680483 ""}
|
||||
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "923 " "Peak virtual memory: 923 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Jan 12 13:51:20 2023 " "Processing ended: Thu Jan 12 13:51:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680505 ""}
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -1,5 +0,0 @@
|
|||
<?xml version="1.0" ?>
|
||||
<LOG_ROOT>
|
||||
<PROJECT NAME="sigdel">
|
||||
</PROJECT>
|
||||
</LOG_ROOT>
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -1,3 +0,0 @@
|
|||
Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
|
||||
Version_Index = 486699264
|
||||
Creation_Time = Mon Jan 16 21:47:58 2023
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
|sigdel
|
||||
phinc[0] => Add0.IN14
|
||||
phinc[1] => Add0.IN13
|
||||
phinc[2] => Add0.IN12
|
||||
phinc[3] => Add0.IN11
|
||||
phinc[4] => Add0.IN10
|
||||
phinc[5] => Add0.IN9
|
||||
phinc[6] => Add0.IN8
|
||||
phinc[7] => Add0.IN7
|
||||
clk => acc[0].CLK
|
||||
clk => acc[1].CLK
|
||||
clk => acc[2].CLK
|
||||
clk => acc[3].CLK
|
||||
clk => acc[4].CLK
|
||||
clk => acc[5].CLK
|
||||
clk => acc[6].CLK
|
||||
clk => acc[7].CLK
|
||||
clk => acc[8].CLK
|
||||
clk => acc[9].CLK
|
||||
clk => acc[10].CLK
|
||||
clk => acc[11].CLK
|
||||
clk => acc[12].CLK
|
||||
clk => acc[13].CLK
|
||||
clr_n => acc[0].ACLR
|
||||
clr_n => acc[1].ACLR
|
||||
clr_n => acc[2].ACLR
|
||||
clr_n => acc[3].ACLR
|
||||
clr_n => acc[4].ACLR
|
||||
clr_n => acc[5].ACLR
|
||||
clr_n => acc[6].ACLR
|
||||
clr_n => acc[7].ACLR
|
||||
clr_n => acc[8].ACLR
|
||||
clr_n => acc[9].ACLR
|
||||
clr_n => acc[10].ACLR
|
||||
clr_n => acc[11].ACLR
|
||||
clr_n => acc[12].ACLR
|
||||
clr_n => acc[13].ACLR
|
||||
phase[0] <= acc[6].DB_MAX_OUTPUT_PORT_TYPE
|
||||
phase[1] <= acc[7].DB_MAX_OUTPUT_PORT_TYPE
|
||||
phase[2] <= acc[8].DB_MAX_OUTPUT_PORT_TYPE
|
||||
phase[3] <= acc[9].DB_MAX_OUTPUT_PORT_TYPE
|
||||
phase[4] <= acc[10].DB_MAX_OUTPUT_PORT_TYPE
|
||||
phase[5] <= acc[11].DB_MAX_OUTPUT_PORT_TYPE
|
||||
phase[6] <= acc[12].DB_MAX_OUTPUT_PORT_TYPE
|
||||
phase[7] <= acc[13].DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
Binary file not shown.
|
|
@ -1,18 +0,0 @@
|
|||
<TABLE>
|
||||
<TR bgcolor="#C0C0C0">
|
||||
<TH>Hierarchy</TH>
|
||||
<TH>Input</TH>
|
||||
<TH>Constant Input</TH>
|
||||
<TH>Unused Input</TH>
|
||||
<TH>Floating Input</TH>
|
||||
<TH>Output</TH>
|
||||
<TH>Constant Output</TH>
|
||||
<TH>Unused Output</TH>
|
||||
<TH>Floating Output</TH>
|
||||
<TH>Bidir</TH>
|
||||
<TH>Constant Bidir</TH>
|
||||
<TH>Unused Bidir</TH>
|
||||
<TH>Input only Bidir</TH>
|
||||
<TH>Output only Bidir</TH>
|
||||
</TR>
|
||||
</TABLE>
|
||||
Binary file not shown.
|
|
@ -1,5 +0,0 @@
|
|||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Legal Partition Candidates ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1 +0,0 @@
|
|||
v1
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673883395012 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 16 18:36:34 2023 " "Processing started: Mon Jan 16 18:36:34 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel " "Found entity 1: sigdel" { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sigdel_tb.sv 1 1 " "Found 1 design units, including 1 entities, in source file sigdel_tb.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel_tb " "Found entity 1: sigdel_tb" { } { { "sigdel_tb.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Testbench/sigdel/sigdel_tb.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "sigdel " "Elaborating entity \"sigdel\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1673883401097 ""}
|
||||
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1673883401388 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1673883401553 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1673883401553 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "32 " "Implemented 32 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1673883401619 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1673883401619 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1047 " "Peak virtual memory: 1047 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 16 18:36:41 2023 " "Processing ended: Mon Jan 16 18:36:41 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401622 ""}
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1 +0,0 @@
|
|||
v1
|
||||
Binary file not shown.
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Binary file not shown.
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Binary file not shown.
|
|
@ -1 +0,0 @@
|
|||
FIT
|
||||
Binary file not shown.
|
|
@ -1,81 +0,0 @@
|
|||
{
|
||||
"partitions" : [
|
||||
{
|
||||
"name" : "Top",
|
||||
"pins" : [
|
||||
{
|
||||
"name" : "phase[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phase[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phase[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phase[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phase[4]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phase[5]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phase[6]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phase[7]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "clk",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "clr_n",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[6]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[7]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[5]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[4]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "phinc[0]",
|
||||
"strict" : false
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
`timescale 1 ns/1 ns
|
||||
|
||||
module inc_lut_tb();
|
||||
|
||||
// Parameters
|
||||
localparam CLK_PRD = 20;
|
||||
localparam PHACC_WIDTH = 14;
|
||||
|
||||
logic clk, clr_n, wr_n;
|
||||
logic [7:0] phinc_val, phase, sine;
|
||||
|
||||
// Instantiate UUT and connect used ports
|
||||
phacc phacc(.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
|
||||
defparam phacc.WIDTH = PHACC_WIDTH;
|
||||
|
||||
sinelut sinelut_inst (
|
||||
.address (phase), .clock (clk), .q(sine)
|
||||
);
|
||||
|
||||
|
||||
// Clock definition
|
||||
initial begin
|
||||
clk = 0;
|
||||
forever #(CLK_PRD/2) clk = ~clk;
|
||||
end
|
||||
|
||||
// Reset and initial values definition
|
||||
initial begin
|
||||
clr_n = 0;
|
||||
#(CLK_PRD*5) clr_n = 1;
|
||||
end
|
||||
|
||||
// Bus write transaction simulation
|
||||
initial begin
|
||||
// Wait until system is out of reset
|
||||
@(posedge clr_n);
|
||||
|
||||
phinc_val=(2**(PHACC_WIDTH - 8));
|
||||
if ((phinc_val <= 255) && (phinc_val != 0)) begin
|
||||
#(CLK_PRD * 256 * 5) $stop;
|
||||
end else begin
|
||||
$display("Error: value of phase increment is out of range! Stopped simulation.");
|
||||
#1 $stop;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
This folder contains data for incremental compilation.
|
||||
|
||||
The compiled_partitions sub-folder contains previous compilation results for each partition.
|
||||
As long as this folder is preserved, incremental compilation results from earlier compiles
|
||||
can be re-used. To perform a clean compilation from source files for all partitions, both
|
||||
the db and incremental_db folder should be removed.
|
||||
|
||||
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
|
||||
As long as this folder is preserved, imported partitions will be automatically re-imported
|
||||
when the db or incremental_db/compiled_partitions folders are removed.
|
||||
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
|
||||
Version_Index = 486699264
|
||||
Creation_Time = Thu Jan 12 13:26:18 2023
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1 +0,0 @@
|
|||
7aee213afbf8301ed5eefc8c827f49a3
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,30 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
|
||||
# Date created = 10:16:23 January 27, 2023
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "18.1"
|
||||
DATE = "10:16:23 January 27, 2023"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "sigdel"
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
|
||||
# Date created = 10:16:23 January 27, 2023
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# sigdel_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name DEVICE EP4CE6E22A7
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY sigdel
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:16:23 JANUARY 27, 2023"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
|
||||
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/phacc.sv
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name QIP_FILE ../../HDL/IP/sinelut.qip
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/sigdel.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE inc_lut_tb.sv
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
|
||||
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH inc_lut_tb -section_id eda_simulation
|
||||
set_global_assignment -name EDA_TEST_BENCH_NAME inc_lut_tb -section_id eda_simulation
|
||||
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id inc_lut_tb
|
||||
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME inc_lut_tb -section_id inc_lut_tb
|
||||
set_global_assignment -name EDA_TEST_BENCH_FILE inc_lut_tb.sv -section_id inc_lut_tb
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
|
|
@ -0,0 +1,242 @@
|
|||
WIDTH = 8;
|
||||
DEPTH = 256;
|
||||
|
||||
ADDRESS_RADIX = DEC;
|
||||
DATA_RADIX = HEX;
|
||||
|
||||
CONTENT BEGIN
|
||||
0 : 02;
|
||||
1 : 05;
|
||||
2 : 08;
|
||||
3 : 0B;
|
||||
4 : 0E;
|
||||
5 : 11;
|
||||
6 : 14;
|
||||
7 : 17;
|
||||
8 : 1A;
|
||||
9 : 1D;
|
||||
10 : 20;
|
||||
11 : 23;
|
||||
12 : 26;
|
||||
13 : 29;
|
||||
14 : 2C;
|
||||
15 : 2F;
|
||||
16 : 32;
|
||||
17 : 35;
|
||||
18 : 38;
|
||||
19 : 3A;
|
||||
20 : 3D;
|
||||
21 : 40;
|
||||
22 : 43;
|
||||
23 : 45;
|
||||
24 : 48;
|
||||
25 : 4A;
|
||||
26 : 4D;
|
||||
27 : 4F;
|
||||
28 : 52;
|
||||
29 : 54;
|
||||
30 : 56;
|
||||
31 : 59;
|
||||
32 : 5B;
|
||||
33 : 5D;
|
||||
34 : 5F;
|
||||
35 : 61;
|
||||
36 : 63;
|
||||
37 : 65;
|
||||
38 : 67;
|
||||
39 : 69;
|
||||
40 : 6A;
|
||||
41 : 6C;
|
||||
42 : 6E;
|
||||
43 : 6F;
|
||||
44 : 71;
|
||||
45 : 72;
|
||||
46 : 73;
|
||||
47 : 75;
|
||||
48 : 76;
|
||||
49 : 77;
|
||||
50 : 78;
|
||||
51 : 79;
|
||||
52 : 7A;
|
||||
53 : 7B;
|
||||
54 : 7C;
|
||||
55 : 7C;
|
||||
56 : 7D;
|
||||
57 : 7D;
|
||||
[58..69] : 7E;
|
||||
70 : 7D;
|
||||
71 : 7D;
|
||||
72 : 7C;
|
||||
73 : 7C;
|
||||
74 : 7B;
|
||||
75 : 7A;
|
||||
76 : 79;
|
||||
77 : 78;
|
||||
78 : 77;
|
||||
79 : 76;
|
||||
80 : 75;
|
||||
81 : 73;
|
||||
82 : 72;
|
||||
83 : 71;
|
||||
84 : 6F;
|
||||
85 : 6E;
|
||||
86 : 6C;
|
||||
87 : 6A;
|
||||
88 : 69;
|
||||
89 : 67;
|
||||
90 : 65;
|
||||
91 : 63;
|
||||
92 : 61;
|
||||
93 : 5F;
|
||||
94 : 5D;
|
||||
95 : 5B;
|
||||
96 : 59;
|
||||
97 : 56;
|
||||
98 : 54;
|
||||
99 : 52;
|
||||
100 : 4F;
|
||||
101 : 4D;
|
||||
102 : 4A;
|
||||
103 : 48;
|
||||
104 : 45;
|
||||
105 : 43;
|
||||
106 : 40;
|
||||
107 : 3D;
|
||||
108 : 3A;
|
||||
109 : 38;
|
||||
110 : 35;
|
||||
111 : 32;
|
||||
112 : 2F;
|
||||
113 : 2C;
|
||||
114 : 29;
|
||||
115 : 26;
|
||||
116 : 23;
|
||||
117 : 20;
|
||||
118 : 1D;
|
||||
119 : 1A;
|
||||
120 : 17;
|
||||
121 : 14;
|
||||
122 : 11;
|
||||
123 : 0E;
|
||||
124 : 0B;
|
||||
125 : 08;
|
||||
126 : 05;
|
||||
127 : 02;
|
||||
128 : FE;
|
||||
129 : FB;
|
||||
130 : F8;
|
||||
131 : F5;
|
||||
132 : F2;
|
||||
133 : EF;
|
||||
134 : EC;
|
||||
135 : E9;
|
||||
136 : E6;
|
||||
137 : E3;
|
||||
138 : E0;
|
||||
139 : DD;
|
||||
140 : DA;
|
||||
141 : D7;
|
||||
142 : D4;
|
||||
143 : D1;
|
||||
144 : CE;
|
||||
145 : CB;
|
||||
146 : C8;
|
||||
147 : C6;
|
||||
148 : C3;
|
||||
149 : C0;
|
||||
150 : BD;
|
||||
151 : BB;
|
||||
152 : B8;
|
||||
153 : B6;
|
||||
154 : B3;
|
||||
155 : B1;
|
||||
156 : AE;
|
||||
157 : AC;
|
||||
158 : AA;
|
||||
159 : A7;
|
||||
160 : A5;
|
||||
161 : A3;
|
||||
162 : A1;
|
||||
163 : 9F;
|
||||
164 : 9D;
|
||||
165 : 9B;
|
||||
166 : 99;
|
||||
167 : 97;
|
||||
168 : 96;
|
||||
169 : 94;
|
||||
170 : 92;
|
||||
171 : 91;
|
||||
172 : 8F;
|
||||
173 : 8E;
|
||||
174 : 8D;
|
||||
175 : 8B;
|
||||
176 : 8A;
|
||||
177 : 89;
|
||||
178 : 88;
|
||||
179 : 87;
|
||||
180 : 86;
|
||||
181 : 85;
|
||||
182 : 84;
|
||||
183 : 84;
|
||||
184 : 83;
|
||||
185 : 83;
|
||||
[186..197] : 82;
|
||||
198 : 83;
|
||||
199 : 83;
|
||||
200 : 84;
|
||||
201 : 84;
|
||||
202 : 85;
|
||||
203 : 86;
|
||||
204 : 87;
|
||||
205 : 88;
|
||||
206 : 89;
|
||||
207 : 8A;
|
||||
208 : 8B;
|
||||
209 : 8D;
|
||||
210 : 8E;
|
||||
211 : 8F;
|
||||
212 : 91;
|
||||
213 : 92;
|
||||
214 : 94;
|
||||
215 : 96;
|
||||
216 : 97;
|
||||
217 : 99;
|
||||
218 : 9B;
|
||||
219 : 9D;
|
||||
220 : 9F;
|
||||
221 : A1;
|
||||
222 : A3;
|
||||
223 : A5;
|
||||
224 : A7;
|
||||
225 : AA;
|
||||
226 : AC;
|
||||
227 : AE;
|
||||
228 : B1;
|
||||
229 : B3;
|
||||
230 : B6;
|
||||
231 : B8;
|
||||
232 : BB;
|
||||
233 : BD;
|
||||
234 : C0;
|
||||
235 : C3;
|
||||
236 : C6;
|
||||
237 : C8;
|
||||
238 : CB;
|
||||
239 : CE;
|
||||
240 : D1;
|
||||
241 : D4;
|
||||
242 : D7;
|
||||
243 : DA;
|
||||
244 : DD;
|
||||
245 : E0;
|
||||
246 : E3;
|
||||
247 : E6;
|
||||
248 : E9;
|
||||
249 : EC;
|
||||
250 : EF;
|
||||
251 : F2;
|
||||
252 : F5;
|
||||
253 : F8;
|
||||
254 : FB;
|
||||
255 : FE;
|
||||
END;
|
||||
Binary file not shown.
|
|
@ -0,0 +1,40 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>ci_project</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>com.altera.sbtgui.project.makefileBuilder</name>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>com.altera.sbtgui.project.makefileBuilder</name>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
<nature>org.eclipse.cdt.core.ccnature</nature>
|
||||
<nature>com.altera.sbtgui.project.SBTGUINature</nature>
|
||||
<nature>com.altera.sbtgui.project.SBTGUIAppNature</nature>
|
||||
<nature>com.altera.sbtgui.project.SBTGUIManagedNature</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project>
|
||||
<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" name="Nios II">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="-1220411458136844691" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
</extension>
|
||||
</configuration>
|
||||
</project>
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project>
|
||||
<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" name="Nios II">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="-1220411458136844691" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
</extension>
|
||||
</configuration>
|
||||
</project>
|
||||
Loading…
Reference in New Issue