ram32ok
This commit is contained in:
parent
6291090406
commit
881e124d27
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@ -10,7 +10,7 @@ module dec
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output logic [31:0] ctl_rddata,
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output logic [31:0] ctl_rddata,
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//memory slave
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//memory slave
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input logic ram_wr,
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input logic ram_wr,
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input logic [1:0] ram_addr,
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input logic [3:0] ram_addr,
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input logic [31:0] ram_wrdata,
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input logic [31:0] ram_wrdata,
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//external ports
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//external ports
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input logic train,
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input logic train,
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Binary file not shown.
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@ -1,11 +1,11 @@
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# TCL File Generated by Component Editor 18.1
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# TCL File Generated by Component Editor 18.1
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# Wed Dec 21 21:00:10 MSK 2022
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# Thu Dec 22 22:35:53 MSK 2022
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# DO NOT MODIFY
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# DO NOT MODIFY
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#
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#
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# sem "Semafor" v1.1
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# sem "Semafor" v1.1
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# 2022.12.21.21:00:10
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# 2022.12.22.22:35:53
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#
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#
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#
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#
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@ -163,7 +163,7 @@ set_interface_property ram_slave CMSIS_SVD_VARIABLES ""
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set_interface_property ram_slave SVD_ADDRESS_GROUP ""
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set_interface_property ram_slave SVD_ADDRESS_GROUP ""
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add_interface_port ram_slave ram_wr write Input 1
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add_interface_port ram_slave ram_wr write Input 1
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add_interface_port ram_slave ram_addr address Input 2
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add_interface_port ram_slave ram_addr address Input 4
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add_interface_port ram_slave ram_wrdata writedata Input 32
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add_interface_port ram_slave ram_wrdata writedata Input 32
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set_interface_assignment ram_slave embeddedsw.configuration.isFlash 0
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set_interface_assignment ram_slave embeddedsw.configuration.isFlash 0
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set_interface_assignment ram_slave embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment ram_slave embeddedsw.configuration.isMemoryDevice 0
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@ -1,11 +1,11 @@
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# TCL File Generated by Component Editor 18.1
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# TCL File Generated by Component Editor 18.1
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# Mon Dec 19 20:23:41 MSK 2022
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# Wed Dec 21 21:00:10 MSK 2022
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# DO NOT MODIFY
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# DO NOT MODIFY
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#
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#
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# sem "Semafor" v1.1
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# sem "Semafor" v1.1
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# 2022.12.19.20:23:40
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# 2022.12.21.21:00:10
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#
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#
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#
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#
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@ -45,7 +45,7 @@
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{
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{
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datum baseAddress
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datum baseAddress
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{
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{
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value = "135224";
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value = "135272";
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type = "String";
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type = "String";
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}
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}
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}
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}
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@ -97,6 +97,14 @@
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type = "String";
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type = "String";
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}
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}
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}
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}
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element niosII
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone IV E";
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type = "String";
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}
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}
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element sem
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element sem
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{
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{
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datum _sortIndex
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datum _sortIndex
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@ -109,7 +117,7 @@
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{
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{
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datum baseAddress
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datum baseAddress
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{
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{
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value = "135216";
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value = "135264";
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type = "String";
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type = "String";
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}
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}
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}
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}
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@ -117,7 +125,7 @@
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{
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{
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datum baseAddress
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datum baseAddress
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{
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{
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value = "135200";
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value = "135168";
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type = "String";
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type = "String";
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}
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}
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}
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}
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@ -133,7 +141,7 @@
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{
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{
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datum baseAddress
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datum baseAddress
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{
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{
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value = "135168";
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value = "135232";
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type = "String";
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type = "String";
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}
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}
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}
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}
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@ -187,7 +195,7 @@
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<parameter name="dataAddrWidth" value="18" />
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<parameter name="dataAddrWidth" value="18" />
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<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
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<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
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<parameter name="dataMasterHighPerformanceMapParam" value="" />
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<parameter name="dataMasterHighPerformanceMapParam" value="" />
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<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
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<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
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<parameter name="data_master_high_performance_paddr_base" value="0" />
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<parameter name="data_master_high_performance_paddr_base" value="0" />
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<parameter name="data_master_high_performance_paddr_size" value="0" />
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<parameter name="data_master_high_performance_paddr_size" value="0" />
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<parameter name="data_master_paddr_base" value="0" />
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<parameter name="data_master_paddr_base" value="0" />
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@ -421,7 +429,7 @@
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start="cpu.data_master"
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start="cpu.data_master"
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end="jtag_uart.avalon_jtag_slave">
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end="jtag_uart.avalon_jtag_slave">
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="baseAddress" value="0x00021038" />
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<parameter name="baseAddress" value="0x00021068" />
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<parameter name="defaultConnection" value="false" />
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<parameter name="defaultConnection" value="false" />
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</connection>
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</connection>
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<connection
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<connection
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@ -430,7 +438,7 @@
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start="cpu.data_master"
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start="cpu.data_master"
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end="sem.ctl_slave">
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end="sem.ctl_slave">
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="baseAddress" value="0x00021030" />
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<parameter name="baseAddress" value="0x00021060" />
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<parameter name="defaultConnection" value="false" />
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<parameter name="defaultConnection" value="false" />
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</connection>
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</connection>
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<connection
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<connection
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start="cpu.data_master"
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start="cpu.data_master"
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end="sem.ram_slave">
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end="sem.ram_slave">
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="baseAddress" value="0x00021020" />
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<parameter name="baseAddress" value="0x00021000" />
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<parameter name="defaultConnection" value="false" />
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<parameter name="defaultConnection" value="false" />
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</connection>
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</connection>
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<connection
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<connection
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start="cpu.data_master"
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start="cpu.data_master"
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end="sys_clk_timer.s1">
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end="sys_clk_timer.s1">
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="arbitrationPriority" value="1" />
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<parameter name="baseAddress" value="0x00021000" />
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<parameter name="baseAddress" value="0x00021040" />
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<parameter name="defaultConnection" value="false" />
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<parameter name="defaultConnection" value="false" />
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</connection>
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</connection>
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<connection kind="avalon" version="18.1" start="cpu.data_master" end="mem.s2">
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<connection kind="avalon" version="18.1" start="cpu.data_master" end="mem.s2">
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@ -1,11 +1,11 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
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<EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
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<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
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<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
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<!-- 2022.12.22.17:19:01 -->
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<!-- 2022.12.22.22:38:31 -->
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<!-- A collection of modules and connections -->
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<!-- A collection of modules and connections -->
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<parameter name="AUTO_GENERATION_ID">
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<parameter name="AUTO_GENERATION_ID">
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<type>java.lang.Integer</type>
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<type>java.lang.Integer</type>
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<value>1671715140</value>
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<value>1671734311</value>
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<derived>false</derived>
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<derived>false</derived>
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<enabled>true</enabled>
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<enabled>true</enabled>
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<visible>false</visible>
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<visible>false</visible>
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@ -2034,7 +2034,7 @@ the requested settings for a module instance. -->
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</parameter>
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</parameter>
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<parameter name="dataSlaveMapParam">
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<parameter name="dataSlaveMapParam">
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<type>java.lang.String</type>
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<type>java.lang.String</type>
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<value><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></value>
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<value><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></value>
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<derived>false</derived>
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<derived>false</derived>
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<enabled>true</enabled>
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<enabled>true</enabled>
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<visible>false</visible>
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<visible>false</visible>
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@ -2705,7 +2705,7 @@ parameters are a RESULT of the module parameters. -->
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<moduleName>jtag_uart</moduleName>
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<moduleName>jtag_uart</moduleName>
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<slaveName>avalon_jtag_slave</slaveName>
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<slaveName>avalon_jtag_slave</slaveName>
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<name>jtag_uart.avalon_jtag_slave</name>
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<name>jtag_uart.avalon_jtag_slave</name>
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<baseAddress>135224</baseAddress>
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<baseAddress>135272</baseAddress>
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<span>8</span>
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<span>8</span>
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</memoryBlock>
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</memoryBlock>
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<memoryBlock>
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<memoryBlock>
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<moduleName>sem</moduleName>
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<moduleName>sem</moduleName>
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<slaveName>ctl_slave</slaveName>
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<slaveName>ctl_slave</slaveName>
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<name>sem.ctl_slave</name>
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<name>sem.ctl_slave</name>
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<baseAddress>135216</baseAddress>
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<baseAddress>135264</baseAddress>
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<span>8</span>
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<span>8</span>
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</memoryBlock>
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</memoryBlock>
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<memoryBlock>
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<memoryBlock>
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<moduleName>sem</moduleName>
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<moduleName>sem</moduleName>
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<slaveName>ram_slave</slaveName>
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<slaveName>ram_slave</slaveName>
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<name>sem.ram_slave</name>
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<name>sem.ram_slave</name>
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<baseAddress>135200</baseAddress>
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<baseAddress>135168</baseAddress>
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<span>16</span>
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<span>64</span>
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</memoryBlock>
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</memoryBlock>
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<memoryBlock>
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<memoryBlock>
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<isBridge>false</isBridge>
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<isBridge>false</isBridge>
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<moduleName>sys_clk_timer</moduleName>
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<moduleName>sys_clk_timer</moduleName>
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<slaveName>s1</slaveName>
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<slaveName>s1</slaveName>
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<name>sys_clk_timer.s1</name>
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<name>sys_clk_timer.s1</name>
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<baseAddress>135168</baseAddress>
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<baseAddress>135232</baseAddress>
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<span>32</span>
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<span>32</span>
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</memoryBlock>
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</memoryBlock>
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<memoryBlock>
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<memoryBlock>
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</parameter>
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</parameter>
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<parameter name="addressSpan">
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<parameter name="addressSpan">
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<type>java.math.BigInteger</type>
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<type>java.math.BigInteger</type>
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<value>16</value>
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<value>64</value>
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<derived>true</derived>
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<derived>true</derived>
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<enabled>true</enabled>
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<enabled>true</enabled>
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<visible>false</visible>
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<visible>false</visible>
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@ -6477,7 +6477,7 @@ parameters are a RESULT of the module parameters. -->
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<port>
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<port>
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<name>ram_addr</name>
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<name>ram_addr</name>
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<direction>Input</direction>
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<direction>Input</direction>
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<width>2</width>
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<width>4</width>
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<role>address</role>
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<role>address</role>
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</port>
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</port>
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<port>
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<port>
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@ -7349,7 +7349,7 @@ parameters are a RESULT of the module parameters. -->
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</parameter>
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</parameter>
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<parameter name="baseAddress">
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<parameter name="baseAddress">
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<type>java.math.BigInteger</type>
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<type>java.math.BigInteger</type>
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<value>0x00021038</value>
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<value>0x00021068</value>
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<derived>false</derived>
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<derived>false</derived>
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<enabled>true</enabled>
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<enabled>true</enabled>
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<visible>true</visible>
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<visible>true</visible>
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@ -7400,7 +7400,7 @@ parameters are a RESULT of the module parameters. -->
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</parameter>
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</parameter>
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<parameter name="baseAddress">
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<parameter name="baseAddress">
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<type>java.math.BigInteger</type>
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<type>java.math.BigInteger</type>
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<value>0x00021030</value>
|
<value>0x00021060</value>
|
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<derived>false</derived>
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<derived>false</derived>
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<enabled>true</enabled>
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<enabled>true</enabled>
|
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<visible>true</visible>
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<visible>true</visible>
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@ -7502,7 +7502,7 @@ parameters are a RESULT of the module parameters. -->
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</parameter>
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</parameter>
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<parameter name="baseAddress">
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<parameter name="baseAddress">
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<type>java.math.BigInteger</type>
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<type>java.math.BigInteger</type>
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<value>0x00021020</value>
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<value>0x00021000</value>
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<derived>false</derived>
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<derived>false</derived>
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<enabled>true</enabled>
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<enabled>true</enabled>
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<visible>true</visible>
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<visible>true</visible>
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@ -7553,7 +7553,7 @@ parameters are a RESULT of the module parameters. -->
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</parameter>
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</parameter>
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<parameter name="baseAddress">
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<parameter name="baseAddress">
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<type>java.math.BigInteger</type>
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<type>java.math.BigInteger</type>
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<value>0x00021000</value>
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<value>0x00021040</value>
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<derived>false</derived>
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<derived>false</derived>
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<enabled>true</enabled>
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<enabled>true</enabled>
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<visible>true</visible>
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<visible>true</visible>
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|
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@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
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</table>
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</table>
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<table class="blueBar">
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<table class="blueBar">
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<tr>
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<tr>
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||||||
<td class="l">2022.12.21.21:02:26</td>
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<td class="l">2022.12.22.22:37:23</td>
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<td class="r">Datasheet</td>
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<td class="r">Datasheet</td>
|
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</tr>
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</tr>
|
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</table>
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</table>
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@ -144,7 +144,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
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</tr>
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</tr>
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<tr>
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<tr>
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<td class="slaveb">avalon_jtag_slave </td>
|
<td class="slaveb">avalon_jtag_slave </td>
|
||||||
<td class="addr"><span style="color:#989898">0x</span>00021038</td>
|
<td class="addr"><span style="color:#989898">0x</span>00021068</td>
|
||||||
<td class="empty"></td>
|
<td class="empty"></td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
|
@ -175,12 +175,12 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="slavem">ctl_slave </td>
|
<td class="slavem">ctl_slave </td>
|
||||||
<td class="addr"><span style="color:#989898">0x</span>00021030</td>
|
<td class="addr"><span style="color:#989898">0x</span>00021060</td>
|
||||||
<td class="empty"></td>
|
<td class="empty"></td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="slavem">ram_slave </td>
|
<td class="slavem">ram_slave </td>
|
||||||
<td class="addr"><span style="color:#989898">0x</span>00021020</td>
|
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
|
||||||
<td class="empty"></td>
|
<td class="empty"></td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
|
@ -193,7 +193,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="slaveb">s1 </td>
|
<td class="slaveb">s1 </td>
|
||||||
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
|
<td class="addr"><span style="color:#989898">0x</span>00021040</td>
|
||||||
<td class="empty"></td>
|
<td class="empty"></td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
|
@ -1107,7 +1107,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="parametername">dataSlaveMapParam</td>
|
<td class="parametername">dataSlaveMapParam</td>
|
||||||
<td class="parametervalue"><address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map></td>
|
<td class="parametervalue"><address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map></td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
|
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
|
||||||
|
@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</div>
|
</div>
|
||||||
<table class="blueBar">
|
<table class="blueBar">
|
||||||
<tr>
|
<tr>
|
||||||
<td class="l">generation took 0,00 seconds</td>
|
<td class="l">generation took 0,01 seconds</td>
|
||||||
<td class="r">rendering took 0,05 seconds</td>
|
<td class="r">rendering took 0,08 seconds</td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
</body>
|
</body>
|
||||||
|
|
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1"
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1"
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys"
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys"
|
||||||
set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"]
|
set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"]
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671642146"
|
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671734242"
|
||||||
set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"]
|
set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"]
|
||||||
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"]
|
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"]
|
||||||
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"]
|
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"]
|
||||||
|
@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTY0MjE0Ng==::QXV0byBHRU5FUkFUSU9OX0lE"
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTczNDI0Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U="
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U="
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
|
||||||
|
@ -365,11 +365,11 @@ set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ=="
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ=="
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MywwLDYsNSw0LDE=::RGVzdGluYXRpb24gSUQ="
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MywwLDUsNiw0LDE=::RGVzdGluYXRpb24gSUQ="
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MTAwMDAwLDAwMDEwMCwwMTAwMDAsMDAxMDAwLDAwMDAxMCwwMDAwMDE=::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MTAwMDAwLDAwMDEwMCwwMDEwMDAsMDEwMDAwLDAwMDAxMCwwMDAwMDE=::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxib3RoLGJvdGgsd3JpdGUsYm90aCxib3Ro::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxib3RoLHdyaXRlLGJvdGgsYm90aCxib3Ro::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgwLDB4MjA4MDAsMHgyMTAwMCwweDIxMDIwLDB4MjEwMzAsMHgyMTAzOA==::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgwLDB4MjA4MDAsMHgyMTAwMCwweDIxMDQwLDB4MjEwNjAsMHgyMTA2OA==::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgyMDAwMCwweDIxMDAwLDB4MjEwMjAsMHgyMTAzMCwweDIxMDM4LDB4MjEwNDA=::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgyMDAwMCwweDIxMDAwLDB4MjEwNDAsMHgyMTA2MCwweDIxMDY4LDB4MjEwNzA=::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwxLDEsMSwxLDE=::Tm9uLXNlY3VyZWQgdGFncw=="
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwxLDEsMSwxLDE=::Tm9uLXNlY3VyZWQgdGFncw=="
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCwwLDAsMCwwLDA=::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCwwLDAsMCwwLDA=::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCwwLDAsMCwwLDA=::U2VjdXJlZCByYW5nZSBwYWlycw=="
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCwwLDAsMCwwLDA=::U2VjdXJlZCByYW5nZSBwYWlycw=="
|
||||||
|
@ -383,7 +383,7 @@ set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MzoxMDAwMDA6MHgwOjB4MjAwMDA6Ym90aDoxOjA6MDoxLDA6MDAwMTAwOjB4MjA4MDA6MHgyMTAwMDpib3RoOjE6MDowOjEsNjowMTAwMDA6MHgyMTAwMDoweDIxMDIwOmJvdGg6MTowOjA6MSw1OjAwMTAwMDoweDIxMDIwOjB4MjEwMzA6d3JpdGU6MTowOjA6MSw0OjAwMDAxMDoweDIxMDMwOjB4MjEwMzg6Ym90aDoxOjA6MDoxLDE6MDAwMDAxOjB4MjEwMzg6MHgyMTA0MDpib3RoOjE6MDowOjE=::U0xBVkVTX0lORk8="
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MzoxMDAwMDA6MHgwOjB4MjAwMDA6Ym90aDoxOjA6MDoxLDA6MDAwMTAwOjB4MjA4MDA6MHgyMTAwMDpib3RoOjE6MDowOjEsNTowMDEwMDA6MHgyMTAwMDoweDIxMDQwOndyaXRlOjE6MDowOjEsNjowMTAwMDA6MHgyMTA0MDoweDIxMDYwOmJvdGg6MTowOjA6MSw0OjAwMDAxMDoweDIxMDYwOjB4MjEwNjg6Ym90aDoxOjA6MDoxLDE6MDAwMDAxOjB4MjEwNjg6MHgyMTA3MDpib3RoOjE6MDowOjE=::U0xBVkVTX0lORk8="
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MA==::RGVjb2RlciB0eXBl"
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MA==::RGVjb2RlciB0eXBl"
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::NQ==::RGVmYXVsdCBjaGFubmVs"
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::NQ==::RGVmYXVsdCBjaGFubmVs"
|
||||||
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
|
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
|
||||||
|
@ -859,7 +859,7 @@ set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_
|
||||||
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
|
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
|
||||||
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
|
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
|
||||||
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0="
|
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0="
|
||||||
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTAzMCcgZW5kPScweDIxMDM4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDM4JyBlbmQ9JzB4MjEwNDAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0="
|
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDQwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTA0MCcgZW5kPScweDIxMDYwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTA2MCcgZW5kPScweDIxMDY4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDY4JyBlbmQ9JzB4MjEwNzAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0="
|
||||||
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k="
|
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k="
|
||||||
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ=="
|
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ=="
|
||||||
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="
|
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="
|
||||||
|
@ -1042,7 +1042,7 @@ set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPON
|
||||||
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
|
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
|
||||||
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
|
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
|
||||||
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0="
|
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0="
|
||||||
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTAzMCcgZW5kPScweDIxMDM4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDM4JyBlbmQ9JzB4MjEwNDAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0="
|
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDQwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTA0MCcgZW5kPScweDIxMDYwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTA2MCcgZW5kPScweDIxMDY4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDY4JyBlbmQ9JzB4MjEwNzAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0="
|
||||||
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k="
|
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k="
|
||||||
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ=="
|
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ=="
|
||||||
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="
|
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="
|
||||||
|
|
|
@ -44,7 +44,7 @@ module niosII (
|
||||||
wire [3:0] mm_interconnect_0_cpu_debug_mem_slave_byteenable; // mm_interconnect_0:cpu_debug_mem_slave_byteenable -> cpu:debug_mem_slave_byteenable
|
wire [3:0] mm_interconnect_0_cpu_debug_mem_slave_byteenable; // mm_interconnect_0:cpu_debug_mem_slave_byteenable -> cpu:debug_mem_slave_byteenable
|
||||||
wire mm_interconnect_0_cpu_debug_mem_slave_write; // mm_interconnect_0:cpu_debug_mem_slave_write -> cpu:debug_mem_slave_write
|
wire mm_interconnect_0_cpu_debug_mem_slave_write; // mm_interconnect_0:cpu_debug_mem_slave_write -> cpu:debug_mem_slave_write
|
||||||
wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_writedata; // mm_interconnect_0:cpu_debug_mem_slave_writedata -> cpu:debug_mem_slave_writedata
|
wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_writedata; // mm_interconnect_0:cpu_debug_mem_slave_writedata -> cpu:debug_mem_slave_writedata
|
||||||
wire [1:0] mm_interconnect_0_sem_ram_slave_address; // mm_interconnect_0:sem_ram_slave_address -> sem:ram_addr
|
wire [3:0] mm_interconnect_0_sem_ram_slave_address; // mm_interconnect_0:sem_ram_slave_address -> sem:ram_addr
|
||||||
wire mm_interconnect_0_sem_ram_slave_write; // mm_interconnect_0:sem_ram_slave_write -> sem:ram_wr
|
wire mm_interconnect_0_sem_ram_slave_write; // mm_interconnect_0:sem_ram_slave_write -> sem:ram_wr
|
||||||
wire [31:0] mm_interconnect_0_sem_ram_slave_writedata; // mm_interconnect_0:sem_ram_slave_writedata -> sem:ram_wrdata
|
wire [31:0] mm_interconnect_0_sem_ram_slave_writedata; // mm_interconnect_0:sem_ram_slave_writedata -> sem:ram_wrdata
|
||||||
wire mm_interconnect_0_sys_clk_timer_s1_chipselect; // mm_interconnect_0:sys_clk_timer_s1_chipselect -> sys_clk_timer:chipselect
|
wire mm_interconnect_0_sys_clk_timer_s1_chipselect; // mm_interconnect_0:sys_clk_timer_s1_chipselect -> sys_clk_timer:chipselect
|
||||||
|
|
|
@ -10,7 +10,7 @@ module dec
|
||||||
output logic [31:0] ctl_rddata,
|
output logic [31:0] ctl_rddata,
|
||||||
//memory slave
|
//memory slave
|
||||||
input logic ram_wr,
|
input logic ram_wr,
|
||||||
input logic [1:0] ram_addr,
|
input logic [3:0] ram_addr,
|
||||||
input logic [31:0] ram_wrdata,
|
input logic [31:0] ram_wrdata,
|
||||||
//external ports
|
//external ports
|
||||||
input logic train,
|
input logic train,
|
||||||
|
|
|
@ -55,7 +55,7 @@ module niosII_mm_interconnect_0 (
|
||||||
output wire sem_ctl_slave_read, // .read
|
output wire sem_ctl_slave_read, // .read
|
||||||
input wire [31:0] sem_ctl_slave_readdata, // .readdata
|
input wire [31:0] sem_ctl_slave_readdata, // .readdata
|
||||||
output wire [31:0] sem_ctl_slave_writedata, // .writedata
|
output wire [31:0] sem_ctl_slave_writedata, // .writedata
|
||||||
output wire [1:0] sem_ram_slave_address, // sem_ram_slave.address
|
output wire [3:0] sem_ram_slave_address, // sem_ram_slave.address
|
||||||
output wire sem_ram_slave_write, // .write
|
output wire sem_ram_slave_write, // .write
|
||||||
output wire [31:0] sem_ram_slave_writedata, // .writedata
|
output wire [31:0] sem_ram_slave_writedata, // .writedata
|
||||||
output wire [2:0] sys_clk_timer_s1_address, // sys_clk_timer_s1.address
|
output wire [2:0] sys_clk_timer_s1_address, // sys_clk_timer_s1.address
|
||||||
|
@ -846,7 +846,7 @@ module niosII_mm_interconnect_0 (
|
||||||
);
|
);
|
||||||
|
|
||||||
altera_merlin_slave_translator #(
|
altera_merlin_slave_translator #(
|
||||||
.AV_ADDRESS_W (2),
|
.AV_ADDRESS_W (4),
|
||||||
.AV_DATA_W (32),
|
.AV_DATA_W (32),
|
||||||
.UAV_DATA_W (32),
|
.UAV_DATA_W (32),
|
||||||
.AV_BURSTCOUNT_W (1),
|
.AV_BURSTCOUNT_W (1),
|
||||||
|
|
|
@ -136,16 +136,16 @@ module niosII_mm_interconnect_0_router
|
||||||
// -------------------------------------------------------
|
// -------------------------------------------------------
|
||||||
localparam PAD0 = log2ceil(64'h20000 - 64'h0);
|
localparam PAD0 = log2ceil(64'h20000 - 64'h0);
|
||||||
localparam PAD1 = log2ceil(64'h21000 - 64'h20800);
|
localparam PAD1 = log2ceil(64'h21000 - 64'h20800);
|
||||||
localparam PAD2 = log2ceil(64'h21020 - 64'h21000);
|
localparam PAD2 = log2ceil(64'h21040 - 64'h21000);
|
||||||
localparam PAD3 = log2ceil(64'h21030 - 64'h21020);
|
localparam PAD3 = log2ceil(64'h21060 - 64'h21040);
|
||||||
localparam PAD4 = log2ceil(64'h21038 - 64'h21030);
|
localparam PAD4 = log2ceil(64'h21068 - 64'h21060);
|
||||||
localparam PAD5 = log2ceil(64'h21040 - 64'h21038);
|
localparam PAD5 = log2ceil(64'h21070 - 64'h21068);
|
||||||
// -------------------------------------------------------
|
// -------------------------------------------------------
|
||||||
// Work out which address bits are significant based on the
|
// Work out which address bits are significant based on the
|
||||||
// address range of the slaves. If the required width is too
|
// address range of the slaves. If the required width is too
|
||||||
// large or too small, we use the address field width instead.
|
// large or too small, we use the address field width instead.
|
||||||
// -------------------------------------------------------
|
// -------------------------------------------------------
|
||||||
localparam ADDR_RANGE = 64'h21040;
|
localparam ADDR_RANGE = 64'h21070;
|
||||||
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
|
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
|
||||||
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
|
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
|
||||||
(RANGE_ADDR_WIDTH == 0) ?
|
(RANGE_ADDR_WIDTH == 0) ?
|
||||||
|
@ -210,26 +210,26 @@ module niosII_mm_interconnect_0_router
|
||||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
|
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
|
||||||
end
|
end
|
||||||
|
|
||||||
// ( 0x21000 .. 0x21020 )
|
// ( 0x21000 .. 0x21040 )
|
||||||
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h21000 ) begin
|
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h21000 && write_transaction ) begin
|
||||||
src_channel = 7'b010000;
|
|
||||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
|
|
||||||
end
|
|
||||||
|
|
||||||
// ( 0x21020 .. 0x21030 )
|
|
||||||
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h21020 && write_transaction ) begin
|
|
||||||
src_channel = 7'b001000;
|
src_channel = 7'b001000;
|
||||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
|
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
|
||||||
end
|
end
|
||||||
|
|
||||||
// ( 0x21030 .. 0x21038 )
|
// ( 0x21040 .. 0x21060 )
|
||||||
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h21030 ) begin
|
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h21040 ) begin
|
||||||
|
src_channel = 7'b010000;
|
||||||
|
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
|
||||||
|
end
|
||||||
|
|
||||||
|
// ( 0x21060 .. 0x21068 )
|
||||||
|
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h21060 ) begin
|
||||||
src_channel = 7'b000010;
|
src_channel = 7'b000010;
|
||||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
|
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
|
||||||
end
|
end
|
||||||
|
|
||||||
// ( 0x21038 .. 0x21040 )
|
// ( 0x21068 .. 0x21070 )
|
||||||
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 18'h21038 ) begin
|
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 18'h21068 ) begin
|
||||||
src_channel = 7'b000001;
|
src_channel = 7'b000001;
|
||||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
|
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
|
||||||
end
|
end
|
||||||
|
|
|
@ -92,6 +92,13 @@ module periodram (
|
||||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
altsyncram_component.clock_enable_input_b = "BYPASS",
|
||||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
altsyncram_component.clock_enable_output_b = "BYPASS",
|
||||||
|
`ifdef NO_PLI
|
||||||
|
altsyncram_component.init_file = "periodram.rif"
|
||||||
|
`else
|
||||||
|
altsyncram_component.init_file = "periodram.hex"
|
||||||
|
`endif
|
||||||
|
,
|
||||||
|
altsyncram_component.init_file_layout = "PORT_B",
|
||||||
altsyncram_component.intended_device_family = "Cyclone IV E",
|
altsyncram_component.intended_device_family = "Cyclone IV E",
|
||||||
altsyncram_component.lpm_type = "altsyncram",
|
altsyncram_component.lpm_type = "altsyncram",
|
||||||
altsyncram_component.numwords_a = 16,
|
altsyncram_component.numwords_a = 16,
|
||||||
|
@ -120,7 +127,7 @@ endmodule
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
||||||
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
||||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
||||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||||
|
@ -145,7 +152,7 @@ endmodule
|
||||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||||
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
|
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
|
||||||
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
||||||
// Retrieval info: PRIVATE: MIFfilename STRING ""
|
// Retrieval info: PRIVATE: MIFfilename STRING "periodram.hex"
|
||||||
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
|
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
|
||||||
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
||||||
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
|
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
|
||||||
|
@ -178,6 +185,8 @@ endmodule
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
||||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
||||||
|
// Retrieval info: CONSTANT: INIT_FILE STRING "periodram.hex"
|
||||||
|
// Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_B"
|
||||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
|
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
|
||||||
|
|
|
@ -94,7 +94,7 @@
|
||||||
# within the Quartus project, and generate a unified
|
# within the Quartus project, and generate a unified
|
||||||
# script which supports all the Altera IP within the design.
|
# script which supports all the Altera IP within the design.
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# ACDS 18.1 625 win32 2022.12.21.21:02:08
|
# ACDS 18.1 625 win32 2022.12.22.22:39:16
|
||||||
|
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# Initialize variables
|
# Initialize variables
|
||||||
|
|
|
@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</table>
|
</table>
|
||||||
<table class="blueBar">
|
<table class="blueBar">
|
||||||
<tr>
|
<tr>
|
||||||
<td class="l">2022.12.21.21:01:24</td>
|
<td class="l">2022.12.22.22:38:31</td>
|
||||||
<td class="r">Datasheet</td>
|
<td class="r">Datasheet</td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
|
@ -144,7 +144,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="slaveb">avalon_jtag_slave </td>
|
<td class="slaveb">avalon_jtag_slave </td>
|
||||||
<td class="addr"><span style="color:#989898">0x</span>00021038</td>
|
<td class="addr"><span style="color:#989898">0x</span>00021068</td>
|
||||||
<td class="empty"></td>
|
<td class="empty"></td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
|
@ -175,12 +175,12 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="slavem">ctl_slave </td>
|
<td class="slavem">ctl_slave </td>
|
||||||
<td class="addr"><span style="color:#989898">0x</span>00021030</td>
|
<td class="addr"><span style="color:#989898">0x</span>00021060</td>
|
||||||
<td class="empty"></td>
|
<td class="empty"></td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="slavem">ram_slave </td>
|
<td class="slavem">ram_slave </td>
|
||||||
<td class="addr"><span style="color:#989898">0x</span>00021020</td>
|
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
|
||||||
<td class="empty"></td>
|
<td class="empty"></td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
|
@ -193,7 +193,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="slaveb">s1 </td>
|
<td class="slaveb">s1 </td>
|
||||||
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
|
<td class="addr"><span style="color:#989898">0x</span>00021040</td>
|
||||||
<td class="empty"></td>
|
<td class="empty"></td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
|
@ -1107,7 +1107,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="parametername">dataSlaveMapParam</td>
|
<td class="parametername">dataSlaveMapParam</td>
|
||||||
<td class="parametervalue"><address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map></td>
|
<td class="parametervalue"><address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map></td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
|
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
|
||||||
|
@ -2039,7 +2039,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
<table class="blueBar">
|
<table class="blueBar">
|
||||||
<tr>
|
<tr>
|
||||||
<td class="l">generation took 0,00 seconds</td>
|
<td class="l">generation took 0,00 seconds</td>
|
||||||
<td class="r">rendering took 0,08 seconds</td>
|
<td class="r">rendering took 0,04 seconds</td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
</body>
|
</body>
|
||||||
|
|
|
@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</table>
|
</table>
|
||||||
<table class="blueBar">
|
<table class="blueBar">
|
||||||
<tr>
|
<tr>
|
||||||
<td class="l">2022.12.21.21:01:33</td>
|
<td class="l">2022.12.22.22:38:42</td>
|
||||||
<td class="r">Datasheet</td>
|
<td class="r">Datasheet</td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
|
@ -144,7 +144,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="slaveb">avalon_jtag_slave </td>
|
<td class="slaveb">avalon_jtag_slave </td>
|
||||||
<td class="addr"><span style="color:#989898">0x</span>00021038</td>
|
<td class="addr"><span style="color:#989898">0x</span>00021068</td>
|
||||||
<td class="empty"></td>
|
<td class="empty"></td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
|
@ -175,12 +175,12 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="slavem">ctl_slave </td>
|
<td class="slavem">ctl_slave </td>
|
||||||
<td class="addr"><span style="color:#989898">0x</span>00021030</td>
|
<td class="addr"><span style="color:#989898">0x</span>00021060</td>
|
||||||
<td class="empty"></td>
|
<td class="empty"></td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="slavem">ram_slave </td>
|
<td class="slavem">ram_slave </td>
|
||||||
<td class="addr"><span style="color:#989898">0x</span>00021020</td>
|
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
|
||||||
<td class="empty"></td>
|
<td class="empty"></td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
|
@ -193,7 +193,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="slaveb">s1 </td>
|
<td class="slaveb">s1 </td>
|
||||||
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
|
<td class="addr"><span style="color:#989898">0x</span>00021040</td>
|
||||||
<td class="empty"></td>
|
<td class="empty"></td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
|
@ -211,7 +211,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
<table>
|
<table>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="parametername">AUTO_GENERATION_ID</td>
|
<td class="parametername">AUTO_GENERATION_ID</td>
|
||||||
<td class="parametervalue">1671642093</td>
|
<td class="parametervalue">1671734322</td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="parametername">AUTO_UNIQUE_ID</td>
|
<td class="parametername">AUTO_UNIQUE_ID</td>
|
||||||
|
@ -1323,7 +1323,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="parametername">dataSlaveMapParam</td>
|
<td class="parametername">dataSlaveMapParam</td>
|
||||||
<td class="parametervalue"><address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map></td>
|
<td class="parametervalue"><address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map></td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
|
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
|
||||||
|
@ -2359,8 +2359,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</div>
|
</div>
|
||||||
<table class="blueBar">
|
<table class="blueBar">
|
||||||
<tr>
|
<tr>
|
||||||
<td class="l">generation took 0,00 seconds</td>
|
<td class="l">generation took 0,02 seconds</td>
|
||||||
<td class="r">rendering took 0,06 seconds</td>
|
<td class="r">rendering took 0,05 seconds</td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
</body>
|
</body>
|
||||||
|
|
|
@ -12,7 +12,7 @@
|
||||||
# or its authorized distributors. Please refer to the applicable
|
# or its authorized distributors. Please refer to the applicable
|
||||||
# agreement for further details.
|
# agreement for further details.
|
||||||
|
|
||||||
# ACDS 18.1 625 win32 2022.12.21.21:02:08
|
# ACDS 18.1 625 win32 2022.12.22.22:39:16
|
||||||
|
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# vcs - auto-generated simulation script
|
# vcs - auto-generated simulation script
|
||||||
|
@ -94,7 +94,7 @@
|
||||||
# within the Quartus project, and generate a unified
|
# within the Quartus project, and generate a unified
|
||||||
# script which supports all the Altera IP within the design.
|
# script which supports all the Altera IP within the design.
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# ACDS 18.1 625 win32 2022.12.21.21:02:08
|
# ACDS 18.1 625 win32 2022.12.22.22:39:16
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# initialize variables
|
# initialize variables
|
||||||
TOP_LEVEL_NAME="niosII_tb"
|
TOP_LEVEL_NAME="niosII_tb"
|
||||||
|
|
|
@ -12,7 +12,7 @@
|
||||||
# or its authorized distributors. Please refer to the applicable
|
# or its authorized distributors. Please refer to the applicable
|
||||||
# agreement for further details.
|
# agreement for further details.
|
||||||
|
|
||||||
# ACDS 18.1 625 win32 2022.12.21.21:02:08
|
# ACDS 18.1 625 win32 2022.12.22.22:39:16
|
||||||
|
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# vcsmx - auto-generated simulation script
|
# vcsmx - auto-generated simulation script
|
||||||
|
@ -107,7 +107,7 @@
|
||||||
# within the Quartus project, and generate a unified
|
# within the Quartus project, and generate a unified
|
||||||
# script which supports all the Altera IP within the design.
|
# script which supports all the Altera IP within the design.
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# ACDS 18.1 625 win32 2022.12.21.21:02:08
|
# ACDS 18.1 625 win32 2022.12.22.22:39:16
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# initialize variables
|
# initialize variables
|
||||||
TOP_LEVEL_NAME="niosII_tb"
|
TOP_LEVEL_NAME="niosII_tb"
|
||||||
|
|
|
@ -1,12 +1,12 @@
|
||||||
# system info niosII_tb on 2022.12.21.21:02:06
|
# system info niosII_tb on 2022.12.22.22:39:13
|
||||||
system_info:
|
system_info:
|
||||||
name,value
|
name,value
|
||||||
DEVICE,EP4CE115F29C7
|
DEVICE,EP4CE115F29C7
|
||||||
DEVICE_FAMILY,Cyclone IV E
|
DEVICE_FAMILY,Cyclone IV E
|
||||||
GENERATION_ID,1671642093
|
GENERATION_ID,1671734322
|
||||||
#
|
#
|
||||||
#
|
#
|
||||||
# Files generated for niosII_tb on 2022.12.21.21:02:06
|
# Files generated for niosII_tb on 2022.12.22.22:39:13
|
||||||
files:
|
files:
|
||||||
filepath,kind,attributes,module,is_top
|
filepath,kind,attributes,module,is_top
|
||||||
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
|
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
|
||||||
|
|
|
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -7,163 +7,163 @@
|
||||||
00000230 T _start
|
00000230 T _start
|
||||||
00000244 t alt_after_alt_main
|
00000244 t alt_after_alt_main
|
||||||
00000248 T main
|
00000248 T main
|
||||||
00000334 T _puts_r
|
00000338 T _puts_r
|
||||||
000003f4 T puts
|
000003f8 T puts
|
||||||
00000408 T strlen
|
0000040c T strlen
|
||||||
000004a0 t __fp_unlock
|
000004a4 t __fp_unlock
|
||||||
000004a8 T _cleanup_r
|
000004ac T _cleanup_r
|
||||||
000004b4 t __sinit.part.1
|
000004b8 t __sinit.part.1
|
||||||
00000650 t __fp_lock
|
00000654 t __fp_lock
|
||||||
00000658 T __sfmoreglue
|
0000065c T __sfmoreglue
|
||||||
000006d0 T __sfp
|
000006d4 T __sfp
|
||||||
000007e8 T _cleanup
|
000007ec T _cleanup
|
||||||
00000800 T __sinit
|
00000804 T __sinit
|
||||||
00000810 T __sfp_lock_acquire
|
00000814 T __sfp_lock_acquire
|
||||||
00000814 T __sfp_lock_release
|
00000818 T __sfp_lock_release
|
||||||
00000818 T __sinit_lock_acquire
|
0000081c T __sinit_lock_acquire
|
||||||
0000081c T __sinit_lock_release
|
00000820 T __sinit_lock_release
|
||||||
00000820 T __fp_lock_all
|
00000824 T __fp_lock_all
|
||||||
00000838 T __fp_unlock_all
|
0000083c T __fp_unlock_all
|
||||||
00000850 T __sfvwrite_r
|
00000854 T __sfvwrite_r
|
||||||
00000d18 T _fwalk
|
00000d1c T _fwalk
|
||||||
00000ddc T _fwalk_reent
|
00000de0 T _fwalk_reent
|
||||||
00000ea0 T _malloc_r
|
00000ea4 T _malloc_r
|
||||||
000016ac T memchr
|
000016b0 T memchr
|
||||||
00001790 T memcpy
|
00001794 T memcpy
|
||||||
000018d8 T memmove
|
000018dc T memmove
|
||||||
00001a34 T memset
|
00001a38 T memset
|
||||||
00001b5c T _realloc_r
|
00001b60 T _realloc_r
|
||||||
000020c0 T _sbrk_r
|
000020c4 T _sbrk_r
|
||||||
00002114 T __sread
|
00002118 T __sread
|
||||||
00002168 T __seofread
|
0000216c T __seofread
|
||||||
00002170 T __swrite
|
00002174 T __swrite
|
||||||
000021ec T __sseek
|
000021f0 T __sseek
|
||||||
00002248 T __sclose
|
0000224c T __sclose
|
||||||
00002250 T _write_r
|
00002254 T _write_r
|
||||||
000022b0 T __swsetup_r
|
000022b4 T __swsetup_r
|
||||||
00002404 T _close_r
|
00002408 T _close_r
|
||||||
00002458 T _fclose_r
|
0000245c T _fclose_r
|
||||||
00002548 T fclose
|
0000254c T fclose
|
||||||
0000255c T __sflush_r
|
00002560 T __sflush_r
|
||||||
00002778 T _fflush_r
|
0000277c T _fflush_r
|
||||||
000027d4 T fflush
|
000027d8 T fflush
|
||||||
00002804 T _malloc_trim_r
|
00002808 T _malloc_trim_r
|
||||||
00002928 T _free_r
|
0000292c T _free_r
|
||||||
00002c38 T _lseek_r
|
00002c3c T _lseek_r
|
||||||
00002c98 T __smakebuf_r
|
00002c9c T __smakebuf_r
|
||||||
00002e54 T _read_r
|
00002e58 T _read_r
|
||||||
00002eb4 T _fstat_r
|
00002eb8 T _fstat_r
|
||||||
00002f10 T _isatty_r
|
00002f14 T _isatty_r
|
||||||
00002f64 T __divsi3
|
00002f68 T __divsi3
|
||||||
00002fe8 T __modsi3
|
00002fec T __modsi3
|
||||||
0000305c T __udivsi3
|
00003060 T __udivsi3
|
||||||
000030c0 T __umodsi3
|
000030c4 T __umodsi3
|
||||||
00003118 T __mulsi3
|
0000311c T __mulsi3
|
||||||
00003140 t alt_get_errno
|
00003144 t alt_get_errno
|
||||||
0000317c T close
|
00003180 T close
|
||||||
00003254 T alt_dcache_flush
|
00003258 T alt_dcache_flush
|
||||||
0000327c t alt_dev_null_write
|
00003280 t alt_dev_null_write
|
||||||
000032a8 t alt_get_errno
|
000032ac t alt_get_errno
|
||||||
000032e4 T fstat
|
000032e8 T fstat
|
||||||
0000339c t alt_get_errno
|
000033a0 t alt_get_errno
|
||||||
000033d8 T isatty
|
000033dc T isatty
|
||||||
00003484 t alt_get_errno
|
00003488 t alt_get_errno
|
||||||
000034c0 T lseek
|
000034c4 T lseek
|
||||||
0000359c T alt_main
|
000035a0 T alt_main
|
||||||
00003618 T __malloc_lock
|
0000361c T __malloc_lock
|
||||||
0000363c T __malloc_unlock
|
00003640 T __malloc_unlock
|
||||||
00003660 t alt_get_errno
|
00003664 t alt_get_errno
|
||||||
0000369c T read
|
000036a0 T read
|
||||||
000037a0 T alt_release_fd
|
000037a4 T alt_release_fd
|
||||||
00003824 T sbrk
|
00003828 T sbrk
|
||||||
000038d4 t alt_get_errno
|
000038d8 t alt_get_errno
|
||||||
00003910 T write
|
00003914 T write
|
||||||
00003a10 t alt_dev_reg
|
00003a14 t alt_dev_reg
|
||||||
00003a44 T alt_irq_init
|
00003a48 T alt_irq_init
|
||||||
00003a7c T alt_sys_init
|
00003a80 T alt_sys_init
|
||||||
00003adc T altera_avalon_jtag_uart_read_fd
|
00003ae0 T altera_avalon_jtag_uart_read_fd
|
||||||
00003b3c T altera_avalon_jtag_uart_write_fd
|
00003b40 T altera_avalon_jtag_uart_write_fd
|
||||||
00003b9c T altera_avalon_jtag_uart_close_fd
|
00003ba0 T altera_avalon_jtag_uart_close_fd
|
||||||
00003bec T altera_avalon_jtag_uart_ioctl_fd
|
00003bf0 T altera_avalon_jtag_uart_ioctl_fd
|
||||||
00003c40 T altera_avalon_jtag_uart_init
|
00003c44 T altera_avalon_jtag_uart_init
|
||||||
00003d00 t altera_avalon_jtag_uart_irq
|
00003d04 t altera_avalon_jtag_uart_irq
|
||||||
00003f0c t altera_avalon_jtag_uart_timeout
|
00003f10 t altera_avalon_jtag_uart_timeout
|
||||||
00003fac T altera_avalon_jtag_uart_close
|
00003fb0 T altera_avalon_jtag_uart_close
|
||||||
00004014 T altera_avalon_jtag_uart_ioctl
|
00004018 T altera_avalon_jtag_uart_ioctl
|
||||||
00004104 T altera_avalon_jtag_uart_read
|
00004108 T altera_avalon_jtag_uart_read
|
||||||
00004320 T altera_avalon_jtag_uart_write
|
00004324 T altera_avalon_jtag_uart_write
|
||||||
00004544 t alt_avalon_timer_sc_irq
|
00004548 t alt_avalon_timer_sc_irq
|
||||||
000045bc T alt_avalon_timer_sc_init
|
000045c0 T alt_avalon_timer_sc_init
|
||||||
00004638 T alt_alarm_start
|
0000463c T alt_alarm_start
|
||||||
00004764 t alt_get_errno
|
00004768 t alt_get_errno
|
||||||
000047a0 T alt_dev_llist_insert
|
000047a4 T alt_dev_llist_insert
|
||||||
00004844 T _do_ctors
|
00004848 T _do_ctors
|
||||||
000048a4 T _do_dtors
|
000048a8 T _do_dtors
|
||||||
00004904 T alt_ic_isr_register
|
00004908 T alt_ic_isr_register
|
||||||
00004954 T alt_ic_irq_enable
|
00004958 T alt_ic_irq_enable
|
||||||
000049dc T alt_ic_irq_disable
|
000049e0 T alt_ic_irq_disable
|
||||||
00004a68 T alt_ic_irq_enabled
|
00004a6c T alt_ic_irq_enabled
|
||||||
00004ab4 T alt_iic_isr_register
|
00004ab8 T alt_iic_isr_register
|
||||||
00004ba4 t alt_open_fd
|
00004ba8 t alt_open_fd
|
||||||
00004c88 T alt_io_redirect
|
00004c8c T alt_io_redirect
|
||||||
00004d04 t alt_get_errno
|
00004d08 t alt_get_errno
|
||||||
00004d40 t alt_file_locked
|
00004d44 t alt_file_locked
|
||||||
00004e2c T open
|
00004e30 T open
|
||||||
00004f88 T alt_alarm_stop
|
00004f8c T alt_alarm_stop
|
||||||
00005024 T alt_tick
|
00005028 T alt_tick
|
||||||
0000512c T altera_nios2_gen2_irq_init
|
00005130 T altera_nios2_gen2_irq_init
|
||||||
00005150 T alt_find_dev
|
00005154 T alt_find_dev
|
||||||
000051e0 T alt_find_file
|
000051e4 T alt_find_file
|
||||||
000052e8 T alt_get_fd
|
000052ec T alt_get_fd
|
||||||
000053ac T alt_exception_cause_generated_bad_addr
|
000053b0 T alt_exception_cause_generated_bad_addr
|
||||||
00005448 T atexit
|
0000544c T atexit
|
||||||
0000545c T exit
|
00005460 T exit
|
||||||
00005494 T memcmp
|
00005498 T memcmp
|
||||||
00005510 T __register_exitproc
|
00005514 T __register_exitproc
|
||||||
00005628 T __call_exitprocs
|
0000562c T __call_exitprocs
|
||||||
000057a8 T _exit
|
000057ac T _exit
|
||||||
000057dc A __CTOR_END__
|
000057e0 A __CTOR_END__
|
||||||
000057dc A __CTOR_LIST__
|
000057e0 A __CTOR_LIST__
|
||||||
000057dc A __DTOR_END__
|
000057e0 A __DTOR_END__
|
||||||
000057dc A __DTOR_LIST__
|
000057e0 A __DTOR_LIST__
|
||||||
000057dc R divisors
|
000057e0 R divisors
|
||||||
00005858 g impure_data
|
0000585c g impure_data
|
||||||
00005c7c G __malloc_av_
|
00005c80 G __malloc_av_
|
||||||
00006084 G alt_dev_null
|
00006088 G alt_dev_null
|
||||||
000060ac G alt_fd_list
|
000060b0 G alt_fd_list
|
||||||
0000622c g jtag_uart
|
00006230 g jtag_uart
|
||||||
0000728c G _global_impure_ptr
|
00007290 G _global_impure_ptr
|
||||||
00007290 G _impure_ptr
|
00007294 G _impure_ptr
|
||||||
00007294 G __malloc_sbrk_base
|
00007298 G __malloc_sbrk_base
|
||||||
00007298 G __malloc_trim_threshold
|
0000729c G __malloc_trim_threshold
|
||||||
0000729c G alt_fs_list
|
000072a0 G alt_fs_list
|
||||||
000072a4 G alt_dev_list
|
000072a8 G alt_dev_list
|
||||||
000072ac G alt_max_fd
|
000072b0 G alt_max_fd
|
||||||
000072b0 G alt_errno
|
000072b4 G alt_errno
|
||||||
000072b4 g heap_end
|
000072b8 g heap_end
|
||||||
000072b8 G alt_priority_mask
|
000072bc G alt_priority_mask
|
||||||
000072bc G alt_alarm_list
|
000072c0 G alt_alarm_list
|
||||||
000072c4 A __bss_start
|
000072c8 A __bss_start
|
||||||
000072c4 B __malloc_max_total_mem
|
000072c8 B __malloc_max_total_mem
|
||||||
000072c4 A _edata
|
000072c8 A _edata
|
||||||
000072c8 B __malloc_max_sbrked_mem
|
000072cc B __malloc_max_sbrked_mem
|
||||||
000072cc B __malloc_top_pad
|
000072d0 B __malloc_top_pad
|
||||||
000072d0 B errno
|
000072d4 B errno
|
||||||
000072d4 B alt_argc
|
000072d8 B alt_argc
|
||||||
000072d8 B alt_argv
|
000072dc B alt_argv
|
||||||
000072dc B alt_envp
|
000072e0 B alt_envp
|
||||||
000072e0 B alt_irq_active
|
000072e4 B alt_irq_active
|
||||||
000072e4 B _alt_tick_rate
|
000072e8 B _alt_tick_rate
|
||||||
000072e8 B _alt_nticks
|
000072ec B _alt_nticks
|
||||||
000072ec B alt_instruction_exception_handler
|
000072f0 B alt_instruction_exception_handler
|
||||||
000072f0 B __malloc_current_mallinfo
|
000072f4 B __malloc_current_mallinfo
|
||||||
00007318 B alt_irq
|
0000731c B alt_irq
|
||||||
00007418 A __alt_heap_start
|
0000741c A __alt_heap_start
|
||||||
00007418 A __alt_stack_base
|
0000741c A __alt_stack_base
|
||||||
00007418 A __bss_end
|
0000741c A __bss_end
|
||||||
00007418 A _end
|
0000741c A _end
|
||||||
00007418 A end
|
0000741c A end
|
||||||
0000f28c A _gp
|
0000f290 A _gp
|
||||||
00020000 A __alt_data_end
|
00020000 A __alt_data_end
|
||||||
00020000 A __alt_heap_limit
|
00020000 A __alt_heap_limit
|
||||||
00020000 A __alt_stack_pointer
|
00020000 A __alt_stack_pointer
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -6,10 +6,10 @@
|
||||||
#define TIME_SETS 4
|
#define TIME_SETS 4
|
||||||
#define TIME_STATES 4
|
#define TIME_STATES 4
|
||||||
const alt_u32 divisors[TIME_SETS][TIME_STATES] = {
|
const alt_u32 divisors[TIME_SETS][TIME_STATES] = {
|
||||||
{0x100000, 0x100000, 0x50000, 0x10000},
|
{0x00000010, 0x00000010, 0x00000005, 0x00000010},
|
||||||
{0x100000, 0x200000, 0x100000, 0x10000},
|
{0x00000010, 0x00000020, 0x00000010, 0x00000010},
|
||||||
{0x150000, 0x250000, 0x200000, 0x10000},
|
{0x000000f0, 0x000000f0, 0x000000f0, 0x00000010},
|
||||||
{0x250000, 0x250000, 0x250000, 0x10000}
|
{0x000000fa, 0x000000f0, 0x000000f0, 0x00000010}
|
||||||
};
|
};
|
||||||
|
|
||||||
int main()
|
int main()
|
||||||
|
@ -20,14 +20,12 @@ int main()
|
||||||
|
|
||||||
//program divisors
|
//program divisors
|
||||||
p = (alt_u32*) SEM_RAM_SLAVE_BASE;
|
p = (alt_u32*) SEM_RAM_SLAVE_BASE;
|
||||||
for (i=0; i<TIME_SETS; i++)
|
for (i = 0; i < TIME_SETS; i++) {
|
||||||
{
|
|
||||||
tmp = 0;
|
tmp = 0;
|
||||||
for (j=TIME_STATES; j>0; j--)
|
for (j = TIME_STATES; j > 0; j--) {
|
||||||
{
|
tmp = (tmp << 32) | divisors[i][j - 1];
|
||||||
tmp = (tmp << 8) | divisors[i][j-1];
|
|
||||||
}
|
}
|
||||||
*p=tmp;
|
*p = tmp;
|
||||||
p++;
|
p++;
|
||||||
}
|
}
|
||||||
//since we use pointers (cached data access) to write divisor RAM,
|
//since we use pointers (cached data access) to write divisor RAM,
|
||||||
|
|
Binary file not shown.
|
@ -2,8 +2,8 @@
|
||||||
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
|
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
|
||||||
<BspType>hal</BspType>
|
<BspType>hal</BspType>
|
||||||
<BspVersion>default</BspVersion>
|
<BspVersion>default</BspVersion>
|
||||||
<BspGeneratedTimeStamp>22.12.2022 17:21:19</BspGeneratedTimeStamp>
|
<BspGeneratedTimeStamp>22.12.2022 22:44:16</BspGeneratedTimeStamp>
|
||||||
<BspGeneratedUnixTimeStamp>1671715279678</BspGeneratedUnixTimeStamp>
|
<BspGeneratedUnixTimeStamp>1671734657095</BspGeneratedUnixTimeStamp>
|
||||||
<BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation>
|
<BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation>
|
||||||
<BspSettingsFile>settings.bsp</BspSettingsFile>
|
<BspSettingsFile>settings.bsp</BspSettingsFile>
|
||||||
<SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile>
|
<SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile>
|
||||||
|
@ -904,27 +904,27 @@
|
||||||
<addressSpan>131072</addressSpan>
|
<addressSpan>131072</addressSpan>
|
||||||
<attributes>memory</attributes>
|
<attributes>memory</attributes>
|
||||||
</MemoryMap>
|
</MemoryMap>
|
||||||
|
<MemoryMap>
|
||||||
|
<slaveDescriptor>sem_ram_slave</slaveDescriptor>
|
||||||
|
<addressRange>0x00021000 - 0x0002103F</addressRange>
|
||||||
|
<addressSpan>64</addressSpan>
|
||||||
|
<attributes/>
|
||||||
|
</MemoryMap>
|
||||||
<MemoryMap>
|
<MemoryMap>
|
||||||
<slaveDescriptor>sys_clk_timer</slaveDescriptor>
|
<slaveDescriptor>sys_clk_timer</slaveDescriptor>
|
||||||
<addressRange>0x00021000 - 0x0002101F</addressRange>
|
<addressRange>0x00021040 - 0x0002105F</addressRange>
|
||||||
<addressSpan>32</addressSpan>
|
<addressSpan>32</addressSpan>
|
||||||
<attributes>timer</attributes>
|
<attributes>timer</attributes>
|
||||||
</MemoryMap>
|
</MemoryMap>
|
||||||
<MemoryMap>
|
|
||||||
<slaveDescriptor>sem_ram_slave</slaveDescriptor>
|
|
||||||
<addressRange>0x00021020 - 0x0002102F</addressRange>
|
|
||||||
<addressSpan>16</addressSpan>
|
|
||||||
<attributes/>
|
|
||||||
</MemoryMap>
|
|
||||||
<MemoryMap>
|
<MemoryMap>
|
||||||
<slaveDescriptor>sem_ctl_slave</slaveDescriptor>
|
<slaveDescriptor>sem_ctl_slave</slaveDescriptor>
|
||||||
<addressRange>0x00021030 - 0x00021037</addressRange>
|
<addressRange>0x00021060 - 0x00021067</addressRange>
|
||||||
<addressSpan>8</addressSpan>
|
<addressSpan>8</addressSpan>
|
||||||
<attributes/>
|
<attributes/>
|
||||||
</MemoryMap>
|
</MemoryMap>
|
||||||
<MemoryMap>
|
<MemoryMap>
|
||||||
<slaveDescriptor>jtag_uart</slaveDescriptor>
|
<slaveDescriptor>jtag_uart</slaveDescriptor>
|
||||||
<addressRange>0x00021038 - 0x0002103F</addressRange>
|
<addressRange>0x00021068 - 0x0002106F</addressRange>
|
||||||
<addressSpan>8</addressSpan>
|
<addressSpan>8</addressSpan>
|
||||||
<attributes>printable</attributes>
|
<attributes>printable</attributes>
|
||||||
</MemoryMap>
|
</MemoryMap>
|
||||||
|
|
|
@ -22,10 +22,10 @@
|
||||||
<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
|
<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr mode="wrap">
|
<tr mode="wrap">
|
||||||
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>22.12.2022 17:21:19</td>
|
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>22.12.2022 22:44:16</td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr mode="wrap">
|
<tr mode="wrap">
|
||||||
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671715279678</td>
|
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671734657095</td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr mode="wrap">
|
<tr mode="wrap">
|
||||||
<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td>
|
<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td>
|
||||||
|
@ -38,16 +38,16 @@
|
||||||
<th align="left" width="20%">Slave Descriptor</th><th align="left" width="40%">Address Range</th><th align="left" width="20%">Size</th><th align="left" width="20%">Attributes</th>
|
<th align="left" width="20%">Slave Descriptor</th><th align="left" width="40%">Address Range</th><th align="left" width="20%">Size</th><th align="left" width="20%">Attributes</th>
|
||||||
</tr>
|
</tr>
|
||||||
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
|
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
|
||||||
<td>jtag_uart</td><td>0x00021038 - 0x0002103F</td><td>8</td><td class="listing">printable</td>
|
<td>jtag_uart</td><td>0x00021068 - 0x0002106F</td><td>8</td><td class="listing">printable</td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
|
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
|
||||||
<td>sem_ctl_slave</td><td>0x00021030 - 0x00021037</td><td>8</td><td class="listing"> </td>
|
<td>sem_ctl_slave</td><td>0x00021060 - 0x00021067</td><td>8</td><td class="listing"> </td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
|
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
|
||||||
<td>sem_ram_slave</td><td>0x00021020 - 0x0002102F</td><td>16</td><td class="listing"> </td>
|
<td>sys_clk_timer</td><td>0x00021040 - 0x0002105F</td><td>32</td><td class="listing">timer</td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
|
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
|
||||||
<td>sys_clk_timer</td><td>0x00021000 - 0x0002101F</td><td>32</td><td class="listing">timer</td>
|
<td>sem_ram_slave</td><td>0x00021000 - 0x0002103F</td><td>64</td><td class="listing"> </td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
|
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
|
||||||
<td>mem</td><td>0x00000000 - 0x0001FFFF</td><td>131072</td><td class="listing">memory</td>
|
<td>mem</td><td>0x00000000 - 0x0001FFFF</td><td>131072</td><td class="listing">memory</td>
|
||||||
|
|
|
@ -4,7 +4,7 @@
|
||||||
* Machine generated for CPU 'cpu' in SOPC Builder design 'niosII'
|
* Machine generated for CPU 'cpu' in SOPC Builder design 'niosII'
|
||||||
* SOPC Builder design path: ../../niosII.sopcinfo
|
* SOPC Builder design path: ../../niosII.sopcinfo
|
||||||
*
|
*
|
||||||
* Generated: Mon Oct 24 11:12:11 MSK 2022
|
* Generated: Thu Dec 22 22:44:18 MSK 2022
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -156,19 +156,19 @@
|
||||||
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
|
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
|
||||||
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
|
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
|
||||||
#define ALT_STDERR "/dev/jtag_uart"
|
#define ALT_STDERR "/dev/jtag_uart"
|
||||||
#define ALT_STDERR_BASE 0x21038
|
#define ALT_STDERR_BASE 0x21068
|
||||||
#define ALT_STDERR_DEV jtag_uart
|
#define ALT_STDERR_DEV jtag_uart
|
||||||
#define ALT_STDERR_IS_JTAG_UART
|
#define ALT_STDERR_IS_JTAG_UART
|
||||||
#define ALT_STDERR_PRESENT
|
#define ALT_STDERR_PRESENT
|
||||||
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
|
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
|
||||||
#define ALT_STDIN "/dev/jtag_uart"
|
#define ALT_STDIN "/dev/jtag_uart"
|
||||||
#define ALT_STDIN_BASE 0x21038
|
#define ALT_STDIN_BASE 0x21068
|
||||||
#define ALT_STDIN_DEV jtag_uart
|
#define ALT_STDIN_DEV jtag_uart
|
||||||
#define ALT_STDIN_IS_JTAG_UART
|
#define ALT_STDIN_IS_JTAG_UART
|
||||||
#define ALT_STDIN_PRESENT
|
#define ALT_STDIN_PRESENT
|
||||||
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
|
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
|
||||||
#define ALT_STDOUT "/dev/jtag_uart"
|
#define ALT_STDOUT "/dev/jtag_uart"
|
||||||
#define ALT_STDOUT_BASE 0x21038
|
#define ALT_STDOUT_BASE 0x21068
|
||||||
#define ALT_STDOUT_DEV jtag_uart
|
#define ALT_STDOUT_DEV jtag_uart
|
||||||
#define ALT_STDOUT_IS_JTAG_UART
|
#define ALT_STDOUT_IS_JTAG_UART
|
||||||
#define ALT_STDOUT_PRESENT
|
#define ALT_STDOUT_PRESENT
|
||||||
|
@ -193,7 +193,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart
|
#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart
|
||||||
#define JTAG_UART_BASE 0x21038
|
#define JTAG_UART_BASE 0x21068
|
||||||
#define JTAG_UART_IRQ 1
|
#define JTAG_UART_IRQ 1
|
||||||
#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
|
#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
|
||||||
#define JTAG_UART_NAME "/dev/jtag_uart"
|
#define JTAG_UART_NAME "/dev/jtag_uart"
|
||||||
|
@ -240,7 +240,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define ALT_MODULE_CLASS_sem_ctl_slave sem
|
#define ALT_MODULE_CLASS_sem_ctl_slave sem
|
||||||
#define SEM_CTL_SLAVE_BASE 0x21030
|
#define SEM_CTL_SLAVE_BASE 0x21060
|
||||||
#define SEM_CTL_SLAVE_IRQ -1
|
#define SEM_CTL_SLAVE_IRQ -1
|
||||||
#define SEM_CTL_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1
|
#define SEM_CTL_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1
|
||||||
#define SEM_CTL_SLAVE_NAME "/dev/sem_ctl_slave"
|
#define SEM_CTL_SLAVE_NAME "/dev/sem_ctl_slave"
|
||||||
|
@ -254,11 +254,11 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define ALT_MODULE_CLASS_sem_ram_slave sem
|
#define ALT_MODULE_CLASS_sem_ram_slave sem
|
||||||
#define SEM_RAM_SLAVE_BASE 0x21020
|
#define SEM_RAM_SLAVE_BASE 0x21000
|
||||||
#define SEM_RAM_SLAVE_IRQ -1
|
#define SEM_RAM_SLAVE_IRQ -1
|
||||||
#define SEM_RAM_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1
|
#define SEM_RAM_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1
|
||||||
#define SEM_RAM_SLAVE_NAME "/dev/sem_ram_slave"
|
#define SEM_RAM_SLAVE_NAME "/dev/sem_ram_slave"
|
||||||
#define SEM_RAM_SLAVE_SPAN 16
|
#define SEM_RAM_SLAVE_SPAN 64
|
||||||
#define SEM_RAM_SLAVE_TYPE "sem"
|
#define SEM_RAM_SLAVE_TYPE "sem"
|
||||||
|
|
||||||
|
|
||||||
|
@ -269,7 +269,7 @@
|
||||||
|
|
||||||
#define ALT_MODULE_CLASS_sys_clk_timer altera_avalon_timer
|
#define ALT_MODULE_CLASS_sys_clk_timer altera_avalon_timer
|
||||||
#define SYS_CLK_TIMER_ALWAYS_RUN 0
|
#define SYS_CLK_TIMER_ALWAYS_RUN 0
|
||||||
#define SYS_CLK_TIMER_BASE 0x21000
|
#define SYS_CLK_TIMER_BASE 0x21040
|
||||||
#define SYS_CLK_TIMER_COUNTER_SIZE 32
|
#define SYS_CLK_TIMER_COUNTER_SIZE 32
|
||||||
#define SYS_CLK_TIMER_FIXED_PERIOD 0
|
#define SYS_CLK_TIMER_FIXED_PERIOD 0
|
||||||
#define SYS_CLK_TIMER_FREQ 50000000
|
#define SYS_CLK_TIMER_FREQ 50000000
|
||||||
|
|
Loading…
Reference in New Issue