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ram32ok

This commit is contained in:
Ivan I. Ovchinnikov 2022-12-22 22:27:05 +03:00
parent 6291090406
commit 881e124d27
32 changed files with 13206 additions and 13192 deletions
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2
HDL/dec.sv
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@ -10,7 +10,7 @@ module dec
output logic [31:0] ctl_rddata, output logic [31:0] ctl_rddata,
//memory slave //memory slave
input logic ram_wr, input logic ram_wr,
input logic [1:0] ram_addr, input logic [3:0] ram_addr,
input logic [31:0] ram_wrdata, input logic [31:0] ram_wrdata,
//external ports //external ports
input logic train, input logic train,

BIN
Testbench/dec/dec.qws
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Binary file not shown.

6
Top/Semafor_hw.tcl
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@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 18.1 # TCL File Generated by Component Editor 18.1
# Wed Dec 21 21:00:10 MSK 2022 # Thu Dec 22 22:35:53 MSK 2022
# DO NOT MODIFY # DO NOT MODIFY
# #
# sem "Semafor" v1.1 # sem "Semafor" v1.1
# 2022.12.21.21:00:10 # 2022.12.22.22:35:53
# #
# #
@ -163,7 +163,7 @@ set_interface_property ram_slave CMSIS_SVD_VARIABLES ""
set_interface_property ram_slave SVD_ADDRESS_GROUP "" set_interface_property ram_slave SVD_ADDRESS_GROUP ""
add_interface_port ram_slave ram_wr write Input 1 add_interface_port ram_slave ram_wr write Input 1
add_interface_port ram_slave ram_addr address Input 2 add_interface_port ram_slave ram_addr address Input 4
add_interface_port ram_slave ram_wrdata writedata Input 32 add_interface_port ram_slave ram_wrdata writedata Input 32
set_interface_assignment ram_slave embeddedsw.configuration.isFlash 0 set_interface_assignment ram_slave embeddedsw.configuration.isFlash 0
set_interface_assignment ram_slave embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment ram_slave embeddedsw.configuration.isMemoryDevice 0

4
Top/Semafor_hw.tcl~
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@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 18.1 # TCL File Generated by Component Editor 18.1
# Mon Dec 19 20:23:41 MSK 2022 # Wed Dec 21 21:00:10 MSK 2022
# DO NOT MODIFY # DO NOT MODIFY
# #
# sem "Semafor" v1.1 # sem "Semafor" v1.1
# 2022.12.19.20:23:40 # 2022.12.21.21:00:10
# #
# #

26
Top/niosII.qsys
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@ -45,7 +45,7 @@
{ {
datum baseAddress datum baseAddress
{ {
value = "135224"; value = "135272";
type = "String"; type = "String";
} }
} }
@ -97,6 +97,14 @@
type = "String"; type = "String";
} }
} }
element niosII
{
datum _originalDeviceFamily
{
value = "Cyclone IV E";
type = "String";
}
}
element sem element sem
{ {
datum _sortIndex datum _sortIndex
@ -109,7 +117,7 @@
{ {
datum baseAddress datum baseAddress
{ {
value = "135216"; value = "135264";
type = "String"; type = "String";
} }
} }
@ -117,7 +125,7 @@
{ {
datum baseAddress datum baseAddress
{ {
value = "135200"; value = "135168";
type = "String"; type = "String";
} }
} }
@ -133,7 +141,7 @@
{ {
datum baseAddress datum baseAddress
{ {
value = "135168"; value = "135232";
type = "String"; type = "String";
} }
} }
@ -187,7 +195,7 @@
<parameter name="dataAddrWidth" value="18" /> <parameter name="dataAddrWidth" value="18" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" /> <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" /> <parameter name="dataMasterHighPerformanceMapParam" value="" />
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter> <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" /> <parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" /> <parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" /> <parameter name="data_master_paddr_base" value="0" />
@ -421,7 +429,7 @@
start="cpu.data_master" start="cpu.data_master"
end="jtag_uart.avalon_jtag_slave"> end="jtag_uart.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00021038" /> <parameter name="baseAddress" value="0x00021068" />
<parameter name="defaultConnection" value="false" /> <parameter name="defaultConnection" value="false" />
</connection> </connection>
<connection <connection
@ -430,7 +438,7 @@
start="cpu.data_master" start="cpu.data_master"
end="sem.ctl_slave"> end="sem.ctl_slave">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00021030" /> <parameter name="baseAddress" value="0x00021060" />
<parameter name="defaultConnection" value="false" /> <parameter name="defaultConnection" value="false" />
</connection> </connection>
<connection <connection
@ -448,7 +456,7 @@
start="cpu.data_master" start="cpu.data_master"
end="sem.ram_slave"> end="sem.ram_slave">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00021020" /> <parameter name="baseAddress" value="0x00021000" />
<parameter name="defaultConnection" value="false" /> <parameter name="defaultConnection" value="false" />
</connection> </connection>
<connection <connection
@ -457,7 +465,7 @@
start="cpu.data_master" start="cpu.data_master"
end="sys_clk_timer.s1"> end="sys_clk_timer.s1">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00021000" /> <parameter name="baseAddress" value="0x00021040" />
<parameter name="defaultConnection" value="false" /> <parameter name="defaultConnection" value="false" />
</connection> </connection>
<connection kind="avalon" version="18.1" start="cpu.data_master" end="mem.s2"> <connection kind="avalon" version="18.1" start="cpu.data_master" end="mem.s2">

28
Top/niosII.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS"> <EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) --> <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2022.12.22.17:19:01 --> <!-- 2022.12.22.22:38:31 -->
<!-- A collection of modules and connections --> <!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID"> <parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type> <type>java.lang.Integer</type>
<value>1671715140</value> <value>1671734311</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -2034,7 +2034,7 @@ the requested settings for a module instance. -->
</parameter> </parameter>
<parameter name="dataSlaveMapParam"> <parameter name="dataSlaveMapParam">
<type>java.lang.String</type> <type>java.lang.String</type>
<value><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></value> <value><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -2705,7 +2705,7 @@ parameters are a RESULT of the module parameters. -->
<moduleName>jtag_uart</moduleName> <moduleName>jtag_uart</moduleName>
<slaveName>avalon_jtag_slave</slaveName> <slaveName>avalon_jtag_slave</slaveName>
<name>jtag_uart.avalon_jtag_slave</name> <name>jtag_uart.avalon_jtag_slave</name>
<baseAddress>135224</baseAddress> <baseAddress>135272</baseAddress>
<span>8</span> <span>8</span>
</memoryBlock> </memoryBlock>
<memoryBlock> <memoryBlock>
@ -2713,7 +2713,7 @@ parameters are a RESULT of the module parameters. -->
<moduleName>sem</moduleName> <moduleName>sem</moduleName>
<slaveName>ctl_slave</slaveName> <slaveName>ctl_slave</slaveName>
<name>sem.ctl_slave</name> <name>sem.ctl_slave</name>
<baseAddress>135216</baseAddress> <baseAddress>135264</baseAddress>
<span>8</span> <span>8</span>
</memoryBlock> </memoryBlock>
<memoryBlock> <memoryBlock>
@ -2729,15 +2729,15 @@ parameters are a RESULT of the module parameters. -->
<moduleName>sem</moduleName> <moduleName>sem</moduleName>
<slaveName>ram_slave</slaveName> <slaveName>ram_slave</slaveName>
<name>sem.ram_slave</name> <name>sem.ram_slave</name>
<baseAddress>135200</baseAddress> <baseAddress>135168</baseAddress>
<span>16</span> <span>64</span>
</memoryBlock> </memoryBlock>
<memoryBlock> <memoryBlock>
<isBridge>false</isBridge> <isBridge>false</isBridge>
<moduleName>sys_clk_timer</moduleName> <moduleName>sys_clk_timer</moduleName>
<slaveName>s1</slaveName> <slaveName>s1</slaveName>
<name>sys_clk_timer.s1</name> <name>sys_clk_timer.s1</name>
<baseAddress>135168</baseAddress> <baseAddress>135232</baseAddress>
<span>32</span> <span>32</span>
</memoryBlock> </memoryBlock>
<memoryBlock> <memoryBlock>
@ -6172,7 +6172,7 @@ parameters are a RESULT of the module parameters. -->
</parameter> </parameter>
<parameter name="addressSpan"> <parameter name="addressSpan">
<type>java.math.BigInteger</type> <type>java.math.BigInteger</type>
<value>16</value> <value>64</value>
<derived>true</derived> <derived>true</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -6477,7 +6477,7 @@ parameters are a RESULT of the module parameters. -->
<port> <port>
<name>ram_addr</name> <name>ram_addr</name>
<direction>Input</direction> <direction>Input</direction>
<width>2</width> <width>4</width>
<role>address</role> <role>address</role>
</port> </port>
<port> <port>
@ -7349,7 +7349,7 @@ parameters are a RESULT of the module parameters. -->
</parameter> </parameter>
<parameter name="baseAddress"> <parameter name="baseAddress">
<type>java.math.BigInteger</type> <type>java.math.BigInteger</type>
<value>0x00021038</value> <value>0x00021068</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>
@ -7400,7 +7400,7 @@ parameters are a RESULT of the module parameters. -->
</parameter> </parameter>
<parameter name="baseAddress"> <parameter name="baseAddress">
<type>java.math.BigInteger</type> <type>java.math.BigInteger</type>
<value>0x00021030</value> <value>0x00021060</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>
@ -7502,7 +7502,7 @@ parameters are a RESULT of the module parameters. -->
</parameter> </parameter>
<parameter name="baseAddress"> <parameter name="baseAddress">
<type>java.math.BigInteger</type> <type>java.math.BigInteger</type>
<value>0x00021020</value> <value>0x00021000</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>
@ -7553,7 +7553,7 @@ parameters are a RESULT of the module parameters. -->
</parameter> </parameter>
<parameter name="baseAddress"> <parameter name="baseAddress">
<type>java.math.BigInteger</type> <type>java.math.BigInteger</type>
<value>0x00021000</value> <value>0x00021040</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>

16
Top/niosII/niosII.html
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@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table> </table>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">2022.12.21.21:02:26</td> <td class="l">2022.12.22.22:37:23</td>
<td class="r">Datasheet</td> <td class="r">Datasheet</td>
</tr> </tr>
</table> </table>
@ -144,7 +144,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="slaveb">avalon_jtag_slave&#160;</td> <td class="slaveb">avalon_jtag_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021038</td> <td class="addr"><span style="color:#989898">0x</span>00021068</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
<tr> <tr>
@ -175,12 +175,12 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="slavem">ctl_slave&#160;</td> <td class="slavem">ctl_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021030</td> <td class="addr"><span style="color:#989898">0x</span>00021060</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
<tr> <tr>
<td class="slavem">ram_slave&#160;</td> <td class="slavem">ram_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021020</td> <td class="addr"><span style="color:#989898">0x</span>00021000</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
<tr> <tr>
@ -193,7 +193,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="slaveb">s1&#160;</td> <td class="slaveb">s1&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021000</td> <td class="addr"><span style="color:#989898">0x</span>00021040</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
</table> </table>
@ -1107,7 +1107,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">dataSlaveMapParam</td> <td class="parametername">dataSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /&gt;&lt;slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td> <td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">tightlyCoupledDataMaster0MapParam</td> <td class="parametername">tightlyCoupledDataMaster0MapParam</td>
@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</div> </div>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">generation took 0,00 seconds</td> <td class="l">generation took 0,01 seconds</td>
<td class="r">rendering took 0,05 seconds</td> <td class="r">rendering took 0,08 seconds</td>
</tr> </tr>
</table> </table>
</body> </body>

284
Top/niosII/niosII.xml
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36
Top/niosII/synthesis/niosII.debuginfo
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20
Top/niosII/synthesis/niosII.qip
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@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1" set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1"
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys" set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"] set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"]
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671642146" set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671734242"
set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"] set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"]
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"] set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"]
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"] set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"]
@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTY0MjE0Ng==::QXV0byBHRU5FUkFUSU9OX0lE" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTczNDI0Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U=" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U="
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@ -365,11 +365,11 @@ set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ==" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_VERSION "MTguMQ=="
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MywwLDYsNSw0LDE=::RGVzdGluYXRpb24gSUQ=" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MywwLDUsNiw0LDE=::RGVzdGluYXRpb24gSUQ="
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MTAwMDAwLDAwMDEwMCwwMTAwMDAsMDAxMDAwLDAwMDAxMCwwMDAwMDE=::QmluYXJ5IENoYW5uZWwgU3RyaW5n" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MTAwMDAwLDAwMDEwMCwwMDEwMDAsMDEwMDAwLDAwMDAxMCwwMDAwMDE=::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxib3RoLGJvdGgsd3JpdGUsYm90aCxib3Ro::VHlwZSBvZiBUcmFuc2FjdGlvbg==" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxib3RoLHdyaXRlLGJvdGgsYm90aCxib3Ro::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgwLDB4MjA4MDAsMHgyMTAwMCwweDIxMDIwLDB4MjEwMzAsMHgyMTAzOA==::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgwLDB4MjA4MDAsMHgyMTAwMCwweDIxMDQwLDB4MjEwNjAsMHgyMTA2OA==::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgyMDAwMCwweDIxMDAwLDB4MjEwMjAsMHgyMTAzMCwweDIxMDM4LDB4MjEwNDA=::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ==" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgyMDAwMCwweDIxMDAwLDB4MjEwNDAsMHgyMTA2MCwweDIxMDY4LDB4MjEwNzA=::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwxLDEsMSwxLDE=::Tm9uLXNlY3VyZWQgdGFncw==" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwxLDEsMSwxLDE=::Tm9uLXNlY3VyZWQgdGFncw=="
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCwwLDAsMCwwLDA=::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM=" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCwwLDAsMCwwLDA=::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCwwLDAsMCwwLDA=::U2VjdXJlZCByYW5nZSBwYWlycw==" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCwwLDAsMCwwLDA=::U2VjdXJlZCByYW5nZSBwYWlycw=="
@ -383,7 +383,7 @@ set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg=" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NTc=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg=" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::OTQ=::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg=" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::Nw==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MzoxMDAwMDA6MHgwOjB4MjAwMDA6Ym90aDoxOjA6MDoxLDA6MDAwMTAwOjB4MjA4MDA6MHgyMTAwMDpib3RoOjE6MDowOjEsNjowMTAwMDA6MHgyMTAwMDoweDIxMDIwOmJvdGg6MTowOjA6MSw1OjAwMTAwMDoweDIxMDIwOjB4MjEwMzA6d3JpdGU6MTowOjA6MSw0OjAwMDAxMDoweDIxMDMwOjB4MjEwMzg6Ym90aDoxOjA6MDoxLDE6MDAwMDAxOjB4MjEwMzg6MHgyMTA0MDpib3RoOjE6MDowOjE=::U0xBVkVTX0lORk8=" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MzoxMDAwMDA6MHgwOjB4MjAwMDA6Ym90aDoxOjA6MDoxLDA6MDAwMTAwOjB4MjA4MDA6MHgyMTAwMDpib3RoOjE6MDowOjEsNTowMDEwMDA6MHgyMTAwMDoweDIxMDQwOndyaXRlOjE6MDowOjEsNjowMTAwMDA6MHgyMTA0MDoweDIxMDYwOmJvdGg6MTowOjA6MSw0OjAwMDAxMDoweDIxMDYwOjB4MjEwNjg6Ym90aDoxOjA6MDoxLDE6MDAwMDAxOjB4MjEwNjg6MHgyMTA3MDpib3RoOjE6MDowOjE=::U0xBVkVTX0lORk8="
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MA==::RGVjb2RlciB0eXBl" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MA==::RGVjb2RlciB0eXBl"
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::NQ==::RGVmYXVsdCBjaGFubmVs" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::NQ==::RGVmYXVsdCBjaGFubmVs"
set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs" set_global_assignment -entity "niosII_mm_interconnect_0_router" -library "niosII" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
@ -859,7 +859,7 @@ set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0=" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTAzMCcgZW5kPScweDIxMDM4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDM4JyBlbmQ9JzB4MjEwNDAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0=" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDQwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTA0MCcgZW5kPScweDIxMDYwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTA2MCcgZW5kPScweDIxMDY4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDY4JyBlbmQ9JzB4MjEwNzAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k=" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ==" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ=="
set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==" set_global_assignment -entity "niosII_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="
@ -1042,7 +1042,7 @@ set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPON
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0=" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczEnIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMScgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::aW5zdFNsYXZlTWFwUGFyYW0="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDIwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAyMCcgZW5kPScweDIxMDMwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTAzMCcgZW5kPScweDIxMDM4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDM4JyBlbmQ9JzB4MjEwNDAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0=" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdtZW0uczInIHN0YXJ0PScweDAnIGVuZD0nMHgyMDAwMCcgdHlwZT0nYWx0ZXJhX2F2YWxvbl9vbmNoaXBfbWVtb3J5Mi5zMicgLz48c2xhdmUgbmFtZT0nY3B1LmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MjA4MDAnIGVuZD0nMHgyMTAwMCcgdHlwZT0nYWx0ZXJhX25pb3MyX2dlbjIuZGVidWdfbWVtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzZW0ucmFtX3NsYXZlJyBzdGFydD0nMHgyMTAwMCcgZW5kPScweDIxMDQwJyB0eXBlPSdzZW0ucmFtX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdzeXNfY2xrX3RpbWVyLnMxJyBzdGFydD0nMHgyMTA0MCcgZW5kPScweDIxMDYwJyB0eXBlPSdhbHRlcmFfYXZhbG9uX3RpbWVyLnMxJyAvPjxzbGF2ZSBuYW1lPSdzZW0uY3RsX3NsYXZlJyBzdGFydD0nMHgyMTA2MCcgZW5kPScweDIxMDY4JyB0eXBlPSdzZW0uY3RsX3NsYXZlJyAvPjxzbGF2ZSBuYW1lPSdqdGFnX3VhcnQuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDIxMDY4JyBlbmQ9JzB4MjEwNzAnIHR5cGU9J2FsdGVyYV9hdmFsb25fanRhZ191YXJ0LmF2YWxvbl9qdGFnX3NsYXZlJyAvPjwvYWRkcmVzcy1tYXA+::ZGF0YVNsYXZlTWFwUGFyYW0="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k=" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::NTAwMDAwMDA=::Y2xvY2tGcmVxdWVuY3k="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ==" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlRmFtaWx5TmFtZQ=="
set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==" set_global_assignment -entity "niosII_cpu_cpu" -library "niosII" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::Mw==::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="

2
Top/niosII/synthesis/niosII.v
View File

@ -44,7 +44,7 @@ module niosII (
wire [3:0] mm_interconnect_0_cpu_debug_mem_slave_byteenable; // mm_interconnect_0:cpu_debug_mem_slave_byteenable -> cpu:debug_mem_slave_byteenable wire [3:0] mm_interconnect_0_cpu_debug_mem_slave_byteenable; // mm_interconnect_0:cpu_debug_mem_slave_byteenable -> cpu:debug_mem_slave_byteenable
wire mm_interconnect_0_cpu_debug_mem_slave_write; // mm_interconnect_0:cpu_debug_mem_slave_write -> cpu:debug_mem_slave_write wire mm_interconnect_0_cpu_debug_mem_slave_write; // mm_interconnect_0:cpu_debug_mem_slave_write -> cpu:debug_mem_slave_write
wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_writedata; // mm_interconnect_0:cpu_debug_mem_slave_writedata -> cpu:debug_mem_slave_writedata wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_writedata; // mm_interconnect_0:cpu_debug_mem_slave_writedata -> cpu:debug_mem_slave_writedata
wire [1:0] mm_interconnect_0_sem_ram_slave_address; // mm_interconnect_0:sem_ram_slave_address -> sem:ram_addr wire [3:0] mm_interconnect_0_sem_ram_slave_address; // mm_interconnect_0:sem_ram_slave_address -> sem:ram_addr
wire mm_interconnect_0_sem_ram_slave_write; // mm_interconnect_0:sem_ram_slave_write -> sem:ram_wr wire mm_interconnect_0_sem_ram_slave_write; // mm_interconnect_0:sem_ram_slave_write -> sem:ram_wr
wire [31:0] mm_interconnect_0_sem_ram_slave_writedata; // mm_interconnect_0:sem_ram_slave_writedata -> sem:ram_wrdata wire [31:0] mm_interconnect_0_sem_ram_slave_writedata; // mm_interconnect_0:sem_ram_slave_writedata -> sem:ram_wrdata
wire mm_interconnect_0_sys_clk_timer_s1_chipselect; // mm_interconnect_0:sys_clk_timer_s1_chipselect -> sys_clk_timer:chipselect wire mm_interconnect_0_sys_clk_timer_s1_chipselect; // mm_interconnect_0:sys_clk_timer_s1_chipselect -> sys_clk_timer:chipselect

2
Top/niosII/synthesis/submodules/dec.sv
View File

@ -10,7 +10,7 @@ module dec
output logic [31:0] ctl_rddata, output logic [31:0] ctl_rddata,
//memory slave //memory slave
input logic ram_wr, input logic ram_wr,
input logic [1:0] ram_addr, input logic [3:0] ram_addr,
input logic [31:0] ram_wrdata, input logic [31:0] ram_wrdata,
//external ports //external ports
input logic train, input logic train,

4
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0.v
View File

@ -55,7 +55,7 @@ module niosII_mm_interconnect_0 (
output wire sem_ctl_slave_read, // .read output wire sem_ctl_slave_read, // .read
input wire [31:0] sem_ctl_slave_readdata, // .readdata input wire [31:0] sem_ctl_slave_readdata, // .readdata
output wire [31:0] sem_ctl_slave_writedata, // .writedata output wire [31:0] sem_ctl_slave_writedata, // .writedata
output wire [1:0] sem_ram_slave_address, // sem_ram_slave.address output wire [3:0] sem_ram_slave_address, // sem_ram_slave.address
output wire sem_ram_slave_write, // .write output wire sem_ram_slave_write, // .write
output wire [31:0] sem_ram_slave_writedata, // .writedata output wire [31:0] sem_ram_slave_writedata, // .writedata
output wire [2:0] sys_clk_timer_s1_address, // sys_clk_timer_s1.address output wire [2:0] sys_clk_timer_s1_address, // sys_clk_timer_s1.address
@ -846,7 +846,7 @@ module niosII_mm_interconnect_0 (
); );
altera_merlin_slave_translator #( altera_merlin_slave_translator #(
.AV_ADDRESS_W (2), .AV_ADDRESS_W (4),
.AV_DATA_W (32), .AV_DATA_W (32),
.UAV_DATA_W (32), .UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1), .AV_BURSTCOUNT_W (1),

34
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router.sv
View File

@ -136,16 +136,16 @@ module niosII_mm_interconnect_0_router
// ------------------------------------------------------- // -------------------------------------------------------
localparam PAD0 = log2ceil(64'h20000 - 64'h0); localparam PAD0 = log2ceil(64'h20000 - 64'h0);
localparam PAD1 = log2ceil(64'h21000 - 64'h20800); localparam PAD1 = log2ceil(64'h21000 - 64'h20800);
localparam PAD2 = log2ceil(64'h21020 - 64'h21000); localparam PAD2 = log2ceil(64'h21040 - 64'h21000);
localparam PAD3 = log2ceil(64'h21030 - 64'h21020); localparam PAD3 = log2ceil(64'h21060 - 64'h21040);
localparam PAD4 = log2ceil(64'h21038 - 64'h21030); localparam PAD4 = log2ceil(64'h21068 - 64'h21060);
localparam PAD5 = log2ceil(64'h21040 - 64'h21038); localparam PAD5 = log2ceil(64'h21070 - 64'h21068);
// ------------------------------------------------------- // -------------------------------------------------------
// Work out which address bits are significant based on the // Work out which address bits are significant based on the
// address range of the slaves. If the required width is too // address range of the slaves. If the required width is too
// large or too small, we use the address field width instead. // large or too small, we use the address field width instead.
// ------------------------------------------------------- // -------------------------------------------------------
localparam ADDR_RANGE = 64'h21040; localparam ADDR_RANGE = 64'h21070;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ? (RANGE_ADDR_WIDTH == 0) ?
@ -210,26 +210,26 @@ module niosII_mm_interconnect_0_router
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end end
// ( 0x21000 .. 0x21020 ) // ( 0x21000 .. 0x21040 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h21000 ) begin if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h21000 && write_transaction ) begin
src_channel = 7'b010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
end
// ( 0x21020 .. 0x21030 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h21020 && write_transaction ) begin
src_channel = 7'b001000; src_channel = 7'b001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end end
// ( 0x21030 .. 0x21038 ) // ( 0x21040 .. 0x21060 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h21030 ) begin if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h21040 ) begin
src_channel = 7'b010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
end
// ( 0x21060 .. 0x21068 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h21060 ) begin
src_channel = 7'b000010; src_channel = 7'b000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end end
// ( 0x21038 .. 0x21040 ) // ( 0x21068 .. 0x21070 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 18'h21038 ) begin if ( {address[RG:PAD5],{PAD5{1'b0}}} == 18'h21068 ) begin
src_channel = 7'b000001; src_channel = 7'b000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end end

13
Top/niosII/synthesis/submodules/periodram.v
View File

@ -92,6 +92,13 @@ module periodram (
altsyncram_component.clock_enable_input_a = "BYPASS", altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS", altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS", altsyncram_component.clock_enable_output_b = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "periodram.rif"
`else
altsyncram_component.init_file = "periodram.hex"
`endif
,
altsyncram_component.init_file_layout = "PORT_B",
altsyncram_component.intended_device_family = "Cyclone IV E", altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram", altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16, altsyncram_component.numwords_a = 16,
@ -120,7 +127,7 @@ endmodule
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" // Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
@ -145,7 +152,7 @@ endmodule
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512" // Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "" // Retrieval info: PRIVATE: MIFfilename STRING "periodram.hex"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
@ -178,6 +185,8 @@ endmodule
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "periodram.hex"
// Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"

2
Top/niosII/testbench/mentor/msim_setup.tcl
View File

@ -94,7 +94,7 @@
# within the Quartus project, and generate a unified # within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design. # script which supports all the Altera IP within the design.
# ---------------------------------------- # ----------------------------------------
# ACDS 18.1 625 win32 2022.12.21.21:02:08 # ACDS 18.1 625 win32 2022.12.22.22:39:16
# ---------------------------------------- # ----------------------------------------
# Initialize variables # Initialize variables

14
Top/niosII/testbench/niosII.html
View File

@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table> </table>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">2022.12.21.21:01:24</td> <td class="l">2022.12.22.22:38:31</td>
<td class="r">Datasheet</td> <td class="r">Datasheet</td>
</tr> </tr>
</table> </table>
@ -144,7 +144,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="slaveb">avalon_jtag_slave&#160;</td> <td class="slaveb">avalon_jtag_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021038</td> <td class="addr"><span style="color:#989898">0x</span>00021068</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
<tr> <tr>
@ -175,12 +175,12 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="slavem">ctl_slave&#160;</td> <td class="slavem">ctl_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021030</td> <td class="addr"><span style="color:#989898">0x</span>00021060</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
<tr> <tr>
<td class="slavem">ram_slave&#160;</td> <td class="slavem">ram_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021020</td> <td class="addr"><span style="color:#989898">0x</span>00021000</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
<tr> <tr>
@ -193,7 +193,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="slaveb">s1&#160;</td> <td class="slaveb">s1&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021000</td> <td class="addr"><span style="color:#989898">0x</span>00021040</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
</table> </table>
@ -1107,7 +1107,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">dataSlaveMapParam</td> <td class="parametername">dataSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /&gt;&lt;slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td> <td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">tightlyCoupledDataMaster0MapParam</td> <td class="parametername">tightlyCoupledDataMaster0MapParam</td>
@ -2039,7 +2039,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">generation took 0,00 seconds</td> <td class="l">generation took 0,00 seconds</td>
<td class="r">rendering took 0,08 seconds</td> <td class="r">rendering took 0,04 seconds</td>
</tr> </tr>
</table> </table>
</body> </body>

18
Top/niosII/testbench/niosII_tb.html
View File

@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table> </table>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">2022.12.21.21:01:33</td> <td class="l">2022.12.22.22:38:42</td>
<td class="r">Datasheet</td> <td class="r">Datasheet</td>
</tr> </tr>
</table> </table>
@ -144,7 +144,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="slaveb">avalon_jtag_slave&#160;</td> <td class="slaveb">avalon_jtag_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021038</td> <td class="addr"><span style="color:#989898">0x</span>00021068</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
<tr> <tr>
@ -175,12 +175,12 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="slavem">ctl_slave&#160;</td> <td class="slavem">ctl_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021030</td> <td class="addr"><span style="color:#989898">0x</span>00021060</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
<tr> <tr>
<td class="slavem">ram_slave&#160;</td> <td class="slavem">ram_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021020</td> <td class="addr"><span style="color:#989898">0x</span>00021000</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
<tr> <tr>
@ -193,7 +193,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="slaveb">s1&#160;</td> <td class="slaveb">s1&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021000</td> <td class="addr"><span style="color:#989898">0x</span>00021040</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
</table> </table>
@ -211,7 +211,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table> <table>
<tr> <tr>
<td class="parametername">AUTO_GENERATION_ID</td> <td class="parametername">AUTO_GENERATION_ID</td>
<td class="parametervalue">1671642093</td> <td class="parametervalue">1671734322</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">AUTO_UNIQUE_ID</td> <td class="parametername">AUTO_UNIQUE_ID</td>
@ -1323,7 +1323,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">dataSlaveMapParam</td> <td class="parametername">dataSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ram_slave' start='0x21020' end='0x21030' type='sem.ram_slave' /&gt;&lt;slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='sem.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td> <td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">tightlyCoupledDataMaster0MapParam</td> <td class="parametername">tightlyCoupledDataMaster0MapParam</td>
@ -2359,8 +2359,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</div> </div>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">generation took 0,00 seconds</td> <td class="l">generation took 0,02 seconds</td>
<td class="r">rendering took 0,06 seconds</td> <td class="r">rendering took 0,05 seconds</td>
</tr> </tr>
</table> </table>
</body> </body>

4
Top/niosII/testbench/synopsys/vcs/vcs_setup.sh
View File

@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable # or its authorized distributors. Please refer to the applicable
# agreement for further details. # agreement for further details.
# ACDS 18.1 625 win32 2022.12.21.21:02:08 # ACDS 18.1 625 win32 2022.12.22.22:39:16
# ---------------------------------------- # ----------------------------------------
# vcs - auto-generated simulation script # vcs - auto-generated simulation script
@ -94,7 +94,7 @@
# within the Quartus project, and generate a unified # within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design. # script which supports all the Altera IP within the design.
# ---------------------------------------- # ----------------------------------------
# ACDS 18.1 625 win32 2022.12.21.21:02:08 # ACDS 18.1 625 win32 2022.12.22.22:39:16
# ---------------------------------------- # ----------------------------------------
# initialize variables # initialize variables
TOP_LEVEL_NAME="niosII_tb" TOP_LEVEL_NAME="niosII_tb"

4
Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh
View File

@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable # or its authorized distributors. Please refer to the applicable
# agreement for further details. # agreement for further details.
# ACDS 18.1 625 win32 2022.12.21.21:02:08 # ACDS 18.1 625 win32 2022.12.22.22:39:16
# ---------------------------------------- # ----------------------------------------
# vcsmx - auto-generated simulation script # vcsmx - auto-generated simulation script
@ -107,7 +107,7 @@
# within the Quartus project, and generate a unified # within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design. # script which supports all the Altera IP within the design.
# ---------------------------------------- # ----------------------------------------
# ACDS 18.1 625 win32 2022.12.21.21:02:08 # ACDS 18.1 625 win32 2022.12.22.22:39:16
# ---------------------------------------- # ----------------------------------------
# initialize variables # initialize variables
TOP_LEVEL_NAME="niosII_tb" TOP_LEVEL_NAME="niosII_tb"

6
Top/niosII_tb.csv
View File

@ -1,12 +1,12 @@
# system info niosII_tb on 2022.12.21.21:02:06 # system info niosII_tb on 2022.12.22.22:39:13
system_info: system_info:
name,value name,value
DEVICE,EP4CE115F29C7 DEVICE,EP4CE115F29C7
DEVICE_FAMILY,Cyclone IV E DEVICE_FAMILY,Cyclone IV E
GENERATION_ID,1671642093 GENERATION_ID,1671734322
# #
# #
# Files generated for niosII_tb on 2022.12.21.21:02:06 # Files generated for niosII_tb on 2022.12.22.22:39:13
files: files:
filepath,kind,attributes,module,is_top filepath,kind,attributes,module,is_top
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true

1 # system info niosII_tb on 2022.12.21.21:02:06 # system info niosII_tb on 2022.12.22.22:39:13
2 system_info: system_info:
3 name,value name,value
4 DEVICE,EP4CE115F29C7 DEVICE,EP4CE115F29C7
5 DEVICE_FAMILY,Cyclone IV E DEVICE_FAMILY,Cyclone IV E
6 GENERATION_ID,1671642093 GENERATION_ID,1671734322
7 # #
8 # #
9 # Files generated for niosII_tb on 2022.12.21.21:02:06 # Files generated for niosII_tb on 2022.12.22.22:39:13
10 files: files:
11 filepath,kind,attributes,module,is_top filepath,kind,attributes,module,is_top
12 niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true

BIN
Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf
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908
Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.map
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11538
Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump
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11573
Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat
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314
Top/software/semafor/mem_init/hdl_sim/niosII_mem.sym
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@ -7,163 +7,163 @@
00000230 T _start 00000230 T _start
00000244 t alt_after_alt_main 00000244 t alt_after_alt_main
00000248 T main 00000248 T main
00000334 T _puts_r 00000338 T _puts_r
000003f4 T puts 000003f8 T puts
00000408 T strlen 0000040c T strlen
000004a0 t __fp_unlock 000004a4 t __fp_unlock
000004a8 T _cleanup_r 000004ac T _cleanup_r
000004b4 t __sinit.part.1 000004b8 t __sinit.part.1
00000650 t __fp_lock 00000654 t __fp_lock
00000658 T __sfmoreglue 0000065c T __sfmoreglue
000006d0 T __sfp 000006d4 T __sfp
000007e8 T _cleanup 000007ec T _cleanup
00000800 T __sinit 00000804 T __sinit
00000810 T __sfp_lock_acquire 00000814 T __sfp_lock_acquire
00000814 T __sfp_lock_release 00000818 T __sfp_lock_release
00000818 T __sinit_lock_acquire 0000081c T __sinit_lock_acquire
0000081c T __sinit_lock_release 00000820 T __sinit_lock_release
00000820 T __fp_lock_all 00000824 T __fp_lock_all
00000838 T __fp_unlock_all 0000083c T __fp_unlock_all
00000850 T __sfvwrite_r 00000854 T __sfvwrite_r
00000d18 T _fwalk 00000d1c T _fwalk
00000ddc T _fwalk_reent 00000de0 T _fwalk_reent
00000ea0 T _malloc_r 00000ea4 T _malloc_r
000016ac T memchr 000016b0 T memchr
00001790 T memcpy 00001794 T memcpy
000018d8 T memmove 000018dc T memmove
00001a34 T memset 00001a38 T memset
00001b5c T _realloc_r 00001b60 T _realloc_r
000020c0 T _sbrk_r 000020c4 T _sbrk_r
00002114 T __sread 00002118 T __sread
00002168 T __seofread 0000216c T __seofread
00002170 T __swrite 00002174 T __swrite
000021ec T __sseek 000021f0 T __sseek
00002248 T __sclose 0000224c T __sclose
00002250 T _write_r 00002254 T _write_r
000022b0 T __swsetup_r 000022b4 T __swsetup_r
00002404 T _close_r 00002408 T _close_r
00002458 T _fclose_r 0000245c T _fclose_r
00002548 T fclose 0000254c T fclose
0000255c T __sflush_r 00002560 T __sflush_r
00002778 T _fflush_r 0000277c T _fflush_r
000027d4 T fflush 000027d8 T fflush
00002804 T _malloc_trim_r 00002808 T _malloc_trim_r
00002928 T _free_r 0000292c T _free_r
00002c38 T _lseek_r 00002c3c T _lseek_r
00002c98 T __smakebuf_r 00002c9c T __smakebuf_r
00002e54 T _read_r 00002e58 T _read_r
00002eb4 T _fstat_r 00002eb8 T _fstat_r
00002f10 T _isatty_r 00002f14 T _isatty_r
00002f64 T __divsi3 00002f68 T __divsi3
00002fe8 T __modsi3 00002fec T __modsi3
0000305c T __udivsi3 00003060 T __udivsi3
000030c0 T __umodsi3 000030c4 T __umodsi3
00003118 T __mulsi3 0000311c T __mulsi3
00003140 t alt_get_errno 00003144 t alt_get_errno
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000032e4 T fstat 000032e8 T fstat
0000339c t alt_get_errno 000033a0 t alt_get_errno
000033d8 T isatty 000033dc T isatty
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000034c0 T lseek 000034c4 T lseek
0000359c T alt_main 000035a0 T alt_main
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00003824 T sbrk 00003828 T sbrk
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00003910 T write 00003914 T write
00003a10 t alt_dev_reg 00003a14 t alt_dev_reg
00003a44 T alt_irq_init 00003a48 T alt_irq_init
00003a7c T alt_sys_init 00003a80 T alt_sys_init
00003adc T altera_avalon_jtag_uart_read_fd 00003ae0 T altera_avalon_jtag_uart_read_fd
00003b3c T altera_avalon_jtag_uart_write_fd 00003b40 T altera_avalon_jtag_uart_write_fd
00003b9c T altera_avalon_jtag_uart_close_fd 00003ba0 T altera_avalon_jtag_uart_close_fd
00003bec T altera_avalon_jtag_uart_ioctl_fd 00003bf0 T altera_avalon_jtag_uart_ioctl_fd
00003c40 T altera_avalon_jtag_uart_init 00003c44 T altera_avalon_jtag_uart_init
00003d00 t altera_avalon_jtag_uart_irq 00003d04 t altera_avalon_jtag_uart_irq
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00004544 t alt_avalon_timer_sc_irq 00004548 t alt_avalon_timer_sc_irq
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00004638 T alt_alarm_start 0000463c T alt_alarm_start
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000047a0 T alt_dev_llist_insert 000047a4 T alt_dev_llist_insert
00004844 T _do_ctors 00004848 T _do_ctors
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00004904 T alt_ic_isr_register 00004908 T alt_ic_isr_register
00004954 T alt_ic_irq_enable 00004958 T alt_ic_irq_enable
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000072c4 A __bss_start 000072c8 A __bss_start
000072c4 B __malloc_max_total_mem 000072c8 B __malloc_max_total_mem
000072c4 A _edata 000072c8 A _edata
000072c8 B __malloc_max_sbrked_mem 000072cc B __malloc_max_sbrked_mem
000072cc B __malloc_top_pad 000072d0 B __malloc_top_pad
000072d0 B errno 000072d4 B errno
000072d4 B alt_argc 000072d8 B alt_argc
000072d8 B alt_argv 000072dc B alt_argv
000072dc B alt_envp 000072e0 B alt_envp
000072e0 B alt_irq_active 000072e4 B alt_irq_active
000072e4 B _alt_tick_rate 000072e8 B _alt_tick_rate
000072e8 B _alt_nticks 000072ec B _alt_nticks
000072ec B alt_instruction_exception_handler 000072f0 B alt_instruction_exception_handler
000072f0 B __malloc_current_mallinfo 000072f4 B __malloc_current_mallinfo
00007318 B alt_irq 0000731c B alt_irq
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00020000 A __alt_stack_pointer 00020000 A __alt_stack_pointer

1470
Top/software/semafor/mem_init/niosII_mem.hex
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18
Top/software/semafor/sem.c
View File

@ -6,10 +6,10 @@
#define TIME_SETS 4 #define TIME_SETS 4
#define TIME_STATES 4 #define TIME_STATES 4
const alt_u32 divisors[TIME_SETS][TIME_STATES] = { const alt_u32 divisors[TIME_SETS][TIME_STATES] = {
{0x100000, 0x100000, 0x50000, 0x10000}, {0x00000010, 0x00000010, 0x00000005, 0x00000010},
{0x100000, 0x200000, 0x100000, 0x10000}, {0x00000010, 0x00000020, 0x00000010, 0x00000010},
{0x150000, 0x250000, 0x200000, 0x10000}, {0x000000f0, 0x000000f0, 0x000000f0, 0x00000010},
{0x250000, 0x250000, 0x250000, 0x10000} {0x000000fa, 0x000000f0, 0x000000f0, 0x00000010}
}; };
int main() int main()
@ -20,14 +20,12 @@ int main()
//program divisors //program divisors
p = (alt_u32*) SEM_RAM_SLAVE_BASE; p = (alt_u32*) SEM_RAM_SLAVE_BASE;
for (i=0; i<TIME_SETS; i++) for (i = 0; i < TIME_SETS; i++) {
{
tmp = 0; tmp = 0;
for (j=TIME_STATES; j>0; j--) for (j = TIME_STATES; j > 0; j--) {
{ tmp = (tmp << 32) | divisors[i][j - 1];
tmp = (tmp << 8) | divisors[i][j-1];
} }
*p=tmp; *p = tmp;
p++; p++;
} }
//since we use pointers (cached data access) to write divisor RAM, //since we use pointers (cached data access) to write divisor RAM,

BIN
Top/software/semafor_bsp/libhal_bsp.a
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Binary file not shown.

22
Top/software/semafor_bsp/settings.bsp
View File

@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema"> <sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType> <BspType>hal</BspType>
<BspVersion>default</BspVersion> <BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>22.12.2022 17:21:19</BspGeneratedTimeStamp> <BspGeneratedTimeStamp>22.12.2022 22:44:16</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1671715279678</BspGeneratedUnixTimeStamp> <BspGeneratedUnixTimeStamp>1671734657095</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation> <BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile> <BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile> <SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile>
@ -904,27 +904,27 @@
<addressSpan>131072</addressSpan> <addressSpan>131072</addressSpan>
<attributes>memory</attributes> <attributes>memory</attributes>
</MemoryMap> </MemoryMap>
<MemoryMap>
<slaveDescriptor>sem_ram_slave</slaveDescriptor>
<addressRange>0x00021000 - 0x0002103F</addressRange>
<addressSpan>64</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap> <MemoryMap>
<slaveDescriptor>sys_clk_timer</slaveDescriptor> <slaveDescriptor>sys_clk_timer</slaveDescriptor>
<addressRange>0x00021000 - 0x0002101F</addressRange> <addressRange>0x00021040 - 0x0002105F</addressRange>
<addressSpan>32</addressSpan> <addressSpan>32</addressSpan>
<attributes>timer</attributes> <attributes>timer</attributes>
</MemoryMap> </MemoryMap>
<MemoryMap>
<slaveDescriptor>sem_ram_slave</slaveDescriptor>
<addressRange>0x00021020 - 0x0002102F</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap> <MemoryMap>
<slaveDescriptor>sem_ctl_slave</slaveDescriptor> <slaveDescriptor>sem_ctl_slave</slaveDescriptor>
<addressRange>0x00021030 - 0x00021037</addressRange> <addressRange>0x00021060 - 0x00021067</addressRange>
<addressSpan>8</addressSpan> <addressSpan>8</addressSpan>
<attributes/> <attributes/>
</MemoryMap> </MemoryMap>
<MemoryMap> <MemoryMap>
<slaveDescriptor>jtag_uart</slaveDescriptor> <slaveDescriptor>jtag_uart</slaveDescriptor>
<addressRange>0x00021038 - 0x0002103F</addressRange> <addressRange>0x00021068 - 0x0002106F</addressRange>
<addressSpan>8</addressSpan> <addressSpan>8</addressSpan>
<attributes>printable</attributes> <attributes>printable</attributes>
</MemoryMap> </MemoryMap>

12
Top/software/semafor_bsp/summary.html
View File

@ -22,10 +22,10 @@
<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td> <td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
</tr> </tr>
<tr mode="wrap"> <tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>22.12.2022 17:21:19</td> <td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>22.12.2022 22:44:16</td>
</tr> </tr>
<tr mode="wrap"> <tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671715279678</td> <td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671734657095</td>
</tr> </tr>
<tr mode="wrap"> <tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td> <td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td>
@ -38,16 +38,16 @@
<th align="left" width="20%">Slave Descriptor</th><th align="left" width="40%">Address Range</th><th align="left" width="20%">Size</th><th align="left" width="20%">Attributes</th> <th align="left" width="20%">Slave Descriptor</th><th align="left" width="40%">Address Range</th><th align="left" width="20%">Size</th><th align="left" width="20%">Attributes</th>
</tr> </tr>
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'"> <tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
<td>jtag_uart</td><td>0x00021038 - 0x0002103F</td><td>8</td><td class="listing">printable</td> <td>jtag_uart</td><td>0x00021068 - 0x0002106F</td><td>8</td><td class="listing">printable</td>
</tr> </tr>
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'"> <tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
<td>sem_ctl_slave</td><td>0x00021030 - 0x00021037</td><td>8</td><td class="listing">&nbsp;</td> <td>sem_ctl_slave</td><td>0x00021060 - 0x00021067</td><td>8</td><td class="listing">&nbsp;</td>
</tr> </tr>
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'"> <tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
<td>sem_ram_slave</td><td>0x00021020 - 0x0002102F</td><td>16</td><td class="listing">&nbsp;</td> <td>sys_clk_timer</td><td>0x00021040 - 0x0002105F</td><td>32</td><td class="listing">timer</td>
</tr> </tr>
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'"> <tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
<td>sys_clk_timer</td><td>0x00021000 - 0x0002101F</td><td>32</td><td class="listing">timer</td> <td>sem_ram_slave</td><td>0x00021000 - 0x0002103F</td><td>64</td><td class="listing">&nbsp;</td>
</tr> </tr>
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'"> <tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
<td>mem</td><td>0x00000000 - 0x0001FFFF</td><td>131072</td><td class="listing">memory</td> <td>mem</td><td>0x00000000 - 0x0001FFFF</td><td>131072</td><td class="listing">memory</td>

18
Top/software/semafor_bsp/system.h
View File

@ -4,7 +4,7 @@
* Machine generated for CPU 'cpu' in SOPC Builder design 'niosII' * Machine generated for CPU 'cpu' in SOPC Builder design 'niosII'
* SOPC Builder design path: ../../niosII.sopcinfo * SOPC Builder design path: ../../niosII.sopcinfo
* *
* Generated: Mon Oct 24 11:12:11 MSK 2022 * Generated: Thu Dec 22 22:44:18 MSK 2022
*/ */
/* /*
@ -156,19 +156,19 @@
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 #define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1 #define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart" #define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_BASE 0x21038 #define ALT_STDERR_BASE 0x21068
#define ALT_STDERR_DEV jtag_uart #define ALT_STDERR_DEV jtag_uart
#define ALT_STDERR_IS_JTAG_UART #define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT #define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart" #define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/jtag_uart" #define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_BASE 0x21038 #define ALT_STDIN_BASE 0x21068
#define ALT_STDIN_DEV jtag_uart #define ALT_STDIN_DEV jtag_uart
#define ALT_STDIN_IS_JTAG_UART #define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT #define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart" #define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart" #define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_BASE 0x21038 #define ALT_STDOUT_BASE 0x21068
#define ALT_STDOUT_DEV jtag_uart #define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_IS_JTAG_UART #define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT #define ALT_STDOUT_PRESENT
@ -193,7 +193,7 @@
*/ */
#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart #define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart
#define JTAG_UART_BASE 0x21038 #define JTAG_UART_BASE 0x21068
#define JTAG_UART_IRQ 1 #define JTAG_UART_IRQ 1
#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0 #define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_NAME "/dev/jtag_uart" #define JTAG_UART_NAME "/dev/jtag_uart"
@ -240,7 +240,7 @@
*/ */
#define ALT_MODULE_CLASS_sem_ctl_slave sem #define ALT_MODULE_CLASS_sem_ctl_slave sem
#define SEM_CTL_SLAVE_BASE 0x21030 #define SEM_CTL_SLAVE_BASE 0x21060
#define SEM_CTL_SLAVE_IRQ -1 #define SEM_CTL_SLAVE_IRQ -1
#define SEM_CTL_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1 #define SEM_CTL_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SEM_CTL_SLAVE_NAME "/dev/sem_ctl_slave" #define SEM_CTL_SLAVE_NAME "/dev/sem_ctl_slave"
@ -254,11 +254,11 @@
*/ */
#define ALT_MODULE_CLASS_sem_ram_slave sem #define ALT_MODULE_CLASS_sem_ram_slave sem
#define SEM_RAM_SLAVE_BASE 0x21020 #define SEM_RAM_SLAVE_BASE 0x21000
#define SEM_RAM_SLAVE_IRQ -1 #define SEM_RAM_SLAVE_IRQ -1
#define SEM_RAM_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1 #define SEM_RAM_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SEM_RAM_SLAVE_NAME "/dev/sem_ram_slave" #define SEM_RAM_SLAVE_NAME "/dev/sem_ram_slave"
#define SEM_RAM_SLAVE_SPAN 16 #define SEM_RAM_SLAVE_SPAN 64
#define SEM_RAM_SLAVE_TYPE "sem" #define SEM_RAM_SLAVE_TYPE "sem"
@ -269,7 +269,7 @@
#define ALT_MODULE_CLASS_sys_clk_timer altera_avalon_timer #define ALT_MODULE_CLASS_sys_clk_timer altera_avalon_timer
#define SYS_CLK_TIMER_ALWAYS_RUN 0 #define SYS_CLK_TIMER_ALWAYS_RUN 0
#define SYS_CLK_TIMER_BASE 0x21000 #define SYS_CLK_TIMER_BASE 0x21040
#define SYS_CLK_TIMER_COUNTER_SIZE 32 #define SYS_CLK_TIMER_COUNTER_SIZE 32
#define SYS_CLK_TIMER_FIXED_PERIOD 0 #define SYS_CLK_TIMER_FIXED_PERIOD 0
#define SYS_CLK_TIMER_FREQ 50000000 #define SYS_CLK_TIMER_FREQ 50000000