simulated individual, looks ok
This commit is contained in:
parent
881e124d27
commit
b86b8e55dc
133
HDL/dec.sv
133
HDL/dec.sv
|
@ -17,8 +17,13 @@ module dec
|
||||||
output logic red, yellow, green
|
output logic red, yellow, green
|
||||||
);
|
);
|
||||||
|
|
||||||
|
typedef enum logic [1:0] {RED, YELLOW, BLINK, GREEN} FSMStates;
|
||||||
|
|
||||||
logic run;
|
logic run;
|
||||||
logic [1:0] divider;
|
logic [1:0] divider;
|
||||||
|
logic [1:0] state;
|
||||||
|
logic [31:0] greenSaved;
|
||||||
|
logic [31:0] greenCount;
|
||||||
|
|
||||||
logic [m-1:0] divisor;
|
logic [m-1:0] divisor;
|
||||||
logic [1:0] contr;
|
logic [1:0] contr;
|
||||||
|
@ -27,17 +32,12 @@ module dec
|
||||||
logic enacnt;
|
logic enacnt;
|
||||||
|
|
||||||
//control slave logic
|
//control slave logic
|
||||||
always_ff @ (posedge clk or negedge clrn)
|
always_ff @ (posedge clk or negedge clrn) begin
|
||||||
begin
|
if (!clrn) begin
|
||||||
if (!clrn)
|
|
||||||
begin
|
|
||||||
run <= 0;
|
run <= 0;
|
||||||
divider <= 0;
|
divider <= 0;
|
||||||
end
|
end else begin
|
||||||
else
|
if (ctl_wr) begin
|
||||||
begin
|
|
||||||
if (ctl_wr)
|
|
||||||
begin
|
|
||||||
case (ctl_addr)
|
case (ctl_addr)
|
||||||
1'b0: run <= ctl_wrdata[0];
|
1'b0: run <= ctl_wrdata[0];
|
||||||
1'b1: divider <= ctl_wrdata[1:0];
|
1'b1: divider <= ctl_wrdata[1:0];
|
||||||
|
@ -46,8 +46,7 @@ module dec
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
always_comb
|
always_comb begin
|
||||||
begin
|
|
||||||
case (ctl_addr)
|
case (ctl_addr)
|
||||||
1'b0: ctl_rddata = {31'b0,run};
|
1'b0: ctl_rddata = {31'b0,run};
|
||||||
1'b1: ctl_rddata = {30'b0,divider};
|
1'b1: ctl_rddata = {30'b0,divider};
|
||||||
|
@ -56,70 +55,96 @@ module dec
|
||||||
end
|
end
|
||||||
|
|
||||||
//semaphore logic
|
//semaphore logic
|
||||||
|
always_ff @ (posedge clk or negedge clrn) begin
|
||||||
always_ff @ (posedge clk or negedge clrn)
|
if (!clrn)
|
||||||
begin
|
cntdiv <= 0;
|
||||||
if (!clrn) cntdiv<=0;
|
else begin
|
||||||
else
|
if (train | ~run)
|
||||||
begin
|
cntdiv<=0;
|
||||||
if (train | ~run) cntdiv<=0;
|
else begin
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (enacnt) cntdiv<=0;
|
if (enacnt) cntdiv<=0;
|
||||||
else cntdiv<=cntdiv+1;
|
else cntdiv<=cntdiv+1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
always_comb
|
// we don't enable counters, if color is green
|
||||||
begin
|
always_comb begin
|
||||||
enacnt=(cntdiv==divisor);
|
enacnt = ((cntdiv == divisor) && !(colors == 3'b001));
|
||||||
end
|
end
|
||||||
|
|
||||||
always_ff @ (posedge clk or negedge clrn)
|
always_ff @ (posedge clk or negedge clrn) begin
|
||||||
begin
|
if (!clrn) begin
|
||||||
if (!clrn)
|
colors <= 3'b001;
|
||||||
begin
|
state <= GREEN;
|
||||||
colors <= 3'b100;
|
greenCount <= 32'd0;
|
||||||
|
end else begin
|
||||||
|
if (~run) begin
|
||||||
|
colors <= 3'b001;
|
||||||
|
state <= GREEN;
|
||||||
end
|
end
|
||||||
else
|
if (train) begin
|
||||||
begin
|
|
||||||
if (train | ~run)
|
|
||||||
begin
|
|
||||||
colors <= 3'b100;
|
colors <= 3'b100;
|
||||||
|
state <= RED;
|
||||||
|
greenSaved <= divisor;
|
||||||
|
greenCount <= divisor;
|
||||||
|
end else begin
|
||||||
|
case (state)
|
||||||
|
RED: begin
|
||||||
|
colors <= 3'b100;
|
||||||
|
if (enacnt) begin
|
||||||
|
state <= state + 1'b1;
|
||||||
|
greenSaved <= divisor;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
YELLOW: begin
|
||||||
|
colors <= 3'b010;
|
||||||
|
if (enacnt) begin
|
||||||
|
state <= state + 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
BLINK: begin
|
||||||
|
if (enacnt) begin
|
||||||
|
state <= state + 1'b1;
|
||||||
|
end
|
||||||
|
if (greenSaved[0] == 0) begin
|
||||||
|
colors <= 3'b011;
|
||||||
|
end else begin
|
||||||
|
greenCount <= greenCount - 1'b1;
|
||||||
|
if (greenCount == 32'd0) begin
|
||||||
|
colors[1] <= ~colors[1];
|
||||||
|
greenCount <= greenSaved;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
GREEN: begin
|
||||||
|
if (enacnt) begin
|
||||||
|
state <= state + 1'b1;
|
||||||
|
end
|
||||||
|
colors <= 3'b001;
|
||||||
end
|
end
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (enacnt)
|
|
||||||
begin
|
|
||||||
case (colors)
|
|
||||||
3'b100: colors <= 3'b010;
|
|
||||||
3'b010: colors <= 3'b011;
|
|
||||||
3'b011: colors <= 3'b001;
|
|
||||||
3'b001: colors <= 3'b001;
|
|
||||||
default: colors <= 3'b100;
|
default: colors <= 3'b100;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
assign contr = state;
|
||||||
|
// always_comb begin
|
||||||
always_comb
|
// case (state)
|
||||||
begin
|
// 2'b00: contr = 2'b00;
|
||||||
case (colors)
|
// 2'b01: contr = 2'b01;
|
||||||
3'b100: contr = 2'b00;
|
// 2'b10: contr = 2'b10;
|
||||||
3'b010: contr = 2'b01;
|
// 2'b11: contr = 2'b11;
|
||||||
3'b011: contr = 2'b10;
|
// default : contr = 2'b00;
|
||||||
3'b001: contr = 2'b11;
|
// endcase
|
||||||
default : contr = 2'b00;
|
// end
|
||||||
endcase
|
|
||||||
end
|
|
||||||
|
|
||||||
assign red = colors[2];
|
assign red = colors[2];
|
||||||
assign yellow = colors[1];
|
assign yellow = colors[1];
|
||||||
assign green = colors[0];
|
assign green = colors[0];
|
||||||
|
|
||||||
periodram b2v_inst3(
|
periodram b2v_inst3
|
||||||
|
(
|
||||||
.clock(clk),
|
.clock(clk),
|
||||||
.data (ram_wrdata),
|
.data (ram_wrdata),
|
||||||
.wraddress (ram_addr),
|
.wraddress (ram_addr),
|
||||||
|
|
|
@ -0,0 +1,128 @@
|
||||||
|
`timescale 1 ns/1 ns
|
||||||
|
|
||||||
|
module dec_tb();
|
||||||
|
|
||||||
|
// Wires and variables to connect to UUT (unit under test)
|
||||||
|
logic clk, clrn, train;
|
||||||
|
logic r, y, g;
|
||||||
|
logic [1:0] div;
|
||||||
|
logic ctl_wr, ctl_rd;
|
||||||
|
logic ctl_addr;
|
||||||
|
logic [31:0] ctl_wrdata;
|
||||||
|
logic [31:0] ctl_rddata;
|
||||||
|
logic ram_wr;
|
||||||
|
logic [3:0] ram_addr;
|
||||||
|
logic [31:0] ram_wrdata;
|
||||||
|
|
||||||
|
logic [31:0] divisor[3:0] = {
|
||||||
|
{8'd10, 8'd70, 8'd50, 8'd20},
|
||||||
|
{8'd10, 8'd30, 8'd40, 8'd30},
|
||||||
|
{8'd10, 8'd30, 8'd10, 8'd100},
|
||||||
|
{8'd10, 8'd60, 8'd80, 8'd50}
|
||||||
|
};
|
||||||
|
|
||||||
|
// Instantiate UUT
|
||||||
|
dec my_sem(
|
||||||
|
.clk(clk), .clrn(clrn),
|
||||||
|
.ctl_wr(ctl_wr), .ctl_rd(ctl_rd),
|
||||||
|
.ctl_addr(ctl_addr), .ctl_wrdata(ctl_wrdata), .ctl_rddata(ctl_rddata),
|
||||||
|
.ram_wr(ram_wr),
|
||||||
|
.ram_addr(ram_addr), .ram_wrdata(ram_wrdata),
|
||||||
|
.train(train), .red(r), .yellow(y), .green(g)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Clock definition
|
||||||
|
initial begin
|
||||||
|
clk = 0;
|
||||||
|
forever #10 clk = ~clk;
|
||||||
|
end
|
||||||
|
|
||||||
|
// Divisor and train definition
|
||||||
|
initial begin
|
||||||
|
//initial reset
|
||||||
|
clrn = 0;
|
||||||
|
div = 0;
|
||||||
|
train = 0;
|
||||||
|
//take reset off
|
||||||
|
@(negedge clk) clrn = 1;
|
||||||
|
//configure semaphore
|
||||||
|
for (int i=0; i<4; i++) write_ram_transaction(i,divisor[i]); //write divisor RAM
|
||||||
|
write_reg_transaction(1,div); //write initial divisor
|
||||||
|
write_reg_transaction(0,1); //enable semaphore
|
||||||
|
//run trains
|
||||||
|
repeat (4)
|
||||||
|
begin
|
||||||
|
repeat (10) @(posedge clk);
|
||||||
|
train=1;
|
||||||
|
repeat (4) @(posedge clk);
|
||||||
|
train=0;
|
||||||
|
wait ({r,y,g}==3'b001);
|
||||||
|
repeat (10) @(posedge clk);
|
||||||
|
write_reg_transaction(1,div);
|
||||||
|
div=div+1;
|
||||||
|
end
|
||||||
|
//wait a little
|
||||||
|
repeat (10) @(posedge clk);
|
||||||
|
$stop;
|
||||||
|
end
|
||||||
|
|
||||||
|
//Single register write transaction task
|
||||||
|
task write_reg_transaction;
|
||||||
|
//input signals
|
||||||
|
input [1:0] offs;
|
||||||
|
input [31:0] val;
|
||||||
|
//transaction implementation
|
||||||
|
begin
|
||||||
|
@(posedge clk);
|
||||||
|
//assert signals for one clock cycle
|
||||||
|
ctl_wr = 1;
|
||||||
|
ctl_addr = offs;
|
||||||
|
ctl_wrdata = val;
|
||||||
|
@(posedge clk);
|
||||||
|
//deassert signals
|
||||||
|
ctl_wr = 0;
|
||||||
|
ctl_addr = 'bx;
|
||||||
|
ctl_wrdata = 'bx;
|
||||||
|
end
|
||||||
|
endtask
|
||||||
|
|
||||||
|
//Single register read transaction task
|
||||||
|
task read_reg_transaction;
|
||||||
|
//input signals
|
||||||
|
input [1:0] offs;
|
||||||
|
output [31:0] val;
|
||||||
|
//transaction implementation
|
||||||
|
begin
|
||||||
|
@(posedge clk);
|
||||||
|
//assert signals for one clock cycle
|
||||||
|
ctl_rd = 1;
|
||||||
|
ctl_addr = offs;
|
||||||
|
@(posedge clk);
|
||||||
|
val = ctl_rddata;
|
||||||
|
//deassert signals
|
||||||
|
ctl_rd = 0;
|
||||||
|
ctl_addr = 'bx;
|
||||||
|
end
|
||||||
|
endtask
|
||||||
|
|
||||||
|
//RAM write transaction task
|
||||||
|
task write_ram_transaction;
|
||||||
|
//input signals
|
||||||
|
input [1:0] offs;
|
||||||
|
input [31:0] val;
|
||||||
|
//transaction implementation
|
||||||
|
begin
|
||||||
|
@(posedge clk);
|
||||||
|
//assert signals for one clock cycle
|
||||||
|
ram_wr = 1;
|
||||||
|
ram_addr = offs;
|
||||||
|
ram_wrdata = val;
|
||||||
|
@(posedge clk);
|
||||||
|
//deassert signals
|
||||||
|
ram_wr = 0;
|
||||||
|
ram_addr = 'bx;
|
||||||
|
ram_wrdata = 'bx;
|
||||||
|
end
|
||||||
|
endtask
|
||||||
|
|
||||||
|
endmodule
|
|
@ -65,4 +65,5 @@ set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dec_tb
|
||||||
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb
|
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb
|
||||||
set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb
|
set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb
|
||||||
set_global_assignment -name HEX_FILE periodram.hex
|
set_global_assignment -name HEX_FILE periodram.hex
|
||||||
|
set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT simulation/modelsim/wave.do -section_id eda_simulation
|
||||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
|
@ -15,10 +15,10 @@ module dec_tb();
|
||||||
logic [31:0] ram_wrdata;
|
logic [31:0] ram_wrdata;
|
||||||
|
|
||||||
logic [31:0] divisor[3:0] = {
|
logic [31:0] divisor[3:0] = {
|
||||||
{8'd10, 8'd70, 8'd50, 8'd20},
|
{8'd11, 8'd71, 8'd51, 8'd21},
|
||||||
{8'd10, 8'd30, 8'd40, 8'd30},
|
{8'd11, 8'd31, 8'd41, 8'd31},
|
||||||
{8'd10, 8'd30, 8'd10, 8'd100},
|
{8'd11, 8'd31, 8'd11, 8'd101},
|
||||||
{8'd10, 8'd60, 8'd80, 8'd50}
|
{8'd11, 8'd61, 8'd81, 8'd51}
|
||||||
};
|
};
|
||||||
|
|
||||||
// Instantiate UUT
|
// Instantiate UUT
|
||||||
|
|
|
@ -1,11 +1,11 @@
|
||||||
# TCL File Generated by Component Editor 18.1
|
# TCL File Generated by Component Editor 18.1
|
||||||
# Thu Dec 22 22:35:53 MSK 2022
|
# Sat Dec 24 02:15:19 MSK 2022
|
||||||
# DO NOT MODIFY
|
# DO NOT MODIFY
|
||||||
|
|
||||||
|
|
||||||
#
|
#
|
||||||
# sem "Semafor" v1.1
|
# sem "Semafor" v1.1
|
||||||
# 2022.12.22.22:35:53
|
# 2022.12.24.02:15:19
|
||||||
#
|
#
|
||||||
#
|
#
|
||||||
|
|
||||||
|
|
|
@ -1,11 +1,11 @@
|
||||||
# TCL File Generated by Component Editor 18.1
|
# TCL File Generated by Component Editor 18.1
|
||||||
# Wed Dec 21 21:00:10 MSK 2022
|
# Sat Dec 24 01:52:10 MSK 2022
|
||||||
# DO NOT MODIFY
|
# DO NOT MODIFY
|
||||||
|
|
||||||
|
|
||||||
#
|
#
|
||||||
# sem "Semafor" v1.1
|
# sem "Semafor" v1.1
|
||||||
# 2022.12.21.21:00:10
|
# 2022.12.24.01:52:10
|
||||||
#
|
#
|
||||||
#
|
#
|
||||||
|
|
||||||
|
@ -163,7 +163,7 @@ set_interface_property ram_slave CMSIS_SVD_VARIABLES ""
|
||||||
set_interface_property ram_slave SVD_ADDRESS_GROUP ""
|
set_interface_property ram_slave SVD_ADDRESS_GROUP ""
|
||||||
|
|
||||||
add_interface_port ram_slave ram_wr write Input 1
|
add_interface_port ram_slave ram_wr write Input 1
|
||||||
add_interface_port ram_slave ram_addr address Input 2
|
add_interface_port ram_slave ram_addr address Input 4
|
||||||
add_interface_port ram_slave ram_wrdata writedata Input 32
|
add_interface_port ram_slave ram_wrdata writedata Input 32
|
||||||
set_interface_assignment ram_slave embeddedsw.configuration.isFlash 0
|
set_interface_assignment ram_slave embeddedsw.configuration.isFlash 0
|
||||||
set_interface_assignment ram_slave embeddedsw.configuration.isMemoryDevice 0
|
set_interface_assignment ram_slave embeddedsw.configuration.isMemoryDevice 0
|
||||||
|
|
|
@ -1,11 +1,11 @@
|
||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
|
<EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
|
||||||
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
|
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
|
||||||
<!-- 2022.12.22.22:38:31 -->
|
<!-- 2022.12.24.02:16:30 -->
|
||||||
<!-- A collection of modules and connections -->
|
<!-- A collection of modules and connections -->
|
||||||
<parameter name="AUTO_GENERATION_ID">
|
<parameter name="AUTO_GENERATION_ID">
|
||||||
<type>java.lang.Integer</type>
|
<type>java.lang.Integer</type>
|
||||||
<value>1671734311</value>
|
<value>1671833790</value>
|
||||||
<derived>false</derived>
|
<derived>false</derived>
|
||||||
<enabled>true</enabled>
|
<enabled>true</enabled>
|
||||||
<visible>false</visible>
|
<visible>false</visible>
|
||||||
|
|
|
@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</table>
|
</table>
|
||||||
<table class="blueBar">
|
<table class="blueBar">
|
||||||
<tr>
|
<tr>
|
||||||
<td class="l">2022.12.22.22:37:23</td>
|
<td class="l">2022.12.24.02:16:30</td>
|
||||||
<td class="r">Datasheet</td>
|
<td class="r">Datasheet</td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
|
@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</div>
|
</div>
|
||||||
<table class="blueBar">
|
<table class="blueBar">
|
||||||
<tr>
|
<tr>
|
||||||
<td class="l">generation took 0,01 seconds</td>
|
<td class="l">generation took 0,00 seconds</td>
|
||||||
<td class="r">rendering took 0,08 seconds</td>
|
<td class="r">rendering took 0,03 seconds</td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
</body>
|
</body>
|
||||||
|
|
File diff suppressed because one or more lines are too long
|
@ -1,7 +1,7 @@
|
||||||
<?xml version="1.0" encoding="UTF-8"?>
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
<EnsembleReport name="niosII" kind="system" version="18.1" fabric="QSYS">
|
<EnsembleReport name="niosII" kind="system" version="18.1" fabric="QSYS">
|
||||||
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
|
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
|
||||||
<!-- 2022.12.22.22:38:00 -->
|
<!-- 2022.12.24.02:16:58 -->
|
||||||
<!-- A collection of modules and connections -->
|
<!-- A collection of modules and connections -->
|
||||||
<parameter name="clockCrossingAdapter">
|
<parameter name="clockCrossingAdapter">
|
||||||
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
|
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
|
||||||
|
@ -53,7 +53,7 @@
|
||||||
</parameter>
|
</parameter>
|
||||||
<parameter name="generationId">
|
<parameter name="generationId">
|
||||||
<type>int</type>
|
<type>int</type>
|
||||||
<value>1671734242</value>
|
<value>1671833790</value>
|
||||||
<derived>false</derived>
|
<derived>false</derived>
|
||||||
<enabled>true</enabled>
|
<enabled>true</enabled>
|
||||||
<visible>true</visible>
|
<visible>true</visible>
|
||||||
|
@ -12925,5 +12925,5 @@ parameters are a RESULT of the module parameters. -->
|
||||||
<version>18.1</version>
|
<version>18.1</version>
|
||||||
</plugin>
|
</plugin>
|
||||||
<reportVersion>18.1 625</reportVersion>
|
<reportVersion>18.1 625</reportVersion>
|
||||||
<uniqueIdentifier>7A31C1D08890000001853B204A2B</uniqueIdentifier>
|
<uniqueIdentifier>7A31C1D0889000000185410F37E7</uniqueIdentifier>
|
||||||
</EnsembleReport>
|
</EnsembleReport>
|
||||||
|
|
|
@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1"
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1"
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys"
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys"
|
||||||
set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"]
|
set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"]
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671734242"
|
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671833790"
|
||||||
set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"]
|
set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"]
|
||||||
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"]
|
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"]
|
||||||
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"]
|
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"]
|
||||||
|
@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTczNDI0Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTgzMzc5MA==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U="
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U="
|
||||||
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
|
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
|
||||||
|
|
|
@ -17,8 +17,13 @@ module dec
|
||||||
output logic red, yellow, green
|
output logic red, yellow, green
|
||||||
);
|
);
|
||||||
|
|
||||||
|
typedef enum logic [1:0] {RED, YELLOW, BLINK, GREEN} FSMStates;
|
||||||
|
|
||||||
logic run;
|
logic run;
|
||||||
logic [1:0] divider;
|
logic [1:0] divider;
|
||||||
|
logic [1:0] state;
|
||||||
|
logic [31:0] greenSaved;
|
||||||
|
logic [31:0] greenCount;
|
||||||
|
|
||||||
logic [m-1:0] divisor;
|
logic [m-1:0] divisor;
|
||||||
logic [1:0] contr;
|
logic [1:0] contr;
|
||||||
|
@ -27,17 +32,12 @@ module dec
|
||||||
logic enacnt;
|
logic enacnt;
|
||||||
|
|
||||||
//control slave logic
|
//control slave logic
|
||||||
always_ff @ (posedge clk or negedge clrn)
|
always_ff @ (posedge clk or negedge clrn) begin
|
||||||
begin
|
if (!clrn) begin
|
||||||
if (!clrn)
|
|
||||||
begin
|
|
||||||
run <= 0;
|
run <= 0;
|
||||||
divider <= 0;
|
divider <= 0;
|
||||||
end
|
end else begin
|
||||||
else
|
if (ctl_wr) begin
|
||||||
begin
|
|
||||||
if (ctl_wr)
|
|
||||||
begin
|
|
||||||
case (ctl_addr)
|
case (ctl_addr)
|
||||||
1'b0: run <= ctl_wrdata[0];
|
1'b0: run <= ctl_wrdata[0];
|
||||||
1'b1: divider <= ctl_wrdata[1:0];
|
1'b1: divider <= ctl_wrdata[1:0];
|
||||||
|
@ -46,8 +46,7 @@ module dec
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
always_comb
|
always_comb begin
|
||||||
begin
|
|
||||||
case (ctl_addr)
|
case (ctl_addr)
|
||||||
1'b0: ctl_rddata = {31'b0,run};
|
1'b0: ctl_rddata = {31'b0,run};
|
||||||
1'b1: ctl_rddata = {30'b0,divider};
|
1'b1: ctl_rddata = {30'b0,divider};
|
||||||
|
@ -56,70 +55,96 @@ module dec
|
||||||
end
|
end
|
||||||
|
|
||||||
//semaphore logic
|
//semaphore logic
|
||||||
|
always_ff @ (posedge clk or negedge clrn) begin
|
||||||
always_ff @ (posedge clk or negedge clrn)
|
if (!clrn)
|
||||||
begin
|
cntdiv <= 0;
|
||||||
if (!clrn) cntdiv<=0;
|
else begin
|
||||||
else
|
if (train | ~run)
|
||||||
begin
|
cntdiv<=0;
|
||||||
if (train | ~run) cntdiv<=0;
|
else begin
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (enacnt) cntdiv<=0;
|
if (enacnt) cntdiv<=0;
|
||||||
else cntdiv<=cntdiv+1;
|
else cntdiv<=cntdiv+1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
always_comb
|
// we don't enable counters, if color is green
|
||||||
begin
|
always_comb begin
|
||||||
enacnt=(cntdiv==divisor);
|
enacnt = ((cntdiv == divisor) && !(colors == 3'b001));
|
||||||
end
|
end
|
||||||
|
|
||||||
always_ff @ (posedge clk or negedge clrn)
|
always_ff @ (posedge clk or negedge clrn) begin
|
||||||
begin
|
if (!clrn) begin
|
||||||
if (!clrn)
|
colors <= 3'b001;
|
||||||
begin
|
state <= GREEN;
|
||||||
colors <= 3'b100;
|
greenCount <= 32'd0;
|
||||||
|
end else begin
|
||||||
|
if (~run) begin
|
||||||
|
colors <= 3'b001;
|
||||||
|
state <= GREEN;
|
||||||
end
|
end
|
||||||
else
|
if (train) begin
|
||||||
begin
|
|
||||||
if (train | ~run)
|
|
||||||
begin
|
|
||||||
colors <= 3'b100;
|
colors <= 3'b100;
|
||||||
|
state <= RED;
|
||||||
|
greenSaved <= divisor;
|
||||||
|
greenCount <= divisor;
|
||||||
|
end else begin
|
||||||
|
case (state)
|
||||||
|
RED: begin
|
||||||
|
colors <= 3'b100;
|
||||||
|
if (enacnt) begin
|
||||||
|
state <= state + 1'b1;
|
||||||
|
greenSaved <= divisor;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
YELLOW: begin
|
||||||
|
colors <= 3'b010;
|
||||||
|
if (enacnt) begin
|
||||||
|
state <= state + 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
BLINK: begin
|
||||||
|
if (enacnt) begin
|
||||||
|
state <= state + 1'b1;
|
||||||
|
end
|
||||||
|
if (greenSaved[0] == 0) begin
|
||||||
|
colors <= 3'b011;
|
||||||
|
end else begin
|
||||||
|
greenCount <= greenCount - 1'b1;
|
||||||
|
if (greenCount == 32'd0) begin
|
||||||
|
colors[1] <= ~colors[1];
|
||||||
|
greenCount <= greenSaved;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
GREEN: begin
|
||||||
|
if (enacnt) begin
|
||||||
|
state <= state + 1'b1;
|
||||||
|
end
|
||||||
|
colors <= 3'b001;
|
||||||
end
|
end
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (enacnt)
|
|
||||||
begin
|
|
||||||
case (colors)
|
|
||||||
3'b100: colors <= 3'b010;
|
|
||||||
3'b010: colors <= 3'b011;
|
|
||||||
3'b011: colors <= 3'b001;
|
|
||||||
3'b001: colors <= 3'b001;
|
|
||||||
default: colors <= 3'b100;
|
default: colors <= 3'b100;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
assign contr = state;
|
||||||
|
// always_comb begin
|
||||||
always_comb
|
// case (state)
|
||||||
begin
|
// 2'b00: contr = 2'b00;
|
||||||
case (colors)
|
// 2'b01: contr = 2'b01;
|
||||||
3'b100: contr = 2'b00;
|
// 2'b10: contr = 2'b10;
|
||||||
3'b010: contr = 2'b01;
|
// 2'b11: contr = 2'b11;
|
||||||
3'b011: contr = 2'b10;
|
// default : contr = 2'b00;
|
||||||
3'b001: contr = 2'b11;
|
// endcase
|
||||||
default : contr = 2'b00;
|
// end
|
||||||
endcase
|
|
||||||
end
|
|
||||||
|
|
||||||
assign red = colors[2];
|
assign red = colors[2];
|
||||||
assign yellow = colors[1];
|
assign yellow = colors[1];
|
||||||
assign green = colors[0];
|
assign green = colors[0];
|
||||||
|
|
||||||
periodram b2v_inst3(
|
periodram b2v_inst3
|
||||||
|
(
|
||||||
.clock(clk),
|
.clock(clk),
|
||||||
.data (ram_wrdata),
|
.data (ram_wrdata),
|
||||||
.wraddress (ram_addr),
|
.wraddress (ram_addr),
|
||||||
|
|
|
@ -94,7 +94,7 @@
|
||||||
# within the Quartus project, and generate a unified
|
# within the Quartus project, and generate a unified
|
||||||
# script which supports all the Altera IP within the design.
|
# script which supports all the Altera IP within the design.
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# ACDS 18.1 625 win32 2022.12.22.22:39:16
|
# ACDS 18.1 625 win32 2022.12.24.02:16:20
|
||||||
|
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# Initialize variables
|
# Initialize variables
|
||||||
|
|
|
@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</table>
|
</table>
|
||||||
<table class="blueBar">
|
<table class="blueBar">
|
||||||
<tr>
|
<tr>
|
||||||
<td class="l">2022.12.22.22:38:31</td>
|
<td class="l">2022.12.24.02:15:37</td>
|
||||||
<td class="r">Datasheet</td>
|
<td class="r">Datasheet</td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
|
@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</div>
|
</div>
|
||||||
<table class="blueBar">
|
<table class="blueBar">
|
||||||
<tr>
|
<tr>
|
||||||
<td class="l">generation took 0,00 seconds</td>
|
<td class="l">generation took 0,01 seconds</td>
|
||||||
<td class="r">rendering took 0,04 seconds</td>
|
<td class="r">rendering took 0,07 seconds</td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
</body>
|
</body>
|
||||||
|
|
|
@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</table>
|
</table>
|
||||||
<table class="blueBar">
|
<table class="blueBar">
|
||||||
<tr>
|
<tr>
|
||||||
<td class="l">2022.12.22.22:38:42</td>
|
<td class="l">2022.12.24.02:15:47</td>
|
||||||
<td class="r">Datasheet</td>
|
<td class="r">Datasheet</td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
|
@ -211,7 +211,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
<table>
|
<table>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="parametername">AUTO_GENERATION_ID</td>
|
<td class="parametername">AUTO_GENERATION_ID</td>
|
||||||
<td class="parametervalue">1671734322</td>
|
<td class="parametervalue">1671833747</td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr>
|
<tr>
|
||||||
<td class="parametername">AUTO_UNIQUE_ID</td>
|
<td class="parametername">AUTO_UNIQUE_ID</td>
|
||||||
|
@ -2359,8 +2359,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
||||||
</div>
|
</div>
|
||||||
<table class="blueBar">
|
<table class="blueBar">
|
||||||
<tr>
|
<tr>
|
||||||
<td class="l">generation took 0,02 seconds</td>
|
<td class="l">generation took 0,01 seconds</td>
|
||||||
<td class="r">rendering took 0,05 seconds</td>
|
<td class="r">rendering took 0,06 seconds</td>
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
</body>
|
</body>
|
||||||
|
|
|
@ -7,7 +7,8 @@ module niosII_tb (
|
||||||
reg train;
|
reg train;
|
||||||
wire red, yellow, green;
|
wire red, yellow, green;
|
||||||
|
|
||||||
niosII niosii_inst (
|
niosII niosii_inst
|
||||||
|
(
|
||||||
.clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk
|
.clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk
|
||||||
.reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
|
.reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
|
||||||
.sem_export_train (train), // sem_export.train
|
.sem_export_train (train), // sem_export.train
|
||||||
|
@ -16,17 +17,23 @@ module niosII_tb (
|
||||||
.sem_export_green (green) // .green
|
.sem_export_green (green) // .green
|
||||||
);
|
);
|
||||||
|
|
||||||
altera_avalon_clock_source #(
|
altera_avalon_clock_source
|
||||||
|
#(
|
||||||
.CLOCK_RATE (50000000),
|
.CLOCK_RATE (50000000),
|
||||||
.CLOCK_UNIT (1)
|
.CLOCK_UNIT (1)
|
||||||
) niosii_inst_clk_bfm (
|
)
|
||||||
|
niosii_inst_clk_bfm
|
||||||
|
(
|
||||||
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
|
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
|
||||||
);
|
);
|
||||||
|
|
||||||
altera_avalon_reset_source #(
|
altera_avalon_reset_source
|
||||||
|
#(
|
||||||
.ASSERT_HIGH_RESET (0),
|
.ASSERT_HIGH_RESET (0),
|
||||||
.INITIAL_RESET_CYCLES (50)
|
.INITIAL_RESET_CYCLES (50)
|
||||||
) niosii_inst_reset_bfm (
|
)
|
||||||
|
niosii_inst_reset_bfm
|
||||||
|
(
|
||||||
.reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
|
.reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
|
||||||
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
|
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
|
||||||
);
|
);
|
||||||
|
@ -39,6 +46,18 @@ module niosII_tb (
|
||||||
train = 1;
|
train = 1;
|
||||||
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
|
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||||
train = 0;
|
train = 0;
|
||||||
|
repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||||
|
train = 1;
|
||||||
|
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||||
|
train = 0;
|
||||||
|
repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||||
|
train = 1;
|
||||||
|
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||||
|
train = 0;
|
||||||
|
repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||||
|
train = 1;
|
||||||
|
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
|
||||||
|
train = 0;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
@ -12,7 +12,7 @@
|
||||||
# or its authorized distributors. Please refer to the applicable
|
# or its authorized distributors. Please refer to the applicable
|
||||||
# agreement for further details.
|
# agreement for further details.
|
||||||
|
|
||||||
# ACDS 18.1 625 win32 2022.12.22.22:39:16
|
# ACDS 18.1 625 win32 2022.12.24.02:16:20
|
||||||
|
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# vcs - auto-generated simulation script
|
# vcs - auto-generated simulation script
|
||||||
|
@ -94,7 +94,7 @@
|
||||||
# within the Quartus project, and generate a unified
|
# within the Quartus project, and generate a unified
|
||||||
# script which supports all the Altera IP within the design.
|
# script which supports all the Altera IP within the design.
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# ACDS 18.1 625 win32 2022.12.22.22:39:16
|
# ACDS 18.1 625 win32 2022.12.24.02:16:20
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# initialize variables
|
# initialize variables
|
||||||
TOP_LEVEL_NAME="niosII_tb"
|
TOP_LEVEL_NAME="niosII_tb"
|
||||||
|
|
|
@ -12,7 +12,7 @@
|
||||||
# or its authorized distributors. Please refer to the applicable
|
# or its authorized distributors. Please refer to the applicable
|
||||||
# agreement for further details.
|
# agreement for further details.
|
||||||
|
|
||||||
# ACDS 18.1 625 win32 2022.12.22.22:39:16
|
# ACDS 18.1 625 win32 2022.12.24.02:16:20
|
||||||
|
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# vcsmx - auto-generated simulation script
|
# vcsmx - auto-generated simulation script
|
||||||
|
@ -107,7 +107,7 @@
|
||||||
# within the Quartus project, and generate a unified
|
# within the Quartus project, and generate a unified
|
||||||
# script which supports all the Altera IP within the design.
|
# script which supports all the Altera IP within the design.
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# ACDS 18.1 625 win32 2022.12.22.22:39:16
|
# ACDS 18.1 625 win32 2022.12.24.02:16:20
|
||||||
# ----------------------------------------
|
# ----------------------------------------
|
||||||
# initialize variables
|
# initialize variables
|
||||||
TOP_LEVEL_NAME="niosII_tb"
|
TOP_LEVEL_NAME="niosII_tb"
|
||||||
|
|
|
@ -1,12 +1,12 @@
|
||||||
# system info niosII_tb on 2022.12.22.22:39:13
|
# system info niosII_tb on 2022.12.24.02:16:19
|
||||||
system_info:
|
system_info:
|
||||||
name,value
|
name,value
|
||||||
DEVICE,EP4CE115F29C7
|
DEVICE,EP4CE115F29C7
|
||||||
DEVICE_FAMILY,Cyclone IV E
|
DEVICE_FAMILY,Cyclone IV E
|
||||||
GENERATION_ID,1671734322
|
GENERATION_ID,1671833747
|
||||||
#
|
#
|
||||||
#
|
#
|
||||||
# Files generated for niosII_tb on 2022.12.22.22:39:13
|
# Files generated for niosII_tb on 2022.12.24.02:16:19
|
||||||
files:
|
files:
|
||||||
filepath,kind,attributes,module,is_top
|
filepath,kind,attributes,module,is_top
|
||||||
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
|
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
|
||||||
|
|
|
Binary file not shown.
Binary file not shown.
|
@ -751,8 +751,8 @@ alt_after_alt_main:
|
||||||
244: 003fff06 br 244 <__alt_data_end+0xfffe0244>
|
244: 003fff06 br 244 <__alt_data_end+0xfffe0244>
|
||||||
|
|
||||||
00000248 <main>:
|
00000248 <main>:
|
||||||
{0x000000f0, 0x000000f0, 0x000000f0, 0x00000010},
|
{0x000000f1, 0x000000f1, 0x000000f1, 0x00000011},
|
||||||
{0x000000fa, 0x000000f0, 0x000000f0, 0x00000010}
|
{0x000000d1, 0x000000f1, 0x000000f1, 0x00000011}
|
||||||
};
|
};
|
||||||
|
|
||||||
int main()
|
int main()
|
||||||
|
|
|
@ -5630,14 +5630,14 @@
|
||||||
@15FD 00000020
|
@15FD 00000020
|
||||||
@15FE 00000010
|
@15FE 00000010
|
||||||
@15FF 00000010
|
@15FF 00000010
|
||||||
@1600 000000F0
|
@1600 000000F1
|
||||||
@1601 000000F0
|
@1601 000000F1
|
||||||
@1602 000000F0
|
@1602 000000F1
|
||||||
@1603 00000010
|
@1603 00000011
|
||||||
@1604 000000FA
|
@1604 000000D1
|
||||||
@1605 000000F0
|
@1605 000000F1
|
||||||
@1606 000000F0
|
@1606 000000F1
|
||||||
@1607 00000010
|
@1607 00000011
|
||||||
@1608 64616552
|
@1608 64616552
|
||||||
@1609 00000079
|
@1609 00000079
|
||||||
@160A 0000000A
|
@160A 0000000A
|
||||||
|
|
|
@ -703,7 +703,7 @@
|
||||||
:2015E800003FB6060005883A003FFB06DEFFFD04DF000215DF000204E13FFF150001883A31
|
:2015E800003FB6060005883A003FFB06DEFFFD04DF000215DF000204E13FFF150001883A31
|
||||||
:2015F000E0BFFF17E0BFFE15E0BFFE1710000226002AF07000000106002AF0B0003FFF06E9
|
:2015F000E0BFFF17E0BFFE15E0BFFE1710000226002AF07000000106002AF0B0003FFF06E9
|
||||||
:2015F80000000010000000100000000500000010000000100000002000000010000000104E
|
:2015F80000000010000000100000000500000010000000100000002000000010000000104E
|
||||||
:20160000000000F0000000F0000000F000000010000000FA000000F0000000F00000001000
|
:20160000000000F1000000F1000000F100000011000000D1000000F1000000F10000001122
|
||||||
:2016080064616552000000790000000A000000437665642F6C756E2F0000006C7665642FBA
|
:2016080064616552000000790000000A000000437665642F6C756E2F0000006C7665642FBA
|
||||||
:2016100061746A2F61755F67000074727665642F61746A2F61755F6700007472000000006C
|
:2016100061746A2F61755F67000074727665642F61746A2F61755F6700007472000000006C
|
||||||
:2016180000005B4800005BB000005C18000000000000000000000000000000000000000090
|
:2016180000005B4800005BB000005C18000000000000000000000000000000000000000090
|
||||||
|
|
|
@ -8,8 +8,8 @@
|
||||||
const alt_u32 divisors[TIME_SETS][TIME_STATES] = {
|
const alt_u32 divisors[TIME_SETS][TIME_STATES] = {
|
||||||
{0x00000010, 0x00000010, 0x00000005, 0x00000010},
|
{0x00000010, 0x00000010, 0x00000005, 0x00000010},
|
||||||
{0x00000010, 0x00000020, 0x00000010, 0x00000010},
|
{0x00000010, 0x00000020, 0x00000010, 0x00000010},
|
||||||
{0x000000f0, 0x000000f0, 0x000000f0, 0x00000010},
|
{0x000000f1, 0x000000f1, 0x000000f1, 0x00000011},
|
||||||
{0x000000fa, 0x000000f0, 0x000000f0, 0x00000010}
|
{0x000000d1, 0x000000f1, 0x000000f1, 0x00000011}
|
||||||
};
|
};
|
||||||
|
|
||||||
int main()
|
int main()
|
||||||
|
|
|
@ -1 +1,8 @@
|
||||||
# Reading C:/Software/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl
|
# Reading C:/Software/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl
|
||||||
|
# vsim -gui null_sim.mpf
|
||||||
|
# Start time: 01:19:59 on Dec 24,2022
|
||||||
|
# ** Error (suppressible): (vsim-19) Failed to access library 'null_sim' at "null_sim".
|
||||||
|
# No such file or directory. (errno = ENOENT)
|
||||||
|
# Error loading design
|
||||||
|
# End time: 01:19:59 on Dec 24,2022, Elapsed time: 0:00:00
|
||||||
|
# Errors: 1, Warnings: 0
|
||||||
|
|
|
@ -2,8 +2,8 @@
|
||||||
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
|
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
|
||||||
<BspType>hal</BspType>
|
<BspType>hal</BspType>
|
||||||
<BspVersion>default</BspVersion>
|
<BspVersion>default</BspVersion>
|
||||||
<BspGeneratedTimeStamp>22.12.2022 22:44:16</BspGeneratedTimeStamp>
|
<BspGeneratedTimeStamp>24.12.2022 2:19:40</BspGeneratedTimeStamp>
|
||||||
<BspGeneratedUnixTimeStamp>1671734657095</BspGeneratedUnixTimeStamp>
|
<BspGeneratedUnixTimeStamp>1671833980256</BspGeneratedUnixTimeStamp>
|
||||||
<BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation>
|
<BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation>
|
||||||
<BspSettingsFile>settings.bsp</BspSettingsFile>
|
<BspSettingsFile>settings.bsp</BspSettingsFile>
|
||||||
<SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile>
|
<SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile>
|
||||||
|
|
|
@ -22,10 +22,10 @@
|
||||||
<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
|
<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr mode="wrap">
|
<tr mode="wrap">
|
||||||
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>22.12.2022 22:44:16</td>
|
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>24.12.2022 2:19:40</td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr mode="wrap">
|
<tr mode="wrap">
|
||||||
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671734657095</td>
|
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671833980256</td>
|
||||||
</tr>
|
</tr>
|
||||||
<tr mode="wrap">
|
<tr mode="wrap">
|
||||||
<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td>
|
<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td>
|
||||||
|
|
Loading…
Reference in New Issue