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simulated individual, looks ok

This commit is contained in:
Ivan I. Ovchinnikov 2022-12-24 02:08:20 +03:00
parent 881e124d27
commit b86b8e55dc
28 changed files with 622 additions and 417 deletions
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139
HDL/dec.sv
View File

@ -1,6 +1,6 @@
module dec
#(m = 32)
(
#(m = 32)
(
//clock and reset
input logic clk, clrn,
//control slave
@ -15,10 +15,15 @@ module dec
//external ports
input logic train,
output logic red, yellow, green
);
);
typedef enum logic [1:0] {RED, YELLOW, BLINK, GREEN} FSMStates;
logic run;
logic [1:0] divider;
logic [1:0] state;
logic [31:0] greenSaved;
logic [31:0] greenCount;
logic [m-1:0] divisor;
logic [1:0] contr;
@ -27,17 +32,12 @@ module dec
logic enacnt;
//control slave logic
always_ff @ (posedge clk or negedge clrn)
begin
if (!clrn)
begin
always_ff @ (posedge clk or negedge clrn) begin
if (!clrn) begin
run <= 0;
divider <= 0;
end
else
begin
if (ctl_wr)
begin
end else begin
if (ctl_wr) begin
case (ctl_addr)
1'b0: run <= ctl_wrdata[0];
1'b1: divider <= ctl_wrdata[1:0];
@ -46,8 +46,7 @@ module dec
end
end
always_comb
begin
always_comb begin
case (ctl_addr)
1'b0: ctl_rddata = {31'b0,run};
1'b1: ctl_rddata = {30'b0,divider};
@ -56,70 +55,96 @@ module dec
end
//semaphore logic
always_ff @ (posedge clk or negedge clrn)
begin
if (!clrn) cntdiv<=0;
else
begin
if (train | ~run) cntdiv<=0;
else
begin
always_ff @ (posedge clk or negedge clrn) begin
if (!clrn)
cntdiv <= 0;
else begin
if (train | ~run)
cntdiv<=0;
else begin
if (enacnt) cntdiv<=0;
else cntdiv<=cntdiv+1;
end
end
end
always_comb
begin
enacnt=(cntdiv==divisor);
// we don't enable counters, if color is green
always_comb begin
enacnt = ((cntdiv == divisor) && !(colors == 3'b001));
end
always_ff @ (posedge clk or negedge clrn)
begin
if (!clrn)
begin
colors <= 3'b100;
always_ff @ (posedge clk or negedge clrn) begin
if (!clrn) begin
colors <= 3'b001;
state <= GREEN;
greenCount <= 32'd0;
end else begin
if (~run) begin
colors <= 3'b001;
state <= GREEN;
end
else
begin
if (train | ~run)
begin
if (train) begin
colors <= 3'b100;
state <= RED;
greenSaved <= divisor;
greenCount <= divisor;
end else begin
case (state)
RED: begin
colors <= 3'b100;
if (enacnt) begin
state <= state + 1'b1;
greenSaved <= divisor;
end
end
YELLOW: begin
colors <= 3'b010;
if (enacnt) begin
state <= state + 1'b1;
end
end
BLINK: begin
if (enacnt) begin
state <= state + 1'b1;
end
if (greenSaved[0] == 0) begin
colors <= 3'b011;
end else begin
greenCount <= greenCount - 1'b1;
if (greenCount == 32'd0) begin
colors[1] <= ~colors[1];
greenCount <= greenSaved;
end
end
end
GREEN: begin
if (enacnt) begin
state <= state + 1'b1;
end
colors <= 3'b001;
end
else
begin
if (enacnt)
begin
case (colors)
3'b100: colors <= 3'b010;
3'b010: colors <= 3'b011;
3'b011: colors <= 3'b001;
3'b001: colors <= 3'b001;
default: colors <= 3'b100;
endcase
end
end
end
end
always_comb
begin
case (colors)
3'b100: contr = 2'b00;
3'b010: contr = 2'b01;
3'b011: contr = 2'b10;
3'b001: contr = 2'b11;
default : contr = 2'b00;
endcase
end
assign contr = state;
// always_comb begin
// case (state)
// 2'b00: contr = 2'b00;
// 2'b01: contr = 2'b01;
// 2'b10: contr = 2'b10;
// 2'b11: contr = 2'b11;
// default : contr = 2'b00;
// endcase
// end
assign red = colors[2];
assign yellow = colors[1];
assign green = colors[0];
periodram b2v_inst3(
periodram b2v_inst3
(
.clock(clk),
.data (ram_wrdata),
.wraddress (ram_addr),

128
Testbench/dec/#dec_tb.sv# Normal file
View File

@ -0,0 +1,128 @@
`timescale 1 ns/1 ns
module dec_tb();
// Wires and variables to connect to UUT (unit under test)
logic clk, clrn, train;
logic r, y, g;
logic [1:0] div;
logic ctl_wr, ctl_rd;
logic ctl_addr;
logic [31:0] ctl_wrdata;
logic [31:0] ctl_rddata;
logic ram_wr;
logic [3:0] ram_addr;
logic [31:0] ram_wrdata;
logic [31:0] divisor[3:0] = {
{8'd10, 8'd70, 8'd50, 8'd20},
{8'd10, 8'd30, 8'd40, 8'd30},
{8'd10, 8'd30, 8'd10, 8'd100},
{8'd10, 8'd60, 8'd80, 8'd50}
};
// Instantiate UUT
dec my_sem(
.clk(clk), .clrn(clrn),
.ctl_wr(ctl_wr), .ctl_rd(ctl_rd),
.ctl_addr(ctl_addr), .ctl_wrdata(ctl_wrdata), .ctl_rddata(ctl_rddata),
.ram_wr(ram_wr),
.ram_addr(ram_addr), .ram_wrdata(ram_wrdata),
.train(train), .red(r), .yellow(y), .green(g)
);
// Clock definition
initial begin
clk = 0;
forever #10 clk = ~clk;
end
// Divisor and train definition
initial begin
//initial reset
clrn = 0;
div = 0;
train = 0;
//take reset off
@(negedge clk) clrn = 1;
//configure semaphore
for (int i=0; i<4; i++) write_ram_transaction(i,divisor[i]); //write divisor RAM
write_reg_transaction(1,div); //write initial divisor
write_reg_transaction(0,1); //enable semaphore
//run trains
repeat (4)
begin
repeat (10) @(posedge clk);
train=1;
repeat (4) @(posedge clk);
train=0;
wait ({r,y,g}==3'b001);
repeat (10) @(posedge clk);
write_reg_transaction(1,div);
div=div+1;
end
//wait a little
repeat (10) @(posedge clk);
$stop;
end
//Single register write transaction task
task write_reg_transaction;
//input signals
input [1:0] offs;
input [31:0] val;
//transaction implementation
begin
@(posedge clk);
//assert signals for one clock cycle
ctl_wr = 1;
ctl_addr = offs;
ctl_wrdata = val;
@(posedge clk);
//deassert signals
ctl_wr = 0;
ctl_addr = 'bx;
ctl_wrdata = 'bx;
end
endtask
//Single register read transaction task
task read_reg_transaction;
//input signals
input [1:0] offs;
output [31:0] val;
//transaction implementation
begin
@(posedge clk);
//assert signals for one clock cycle
ctl_rd = 1;
ctl_addr = offs;
@(posedge clk);
val = ctl_rddata;
//deassert signals
ctl_rd = 0;
ctl_addr = 'bx;
end
endtask
//RAM write transaction task
task write_ram_transaction;
//input signals
input [1:0] offs;
input [31:0] val;
//transaction implementation
begin
@(posedge clk);
//assert signals for one clock cycle
ram_wr = 1;
ram_addr = offs;
ram_wrdata = val;
@(posedge clk);
//deassert signals
ram_wr = 0;
ram_addr = 'bx;
ram_wrdata = 'bx;
end
endtask
endmodule

1
Testbench/dec/dec.qsf
View File

@ -65,4 +65,5 @@ set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dec_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb
set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb
set_global_assignment -name HEX_FILE periodram.hex
set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT simulation/modelsim/wave.do -section_id eda_simulation
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

8
Testbench/dec/dec_tb.sv
View File

@ -15,10 +15,10 @@ module dec_tb();
logic [31:0] ram_wrdata;
logic [31:0] divisor[3:0] = {
{8'd10, 8'd70, 8'd50, 8'd20},
{8'd10, 8'd30, 8'd40, 8'd30},
{8'd10, 8'd30, 8'd10, 8'd100},
{8'd10, 8'd60, 8'd80, 8'd50}
{8'd11, 8'd71, 8'd51, 8'd21},
{8'd11, 8'd31, 8'd41, 8'd31},
{8'd11, 8'd31, 8'd11, 8'd101},
{8'd11, 8'd61, 8'd81, 8'd51}
};
// Instantiate UUT

4
Top/Semafor_hw.tcl
View File

@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 18.1
# Thu Dec 22 22:35:53 MSK 2022
# Sat Dec 24 02:15:19 MSK 2022
# DO NOT MODIFY
#
# sem "Semafor" v1.1
# 2022.12.22.22:35:53
# 2022.12.24.02:15:19
#
#

6
Top/Semafor_hw.tcl~
View File

@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 18.1
# Wed Dec 21 21:00:10 MSK 2022
# Sat Dec 24 01:52:10 MSK 2022
# DO NOT MODIFY
#
# sem "Semafor" v1.1
# 2022.12.21.21:00:10
# 2022.12.24.01:52:10
#
#
@ -163,7 +163,7 @@ set_interface_property ram_slave CMSIS_SVD_VARIABLES ""
set_interface_property ram_slave SVD_ADDRESS_GROUP ""
add_interface_port ram_slave ram_wr write Input 1
add_interface_port ram_slave ram_addr address Input 2
add_interface_port ram_slave ram_addr address Input 4
add_interface_port ram_slave ram_wrdata writedata Input 32
set_interface_assignment ram_slave embeddedsw.configuration.isFlash 0
set_interface_assignment ram_slave embeddedsw.configuration.isMemoryDevice 0

4
Top/niosII.sopcinfo
View File

@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2022.12.22.22:38:31 -->
<!-- 2022.12.24.02:16:30 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1671734311</value>
<value>1671833790</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>

6
Top/niosII/niosII.html
View File

@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table>
<table class="blueBar">
<tr>
<td class="l">2022.12.22.22:37:23</td>
<td class="l">2022.12.24.02:16:30</td>
<td class="r">Datasheet</td>
</tr>
</table>
@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0,01 seconds</td>
<td class="r">rendering took 0,08 seconds</td>
<td class="l">generation took 0,00 seconds</td>
<td class="r">rendering took 0,03 seconds</td>
</tr>
</table>
</body>

188
Top/niosII/niosII.xml
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File diff suppressed because one or more lines are too long

6
Top/niosII/synthesis/niosII.debuginfo
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@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="niosII" kind="system" version="18.1" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2022.12.22.22:38:00 -->
<!-- 2022.12.24.02:16:58 -->
<!-- A collection of modules and connections -->
<parameter name="clockCrossingAdapter">
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@ -53,7 +53,7 @@
</parameter>
<parameter name="generationId">
<type>int</type>
<value>1671734242</value>
<value>1671833790</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@ -12925,5 +12925,5 @@ parameters are a RESULT of the module parameters. -->
<version>18.1</version>
</plugin>
<reportVersion>18.1 625</reportVersion>
<uniqueIdentifier>7A31C1D08890000001853B204A2B</uniqueIdentifier>
<uniqueIdentifier>7A31C1D0889000000185410F37E7</uniqueIdentifier>
</EnsembleReport>

4
Top/niosII/synthesis/niosII.qip
View File

@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1"
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"]
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671734242"
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671833790"
set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"]
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"]
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"]
@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTczNDI0Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTgzMzc5MA==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U="
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="

139
Top/niosII/synthesis/submodules/dec.sv
View File

@ -1,6 +1,6 @@
module dec
#(m = 32)
(
#(m = 32)
(
//clock and reset
input logic clk, clrn,
//control slave
@ -15,10 +15,15 @@ module dec
//external ports
input logic train,
output logic red, yellow, green
);
);
typedef enum logic [1:0] {RED, YELLOW, BLINK, GREEN} FSMStates;
logic run;
logic [1:0] divider;
logic [1:0] state;
logic [31:0] greenSaved;
logic [31:0] greenCount;
logic [m-1:0] divisor;
logic [1:0] contr;
@ -27,17 +32,12 @@ module dec
logic enacnt;
//control slave logic
always_ff @ (posedge clk or negedge clrn)
begin
if (!clrn)
begin
always_ff @ (posedge clk or negedge clrn) begin
if (!clrn) begin
run <= 0;
divider <= 0;
end
else
begin
if (ctl_wr)
begin
end else begin
if (ctl_wr) begin
case (ctl_addr)
1'b0: run <= ctl_wrdata[0];
1'b1: divider <= ctl_wrdata[1:0];
@ -46,8 +46,7 @@ module dec
end
end
always_comb
begin
always_comb begin
case (ctl_addr)
1'b0: ctl_rddata = {31'b0,run};
1'b1: ctl_rddata = {30'b0,divider};
@ -56,70 +55,96 @@ module dec
end
//semaphore logic
always_ff @ (posedge clk or negedge clrn)
begin
if (!clrn) cntdiv<=0;
else
begin
if (train | ~run) cntdiv<=0;
else
begin
always_ff @ (posedge clk or negedge clrn) begin
if (!clrn)
cntdiv <= 0;
else begin
if (train | ~run)
cntdiv<=0;
else begin
if (enacnt) cntdiv<=0;
else cntdiv<=cntdiv+1;
end
end
end
always_comb
begin
enacnt=(cntdiv==divisor);
// we don't enable counters, if color is green
always_comb begin
enacnt = ((cntdiv == divisor) && !(colors == 3'b001));
end
always_ff @ (posedge clk or negedge clrn)
begin
if (!clrn)
begin
colors <= 3'b100;
always_ff @ (posedge clk or negedge clrn) begin
if (!clrn) begin
colors <= 3'b001;
state <= GREEN;
greenCount <= 32'd0;
end else begin
if (~run) begin
colors <= 3'b001;
state <= GREEN;
end
else
begin
if (train | ~run)
begin
if (train) begin
colors <= 3'b100;
state <= RED;
greenSaved <= divisor;
greenCount <= divisor;
end else begin
case (state)
RED: begin
colors <= 3'b100;
if (enacnt) begin
state <= state + 1'b1;
greenSaved <= divisor;
end
end
YELLOW: begin
colors <= 3'b010;
if (enacnt) begin
state <= state + 1'b1;
end
end
BLINK: begin
if (enacnt) begin
state <= state + 1'b1;
end
if (greenSaved[0] == 0) begin
colors <= 3'b011;
end else begin
greenCount <= greenCount - 1'b1;
if (greenCount == 32'd0) begin
colors[1] <= ~colors[1];
greenCount <= greenSaved;
end
end
end
GREEN: begin
if (enacnt) begin
state <= state + 1'b1;
end
colors <= 3'b001;
end
else
begin
if (enacnt)
begin
case (colors)
3'b100: colors <= 3'b010;
3'b010: colors <= 3'b011;
3'b011: colors <= 3'b001;
3'b001: colors <= 3'b001;
default: colors <= 3'b100;
endcase
end
end
end
end
always_comb
begin
case (colors)
3'b100: contr = 2'b00;
3'b010: contr = 2'b01;
3'b011: contr = 2'b10;
3'b001: contr = 2'b11;
default : contr = 2'b00;
endcase
end
assign contr = state;
// always_comb begin
// case (state)
// 2'b00: contr = 2'b00;
// 2'b01: contr = 2'b01;
// 2'b10: contr = 2'b10;
// 2'b11: contr = 2'b11;
// default : contr = 2'b00;
// endcase
// end
assign red = colors[2];
assign yellow = colors[1];
assign green = colors[0];
periodram b2v_inst3(
periodram b2v_inst3
(
.clock(clk),
.data (ram_wrdata),
.wraddress (ram_addr),

2
Top/niosII/testbench/mentor/msim_setup.tcl
View File

@ -94,7 +94,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 win32 2022.12.22.22:39:16
# ACDS 18.1 625 win32 2022.12.24.02:16:20
# ----------------------------------------
# Initialize variables

6
Top/niosII/testbench/niosII.html
View File

@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table>
<table class="blueBar">
<tr>
<td class="l">2022.12.22.22:38:31</td>
<td class="l">2022.12.24.02:15:37</td>
<td class="r">Datasheet</td>
</tr>
</table>
@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0,00 seconds</td>
<td class="r">rendering took 0,04 seconds</td>
<td class="l">generation took 0,01 seconds</td>
<td class="r">rendering took 0,07 seconds</td>
</tr>
</table>
</body>

8
Top/niosII/testbench/niosII_tb.html
View File

@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table>
<table class="blueBar">
<tr>
<td class="l">2022.12.22.22:38:42</td>
<td class="l">2022.12.24.02:15:47</td>
<td class="r">Datasheet</td>
</tr>
</table>
@ -211,7 +211,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table>
<tr>
<td class="parametername">AUTO_GENERATION_ID</td>
<td class="parametervalue">1671734322</td>
<td class="parametervalue">1671833747</td>
</tr>
<tr>
<td class="parametername">AUTO_UNIQUE_ID</td>
@ -2359,8 +2359,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0,02 seconds</td>
<td class="r">rendering took 0,05 seconds</td>
<td class="l">generation took 0,01 seconds</td>
<td class="r">rendering took 0,06 seconds</td>
</tr>
</table>
</body>

31
Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v
View File

@ -1,13 +1,14 @@
`timescale 1 ps / 1 ps
module niosII_tb (
);
);
wire niosii_inst_clk_bfm_clk_clk; // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk]
wire niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n
reg train;
wire red, yellow, green;
niosII niosii_inst (
niosII niosii_inst
(
.clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk
.reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
.sem_export_train (train), // sem_export.train
@ -16,17 +17,23 @@ module niosII_tb (
.sem_export_green (green) // .green
);
altera_avalon_clock_source #(
altera_avalon_clock_source
#(
.CLOCK_RATE (50000000),
.CLOCK_UNIT (1)
) niosii_inst_clk_bfm (
)
niosii_inst_clk_bfm
(
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
);
altera_avalon_reset_source #(
altera_avalon_reset_source
#(
.ASSERT_HIGH_RESET (0),
.INITIAL_RESET_CYCLES (50)
) niosii_inst_reset_bfm (
)
niosii_inst_reset_bfm
(
.reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
);
@ -39,6 +46,18 @@ module niosII_tb (
train = 1;
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
train = 0;
repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk);
train = 1;
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
train = 0;
repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk);
train = 1;
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
train = 0;
repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk);
train = 1;
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
train = 0;
end
end

4
Top/niosII/testbench/synopsys/vcs/vcs_setup.sh
View File

@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 18.1 625 win32 2022.12.22.22:39:16
# ACDS 18.1 625 win32 2022.12.24.02:16:20
# ----------------------------------------
# vcs - auto-generated simulation script
@ -94,7 +94,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 win32 2022.12.22.22:39:16
# ACDS 18.1 625 win32 2022.12.24.02:16:20
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="niosII_tb"

4
Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh
View File

@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 18.1 625 win32 2022.12.22.22:39:16
# ACDS 18.1 625 win32 2022.12.24.02:16:20
# ----------------------------------------
# vcsmx - auto-generated simulation script
@ -107,7 +107,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 win32 2022.12.22.22:39:16
# ACDS 18.1 625 win32 2022.12.24.02:16:20
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="niosII_tb"

6
Top/niosII_tb.csv
View File

@ -1,12 +1,12 @@
# system info niosII_tb on 2022.12.22.22:39:13
# system info niosII_tb on 2022.12.24.02:16:19
system_info:
name,value
DEVICE,EP4CE115F29C7
DEVICE_FAMILY,Cyclone IV E
GENERATION_ID,1671734322
GENERATION_ID,1671833747
#
#
# Files generated for niosII_tb on 2022.12.22.22:39:13
# Files generated for niosII_tb on 2022.12.24.02:16:19
files:
filepath,kind,attributes,module,is_top
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true

1 # system info niosII_tb on 2022.12.22.22:39:13 # system info niosII_tb on 2022.12.24.02:16:19
2 system_info: system_info:
3 name,value name,value
4 DEVICE,EP4CE115F29C7 DEVICE,EP4CE115F29C7
5 DEVICE_FAMILY,Cyclone IV E DEVICE_FAMILY,Cyclone IV E
6 GENERATION_ID,1671734322 GENERATION_ID,1671833747
7 # #
8 # #
9 # Files generated for niosII_tb on 2022.12.22.22:39:13 # Files generated for niosII_tb on 2022.12.24.02:16:19
10 files: files:
11 filepath,kind,attributes,module,is_top filepath,kind,attributes,module,is_top
12 niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true

BIN
Top/semafor.qws Normal file
View File

Binary file not shown.

BIN
Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf
View File

Binary file not shown.

4
Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump
View File

@ -751,8 +751,8 @@ alt_after_alt_main:
244: 003fff06 br 244 <__alt_data_end+0xfffe0244>
00000248 <main>:
{0x000000f0, 0x000000f0, 0x000000f0, 0x00000010},
{0x000000fa, 0x000000f0, 0x000000f0, 0x00000010}
{0x000000f1, 0x000000f1, 0x000000f1, 0x00000011},
{0x000000d1, 0x000000f1, 0x000000f1, 0x00000011}
};
int main()

16
Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat
View File

@ -5630,14 +5630,14 @@
@15FD 00000020
@15FE 00000010
@15FF 00000010
@1600 000000F0
@1601 000000F0
@1602 000000F0
@1603 00000010
@1604 000000FA
@1605 000000F0
@1606 000000F0
@1607 00000010
@1600 000000F1
@1601 000000F1
@1602 000000F1
@1603 00000011
@1604 000000D1
@1605 000000F1
@1606 000000F1
@1607 00000011
@1608 64616552
@1609 00000079
@160A 0000000A

2
Top/software/semafor/mem_init/niosII_mem.hex
View File

@ -703,7 +703,7 @@
:2015E800003FB6060005883A003FFB06DEFFFD04DF000215DF000204E13FFF150001883A31
:2015F000E0BFFF17E0BFFE15E0BFFE1710000226002AF07000000106002AF0B0003FFF06E9
:2015F80000000010000000100000000500000010000000100000002000000010000000104E
:20160000000000F0000000F0000000F000000010000000FA000000F0000000F00000001000
:20160000000000F1000000F1000000F100000011000000D1000000F1000000F10000001122
:2016080064616552000000790000000A000000437665642F6C756E2F0000006C7665642FBA
:2016100061746A2F61755F67000074727665642F61746A2F61755F6700007472000000006C
:2016180000005B4800005BB000005C18000000000000000000000000000000000000000090

4
Top/software/semafor/sem.c
View File

@ -8,8 +8,8 @@
const alt_u32 divisors[TIME_SETS][TIME_STATES] = {
{0x00000010, 0x00000010, 0x00000005, 0x00000010},
{0x00000010, 0x00000020, 0x00000010, 0x00000010},
{0x000000f0, 0x000000f0, 0x000000f0, 0x00000010},
{0x000000fa, 0x000000f0, 0x000000f0, 0x00000010}
{0x000000f1, 0x000000f1, 0x000000f1, 0x00000011},
{0x000000d1, 0x000000f1, 0x000000f1, 0x00000011}
};
int main()

7
Top/software/semafor/transcript
View File

@ -1 +1,8 @@
# Reading C:/Software/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl
# vsim -gui null_sim.mpf
# Start time: 01:19:59 on Dec 24,2022
# ** Error (suppressible): (vsim-19) Failed to access library 'null_sim' at "null_sim".
# No such file or directory. (errno = ENOENT)
# Error loading design
# End time: 01:19:59 on Dec 24,2022, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0

4
Top/software/semafor_bsp/settings.bsp
View File

@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>22.12.2022 22:44:16</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1671734657095</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>24.12.2022 2:19:40</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1671833980256</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile>

4
Top/software/semafor_bsp/summary.html
View File

@ -22,10 +22,10 @@
<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>22.12.2022 22:44:16</td>
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>24.12.2022 2:19:40</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671734657095</td>
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671833980256</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td>