pt 1. initial sources
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set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
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set_global_assignment -name IP_TOOL_VERSION "14.0"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "periodram.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "periodram_inst.v"]
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// megafunction wizard: %RAM: 2-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: periodram.v
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// Megafunction Name(s):
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// altsyncram
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 14.0.2 Build 209 09/17/2014 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, the Altera Quartus II License Agreement,
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//the Altera MegaCore Function License Agreement, or other
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//applicable license agreement, including, without limitation,
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//that your use is for the sole purpose of programming logic
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//devices manufactured by Altera and sold by Altera or its
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//authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module periodram (
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clock,
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data,
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rdaddress,
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wraddress,
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wren,
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q);
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input clock;
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input [31:0] data;
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input [3:0] rdaddress;
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input [1:0] wraddress;
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input wren;
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output [7:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock;
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tri0 wren;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [7:0] sub_wire0;
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wire [7:0] q = sub_wire0[7:0];
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altsyncram altsyncram_component (
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.address_a (wraddress),
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.address_b (rdaddress),
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.clock0 (clock),
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.data_a (data),
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.wren_a (wren),
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.q_b (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({8{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_b = "NONE",
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altsyncram_component.address_reg_b = "CLOCK0",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.intended_device_family = "Cyclone IV E",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 4,
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altsyncram_component.numwords_b = 16,
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altsyncram_component.operation_mode = "DUAL_PORT",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_b = "UNREGISTERED",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
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altsyncram_component.widthad_a = 2,
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altsyncram_component.widthad_b = 4,
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altsyncram_component.width_a = 32,
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altsyncram_component.width_b = 8,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
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// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
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// Retrieval info: PRIVATE: CLRq NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
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// Retrieval info: PRIVATE: Clock NUMERIC "0"
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// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
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// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
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// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MEMSIZE NUMERIC "128"
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// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING ""
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// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
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// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
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// Retrieval info: PRIVATE: REGdata NUMERIC "1"
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// Retrieval info: PRIVATE: REGq NUMERIC "1"
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// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
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// Retrieval info: PRIVATE: REGrren NUMERIC "1"
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// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
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// Retrieval info: PRIVATE: REGwren NUMERIC "1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
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// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
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// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
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// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
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// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
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// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
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// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
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// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
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// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: enable NUMERIC "0"
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// Retrieval info: PRIVATE: rden NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
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// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4"
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// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
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// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2"
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// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
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// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
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// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
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// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]"
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// Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL "wraddress[1..0]"
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// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
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// Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0
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// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
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// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_inst.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_bb.v FALSE
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// Retrieval info: LIB_FILE: altera_mf
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@ -0,0 +1,8 @@
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periodram periodram_inst (
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.clock ( clock_sig ),
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.data ( data_sig ),
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.rdaddress ( rdaddress_sig ),
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.wraddress ( wraddress_sig ),
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.wren ( wren_sig ),
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.q ( q_sig )
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);
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@ -0,0 +1,132 @@
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module dec
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#(m = 8)
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(
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//clock and reset
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input logic clk, clrn,
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//control slave
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input logic ctl_wr, ctl_rd,
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input logic ctl_addr,
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input logic [31:0] ctl_wrdata,
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output logic [31:0] ctl_rddata,
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//memory slave
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input logic ram_wr,
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input logic [1:0] ram_addr,
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input logic [31:0] ram_wrdata,
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//external ports
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input logic train,
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output logic red, yellow, green
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);
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logic run;
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logic [1:0] divider;
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logic [m-1:0] divisor;
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logic [1:0] contr;
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logic [2:0] colors;
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logic [m-1:0] cntdiv;
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logic enacnt;
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//control slave logic
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always_ff @ (posedge clk or negedge clrn)
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begin
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if (!clrn)
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begin
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run <= 0;
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divider <= 0;
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end
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else
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begin
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if (ctl_wr)
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begin
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case (ctl_addr)
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1'b0: run <= ctl_wrdata[0];
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1'b1: divider <= ctl_wrdata[1:0];
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endcase
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end
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end
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end
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always_comb
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begin
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case (ctl_addr)
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1'b0: ctl_rddata = {31'b0,run};
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1'b1: ctl_rddata = {30'b0,divider};
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default: ctl_rddata = 'bx;
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endcase
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end
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//semaphore logic
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always_ff @ (posedge clk or negedge clrn)
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begin
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if (!clrn) cntdiv<=0;
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else
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begin
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if (train | ~run) cntdiv<=0;
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else
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begin
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if (enacnt) cntdiv<=0;
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else cntdiv<=cntdiv+1;
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end
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end
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end
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always_comb
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begin
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enacnt=(cntdiv==divisor);
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end
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always_ff @ (posedge clk or negedge clrn)
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begin
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if (!clrn)
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begin
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colors <= 3'b100;
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end
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else
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begin
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if (train | ~run)
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begin
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colors <= 3'b100;
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end
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else
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begin
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if (enacnt)
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begin
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case (colors)
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3'b100: colors <= 3'b010;
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3'b010: colors <= 3'b011;
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3'b011: colors <= 3'b001;
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3'b001: colors <= 3'b001;
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default: colors <= 3'b100;
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endcase
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end
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end
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end
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end
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always_comb
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begin
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case (colors)
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3'b100: contr = 2'b00;
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3'b010: contr = 2'b01;
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3'b011: contr = 2'b10;
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3'b001: contr = 2'b11;
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default : contr = 2'b00;
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endcase
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end
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assign red = colors[2];
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assign yellow = colors[1];
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assign green = colors[0];
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periodram b2v_inst3(
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.clock(clk),
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.data (ram_wrdata),
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.wraddress (ram_addr),
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.wren (ram_wr),
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.rdaddress({divider,contr}),
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.q(divisor)
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);
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endmodule
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@ -0,0 +1,128 @@
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`timescale 1 ns/1 ns
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module dec_tb();
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// Wires and variables to connect to UUT (unit under test)
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logic clk, clrn, train;
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logic r, y, g;
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logic [1:0] div;
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logic ctl_wr, ctl_rd;
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logic ctl_addr;
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logic [31:0] ctl_wrdata;
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logic [31:0] ctl_rddata;
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logic ram_wr;
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logic [1:0] ram_addr;
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logic [31:0] ram_wrdata;
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logic [31:0] divisor[3:0] = {
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{8'd10, 8'd70, 8'd50, 8'd20},
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{8'd10, 8'd30, 8'd40, 8'd30},
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{8'd10, 8'd30, 8'd10, 8'd100},
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{8'd10, 8'd60, 8'd80, 8'd50}
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};
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// Instantiate UUT
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dec my_sem(
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.clk(clk), .clrn(clrn),
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.ctl_wr(ctl_wr), .ctl_rd(ctl_rd),
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.ctl_addr(ctl_addr), .ctl_wrdata(ctl_wrdata), .ctl_rddata(ctl_rddata),
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.ram_wr(ram_wr),
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.ram_addr(ram_addr), .ram_wrdata(ram_wrdata),
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.train(train), .red(r), .yellow(y), .green(g)
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);
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// Clock definition
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initial begin
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clk = 0;
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forever #10 clk = ~clk;
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end
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// Divisor and train definition
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initial begin
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//initial reset
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clrn = 0;
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div = 0;
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train = 0;
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//take reset off
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@(negedge clk) clrn = 1;
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//configure semaphore
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||||
for (int i=0; i<4; i++) write_ram_transaction(i,divisor[i]); //write divisor RAM
|
||||
write_reg_transaction(1,div); //write initial divisor
|
||||
write_reg_transaction(0,1); //enable semaphore
|
||||
//run trains
|
||||
repeat (4)
|
||||
begin
|
||||
repeat (10) @(posedge clk);
|
||||
train=1;
|
||||
repeat (4) @(posedge clk);
|
||||
train=0;
|
||||
wait ({r,y,g}==3'b001);
|
||||
repeat (10) @(posedge clk);
|
||||
write_reg_transaction(1,div);
|
||||
div=div+1;
|
||||
end
|
||||
//wait a little
|
||||
repeat (10) @(posedge clk);
|
||||
$stop;
|
||||
end
|
||||
|
||||
//Single register write transaction task
|
||||
task write_reg_transaction;
|
||||
//input signals
|
||||
input [1:0] offs;
|
||||
input [31:0] val;
|
||||
//transaction implementation
|
||||
begin
|
||||
@(posedge clk);
|
||||
//assert signals for one clock cycle
|
||||
ctl_wr = 1;
|
||||
ctl_addr = offs;
|
||||
ctl_wrdata = val;
|
||||
@(posedge clk);
|
||||
//deassert signals
|
||||
ctl_wr = 0;
|
||||
ctl_addr = 'bx;
|
||||
ctl_wrdata = 'bx;
|
||||
end
|
||||
endtask
|
||||
|
||||
//Single register read transaction task
|
||||
task read_reg_transaction;
|
||||
//input signals
|
||||
input [1:0] offs;
|
||||
output [31:0] val;
|
||||
//transaction implementation
|
||||
begin
|
||||
@(posedge clk);
|
||||
//assert signals for one clock cycle
|
||||
ctl_rd = 1;
|
||||
ctl_addr = offs;
|
||||
@(posedge clk);
|
||||
val = ctl_rddata;
|
||||
//deassert signals
|
||||
ctl_rd = 0;
|
||||
ctl_addr = 'bx;
|
||||
end
|
||||
endtask
|
||||
|
||||
//RAM write transaction task
|
||||
task write_ram_transaction;
|
||||
//input signals
|
||||
input [1:0] offs;
|
||||
input [31:0] val;
|
||||
//transaction implementation
|
||||
begin
|
||||
@(posedge clk);
|
||||
//assert signals for one clock cycle
|
||||
ram_wr = 1;
|
||||
ram_addr = offs;
|
||||
ram_wrdata = val;
|
||||
@(posedge clk);
|
||||
//deassert signals
|
||||
ram_wr = 0;
|
||||
ram_addr = 'bx;
|
||||
ram_wrdata = 'bx;
|
||||
end
|
||||
endtask
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue