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periodram x32 unchecked

This commit is contained in:
Ivan I. Ovchinnikov 2022-12-22 15:20:49 +03:00
parent 1589af18e7
commit f6e75a12d5
22 changed files with 203 additions and 160 deletions
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30
HDL/IP/periodram.v
View File

@ -46,8 +46,8 @@ module periodram (
input clock;
input [31:0] data;
input [1:0] rdaddress;
input [1:0] wraddress;
input [3:0] rdaddress;
input [3:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
@ -94,15 +94,15 @@ module periodram (
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4,
altsyncram_component.numwords_b = 4,
altsyncram_component.numwords_a = 16,
altsyncram_component.numwords_b = 16,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 2,
altsyncram_component.widthad_b = 2,
altsyncram_component.widthad_a = 4,
altsyncram_component.widthad_b = 4,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
@ -143,7 +143,7 @@ endmodule
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "128"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
@ -180,26 +180,26 @@ endmodule
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "2"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 2 0 INPUT NODEFVAL "rdaddress[1..0]"
// Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL "wraddress[1..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]"
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL "wraddress[3..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0
// Retrieval info: CONNECT: @address_b 0 0 2 0 rdaddress 0 0 2 0
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0

BIN
Testbench/dec/dec.qws Normal file
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Binary file not shown.

4
Top/Semafor_hw.tcl
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@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 18.1
# Mon Dec 19 20:23:41 MSK 2022
# Wed Dec 21 21:00:10 MSK 2022
# DO NOT MODIFY
#
# sem "Semafor" v1.1
# 2022.12.19.20:23:40
# 2022.12.21.21:00:10
#
#

4
Top/Semafor_hw.tcl~
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@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 18.1
# Mon Dec 19 20:18:22 MSK 2022
# Mon Dec 19 20:23:41 MSK 2022
# DO NOT MODIFY
#
# sem "Semafor" v1.1
# 2022.12.19.20:18:22
# 2022.12.19.20:23:40
#
#

4
Top/niosII.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2022.12.19.20:24:19 -->
<!-- 2022.12.21.21:03:50 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1671467059</value>
<value>1671642230</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>

2
Top/niosII/niosII.bsf
View File

@ -75,7 +75,7 @@ refer to the applicable agreement for further details.
(text "red" (rect 117 163 252 336)(font "Arial" (color 0 0 0)))
(text "yellow" (rect 117 179 270 368)(font "Arial" (color 0 0 0)))
(text "green" (rect 117 195 264 400)(font "Arial" (color 0 0 0)))
(text " system " (rect 253 216 554 442)(font "Arial" ))
(text " niosII " (rect 262 216 572 442)(font "Arial" ))
(line (pt 112 32)(pt 176 32)(line_width 1))
(line (pt 176 32)(pt 176 216)(line_width 1))
(line (pt 112 216)(pt 176 216)(line_width 1))

4
Top/niosII/niosII.html
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@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table>
<table class="blueBar">
<tr>
<td class="l">2022.12.17.15:20:08</td>
<td class="l">2022.12.21.21:02:26</td>
<td class="r">Datasheet</td>
</tr>
</table>
@ -2039,7 +2039,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table class="blueBar">
<tr>
<td class="l">generation took 0,00 seconds</td>
<td class="r">rendering took 0,11 seconds</td>
<td class="r">rendering took 0,05 seconds</td>
</tr>
</table>
</body>

192
Top/niosII/niosII.xml
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File diff suppressed because one or more lines are too long

6
Top/niosII/synthesis/niosII.debuginfo
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@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="niosII" kind="system" version="18.1" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2022.12.17.15:20:44 -->
<!-- 2022.12.21.21:02:54 -->
<!-- A collection of modules and connections -->
<parameter name="clockCrossingAdapter">
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@ -53,7 +53,7 @@
</parameter>
<parameter name="generationId">
<type>int</type>
<value>1671276008</value>
<value>1671642146</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@ -12925,5 +12925,5 @@ parameters are a RESULT of the module parameters. -->
<version>18.1</version>
</plugin>
<reportVersion>18.1 625</reportVersion>
<uniqueIdentifier>7A31C1D08890000001851FD02AF4</uniqueIdentifier>
<uniqueIdentifier>7A31C1D088900000018535A2F788</uniqueIdentifier>
</EnsembleReport>

4
Top/niosII/synthesis/niosII.qip
View File

@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1"
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"]
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671276008"
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671642146"
set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"]
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"]
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"]
@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTI3NjAwOA==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTY0MjE0Ng==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U="
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="

30
Top/niosII/synthesis/submodules/periodram.v
View File

@ -46,8 +46,8 @@ module periodram (
input clock;
input [31:0] data;
input [1:0] rdaddress;
input [1:0] wraddress;
input [3:0] rdaddress;
input [3:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
@ -94,15 +94,15 @@ module periodram (
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4,
altsyncram_component.numwords_b = 4,
altsyncram_component.numwords_a = 16,
altsyncram_component.numwords_b = 16,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 2,
altsyncram_component.widthad_b = 2,
altsyncram_component.widthad_a = 4,
altsyncram_component.widthad_b = 4,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
@ -143,7 +143,7 @@ endmodule
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "128"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
@ -180,26 +180,26 @@ endmodule
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "2"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 2 0 INPUT NODEFVAL "rdaddress[1..0]"
// Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL "wraddress[1..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]"
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL "wraddress[3..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0
// Retrieval info: CONNECT: @address_b 0 0 2 0 rdaddress 0 0 2 0
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0

2
Top/niosII/testbench/mentor/msim_setup.tcl
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@ -94,7 +94,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 win32 2022.12.19.20:25:08
# ACDS 18.1 625 win32 2022.12.21.21:02:08
# ----------------------------------------
# Initialize variables

6
Top/niosII/testbench/niosII.html
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@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table>
<table class="blueBar">
<tr>
<td class="l">2022.12.19.20:24:19</td>
<td class="l">2022.12.21.21:01:24</td>
<td class="r">Datasheet</td>
</tr>
</table>
@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0,01 seconds</td>
<td class="r">rendering took 0,07 seconds</td>
<td class="l">generation took 0,00 seconds</td>
<td class="r">rendering took 0,08 seconds</td>
</tr>
</table>
</body>

6
Top/niosII/testbench/niosII_tb.html
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@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table>
<table class="blueBar">
<tr>
<td class="l">2022.12.19.20:24:29</td>
<td class="l">2022.12.21.21:01:33</td>
<td class="r">Datasheet</td>
</tr>
</table>
@ -211,7 +211,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table>
<tr>
<td class="parametername">AUTO_GENERATION_ID</td>
<td class="parametervalue">1671467069</td>
<td class="parametervalue">1671642093</td>
</tr>
<tr>
<td class="parametername">AUTO_UNIQUE_ID</td>
@ -2360,7 +2360,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table class="blueBar">
<tr>
<td class="l">generation took 0,00 seconds</td>
<td class="r">rendering took 0,04 seconds</td>
<td class="r">rendering took 0,06 seconds</td>
</tr>
</table>
</body>

43
Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v Normal file
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@ -0,0 +1,43 @@
`timescale 1 ps / 1 ps
module niosII_tb (
);
wire niosii_inst_clk_bfm_clk_clk; // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk]
wire niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n
niosII niosii_inst (
.clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk
.reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
.sem_export_train (), // sem_export.train
.sem_export_red (), // .red
.sem_export_yellow (), // .yellow
.sem_export_green () // .green
);
altera_avalon_clock_source #(
.CLOCK_RATE (50000000),
.CLOCK_UNIT (1)
) niosii_inst_clk_bfm (
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
);
altera_avalon_reset_source #(
.ASSERT_HIGH_RESET (0),
.INITIAL_RESET_CYCLES (50)
) niosii_inst_reset_bfm (
.reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
);
initial begin
train = 0;
wait (niosii_inst_reset_bfm_reset_reset);
forever begin
repeat (29000) @(posedge niosII_inst_clk_bfm_clk_clk);
train = 1;
repeat (10) @(posedge niosII_inst_clk_bfm_clk_clk);
train = 0;
end
end
endmodule

4
Top/niosII/testbench/synopsys/vcs/vcs_setup.sh
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@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 18.1 625 win32 2022.12.19.20:25:08
# ACDS 18.1 625 win32 2022.12.21.21:02:08
# ----------------------------------------
# vcs - auto-generated simulation script
@ -94,7 +94,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 win32 2022.12.19.20:25:08
# ACDS 18.1 625 win32 2022.12.21.21:02:08
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="niosII_tb"

4
Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh
View File

@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 18.1 625 win32 2022.12.19.20:25:08
# ACDS 18.1 625 win32 2022.12.21.21:02:08
# ----------------------------------------
# vcsmx - auto-generated simulation script
@ -107,7 +107,7 @@
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 win32 2022.12.19.20:25:08
# ACDS 18.1 625 win32 2022.12.21.21:02:08
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="niosII_tb"

6
Top/niosII_tb.csv
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@ -1,12 +1,12 @@
# system info niosII_tb on 2022.12.19.20:25:06
# system info niosII_tb on 2022.12.21.21:02:06
system_info:
name,value
DEVICE,EP4CE115F29C7
DEVICE_FAMILY,Cyclone IV E
GENERATION_ID,1671467069
GENERATION_ID,1671642093
#
#
# Files generated for niosII_tb on 2022.12.19.20:25:06
# Files generated for niosII_tb on 2022.12.21.21:02:06
files:
filepath,kind,attributes,module,is_top
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true

1 # system info niosII_tb on 2022.12.19.20:25:06 # system info niosII_tb on 2022.12.21.21:02:06
2 system_info: system_info:
3 name,value name,value
4 DEVICE,EP4CE115F29C7 DEVICE,EP4CE115F29C7
5 DEVICE_FAMILY,Cyclone IV E DEVICE_FAMILY,Cyclone IV E
6 GENERATION_ID,1671467069 GENERATION_ID,1671642093
7 # #
8 # #
9 # Files generated for niosII_tb on 2022.12.19.20:25:06 # Files generated for niosII_tb on 2022.12.21.21:02:06
10 files: files:
11 filepath,kind,attributes,module,is_top filepath,kind,attributes,module,is_top
12 niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true

2
Top/software/semafor/.settings/language.settings.xml
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@ -2,7 +2,7 @@
<project>
<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" name="Nios II">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="396483926927256637" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="1701080960758821589" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>

2
Top/software/semafor_bsp/.settings/language.settings.xml
View File

@ -2,7 +2,7 @@
<project>
<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" name="Nios II">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="396483926927256637" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="1701080960758821589" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>

4
Top/software/semafor_bsp/settings.bsp
View File

@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>17.12.2022 15:27:50</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1671276470966</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>21.12.2022 21:06:52</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1671642412929</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile>

4
Top/software/semafor_bsp/summary.html
View File

@ -22,10 +22,10 @@
<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>17.12.2022 15:27:50</td>
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>21.12.2022 21:06:52</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671276470966</td>
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671642412929</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td>