reported lr2 + individual

HDL/dec.sv

@@ -83,6 +83,7 @@ module dec
                 colors <= 3'b001;
                 state <= GREEN;
             end
+				
             if (train) begin
                 colors <= 3'b100;
                 state <= RED;

Testbench/sigdel/db/prev_cmp_sigdel.qmsg

@@ -0,0 +1,9 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673520674097 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 12 13:51:13 2023 " "Processing started: Thu Jan 12 13:51:13 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674097 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674098 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
+{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"\[\";  expecting an operand sigdel.sv(14) " "Verilog HDL syntax error at sigdel.sv(14) near text: \"\[\";  expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." {  } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 14 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "sigdel sigdel.sv(1) " "Ignored design unit \"sigdel\" at sigdel.sv(1) due to previous errors" {  } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" {  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680483 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "923 " "Peak virtual memory: 923 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Jan 12 13:51:20 2023 " "Processing ended: Thu Jan 12 13:51:20 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680505 ""}

Testbench/sigdel/db/sigdel.cbx.xml

@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="sigdel">
+	</PROJECT>
+</LOG_ROOT>

Testbench/sigdel/db/sigdel.db_info

@@ -0,0 +1,3 @@
+Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+Version_Index = 486699264
+Creation_Time = Mon Jan 16 21:47:58 2023

Testbench/sigdel/db/sigdel.hier_info

@@ -0,0 +1,47 @@
+|sigdel
+phinc[0] => Add0.IN14
+phinc[1] => Add0.IN13
+phinc[2] => Add0.IN12
+phinc[3] => Add0.IN11
+phinc[4] => Add0.IN10
+phinc[5] => Add0.IN9
+phinc[6] => Add0.IN8
+phinc[7] => Add0.IN7
+clk => acc[0].CLK
+clk => acc[1].CLK
+clk => acc[2].CLK
+clk => acc[3].CLK
+clk => acc[4].CLK
+clk => acc[5].CLK
+clk => acc[6].CLK
+clk => acc[7].CLK
+clk => acc[8].CLK
+clk => acc[9].CLK
+clk => acc[10].CLK
+clk => acc[11].CLK
+clk => acc[12].CLK
+clk => acc[13].CLK
+clr_n => acc[0].ACLR
+clr_n => acc[1].ACLR
+clr_n => acc[2].ACLR
+clr_n => acc[3].ACLR
+clr_n => acc[4].ACLR
+clr_n => acc[5].ACLR
+clr_n => acc[6].ACLR
+clr_n => acc[7].ACLR
+clr_n => acc[8].ACLR
+clr_n => acc[9].ACLR
+clr_n => acc[10].ACLR
+clr_n => acc[11].ACLR
+clr_n => acc[12].ACLR
+clr_n => acc[13].ACLR
+phase[0] <= acc[6].DB_MAX_OUTPUT_PORT_TYPE
+phase[1] <= acc[7].DB_MAX_OUTPUT_PORT_TYPE
+phase[2] <= acc[8].DB_MAX_OUTPUT_PORT_TYPE
+phase[3] <= acc[9].DB_MAX_OUTPUT_PORT_TYPE
+phase[4] <= acc[10].DB_MAX_OUTPUT_PORT_TYPE
+phase[5] <= acc[11].DB_MAX_OUTPUT_PORT_TYPE
+phase[6] <= acc[12].DB_MAX_OUTPUT_PORT_TYPE
+phase[7] <= acc[13].DB_MAX_OUTPUT_PORT_TYPE
+
+

Testbench/sigdel/db/sigdel.lpc.html

@@ -0,0 +1,18 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+</TABLE>

Testbench/sigdel/db/sigdel.lpc.txt

@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

Testbench/sigdel/db/sigdel.map.logdb

@@ -0,0 +1 @@
+v1

Testbench/sigdel/db/sigdel.map.qmsg

@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673883395012 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 16 18:36:34 2023 " "Processing started: Mon Jan 16 18:36:34 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel " "Found entity 1: sigdel" {  } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sigdel_tb.sv 1 1 " "Found 1 design units, including 1 entities, in source file sigdel_tb.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel_tb " "Found entity 1: sigdel_tb" {  } { { "sigdel_tb.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Testbench/sigdel/sigdel_tb.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "sigdel " "Elaborating entity \"sigdel\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1673883401097 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1673883401388 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1673883401553 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1673883401553 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "32 " "Implemented 32 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1673883401619 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1673883401619 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1047 " "Peak virtual memory: 1047 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 16 18:36:41 2023 " "Processing ended: Mon Jan 16 18:36:41 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401622 ""}

Testbench/sigdel/db/sigdel.map_bb.logdb

@@ -0,0 +1 @@
+v1

Testbench/sigdel/db/sigdel.smart_action.txt

@@ -0,0 +1 @@
+FIT

Testbench/sigdel/db/sigdel_partition_pins.json

@@ -0,0 +1,81 @@
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "phase[0]",
+					"strict" : false
+				},
+				{
+					"name" : "phase[1]",
+					"strict" : false
+				},
+				{
+					"name" : "phase[2]",
+					"strict" : false
+				},
+				{
+					"name" : "phase[3]",
+					"strict" : false
+				},
+				{
+					"name" : "phase[4]",
+					"strict" : false
+				},
+				{
+					"name" : "phase[5]",
+					"strict" : false
+				},
+				{
+					"name" : "phase[6]",
+					"strict" : false
+				},
+				{
+					"name" : "phase[7]",
+					"strict" : false
+				},
+				{
+					"name" : "clk",
+					"strict" : false
+				},
+				{
+					"name" : "clr_n",
+					"strict" : false
+				},
+				{
+					"name" : "phinc[6]",
+					"strict" : false
+				},
+				{
+					"name" : "phinc[7]",
+					"strict" : false
+				},
+				{
+					"name" : "phinc[5]",
+					"strict" : false
+				},
+				{
+					"name" : "phinc[4]",
+					"strict" : false
+				},
+				{
+					"name" : "phinc[3]",
+					"strict" : false
+				},
+				{
+					"name" : "phinc[2]",
+					"strict" : false
+				},
+				{
+					"name" : "phinc[1]",
+					"strict" : false
+				},
+				{
+					"name" : "phinc[0]",
+					"strict" : false
+				}
+			]
+		}
+	]
+}

Testbench/sigdel/incremental_db/README

@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+

Testbench/sigdel/incremental_db/compiled_partitions/sigdel.db_info

@@ -0,0 +1,3 @@
+Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+Version_Index = 486699264
+Creation_Time = Thu Jan 12 13:26:18 2023

Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.sig

@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3

Top/niosII.sopcinfo

@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
  <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
- <!-- 2022.12.24.02:16:30 -->
+ <!-- 2023.01.17.19:01:29 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
   <type>java.lang.Integer</type>
-  <value>1671833790</value>
+  <value>1673967689</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>

Top/niosII/niosII.html

@@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   </table>
   <table class="blueBar">
    <tr>
-    <td class="l">2022.12.24.02:16:30</td>
+    <td class="l">2023.01.17.19:00:54</td>
     <td class="r">Datasheet</td>
    </tr>
   </table>
@@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   </div>
   <table class="blueBar">
    <tr>
-    <td class="l">generation took 0,00 seconds</td>
+    <td class="l">generation took 0.00 seconds</td>
-    <td class="r">rendering took 0,03 seconds</td>
+    <td class="r">rendering took 0.02 seconds</td>
    </tr>
   </table>
  </body>

Top/niosII/synthesis/niosII.debuginfo

@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="niosII" kind="system" version="18.1" fabric="QSYS">
  <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
- <!-- 2022.12.24.02:16:58 -->
+ <!-- 2023.01.17.19:00:59 -->
  <!-- A collection of modules and connections -->
  <parameter name="clockCrossingAdapter">
   <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@@ -53,7 +53,7 @@
  </parameter>
  <parameter name="generationId">
   <type>int</type>
-  <value>1671833790</value>
+  <value>1673967654</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
@@ -12925,5 +12925,5 @@ parameters are a RESULT of the module parameters. -->
   <version>18.1</version>
  </plugin>
  <reportVersion>18.1 625</reportVersion>
- <uniqueIdentifier>7A31C1D0889000000185410F37E7</uniqueIdentifier>
+ <uniqueIdentifier>024262A031A800000185C03F5C6B</uniqueIdentifier>
 </EnsembleReport>

Top/niosII/synthesis/niosII.qip

@@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy
 set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1"
 set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys"
 set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"]
-set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671833790"
+set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1673967654"
 set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"]
 set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"]
 set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"]
@@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP
 set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On"
 set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTgzMzc5MA==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3Mzk2NzY1NA==::QXV0byBHRU5FUkFUSU9OX0lE"
 set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
 set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U="
 set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@@ -1083,15 +1083,15 @@ set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(
 set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mem.v"]
 set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_jtag_uart.v"]
 set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu.v"]
-set_global_assignment -library "niosII" -name SDC_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu.sdc"]
-set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu.v"]
 set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_sysclk.v"]
-set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_tck.v"]
-set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_wrapper.v"]
 set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_ociram_default_contents.mif"]
-set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_rf_ram_a.mif"]
+set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_tck.v"]
+set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu.v"]
 set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_rf_ram_b.mif"]
+set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_wrapper.v"]
+set_global_assignment -library "niosII" -name SDC_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu.sdc"]
 set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_test_bench.v"]
+set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_rf_ram_a.mif"]
 
 set_global_assignment -entity "altera_reset_controller" -library "niosII" -name IP_TOOL_NAME "altera_reset_controller"
 set_global_assignment -entity "altera_reset_controller" -library "niosII" -name IP_TOOL_VERSION "18.1"

Top/niosII/synthesis/niosII.regmap

@@ -1,4 +1,4 @@
-<?xml version="1.0"?>
+<?xml version="1.0" encoding="UTF-8"?>
 <device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
 <name>niosII</name>
 <peripherals>

Top/niosII/synthesis/submodules/dec.sv

@@ -83,6 +83,7 @@ module dec
                 colors <= 3'b001;
                 state <= GREEN;
             end
+				
             if (train) begin
                 colors <= 3'b100;
                 state <= RED;

Top/niosII/synthesis/submodules/niosII_cpu_cpu.sdc

@@ -1,4 +1,4 @@
-# Legal Notice: (C)2022 Altera Corporation. All rights reserved.  Your
+# Legal Notice: (C)2023 Altera Corporation. All rights reserved.  Your
 # use of Altera Corporation's design tools, logic functions and other
 # software and tools, and its AMPP partner logic functions, and any
 # output files any of the foregoing (including device programming or

Top/niosII/synthesis/submodules/niosII_cpu_cpu.v

@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved.  Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved.  Your
 //use of Altera Corporation's design tools, logic functions and other
 //software and tools, and its AMPP partner logic functions, and any
 //output files any of the foregoing (including device programming or

Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_sysclk.v

@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved.  Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved.  Your
 //use of Altera Corporation's design tools, logic functions and other
 //software and tools, and its AMPP partner logic functions, and any
 //output files any of the foregoing (including device programming or

Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_tck.v

@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved.  Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved.  Your
 //use of Altera Corporation's design tools, logic functions and other
 //software and tools, and its AMPP partner logic functions, and any
 //output files any of the foregoing (including device programming or

Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_wrapper.v

@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved.  Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved.  Your
 //use of Altera Corporation's design tools, logic functions and other
 //software and tools, and its AMPP partner logic functions, and any
 //output files any of the foregoing (including device programming or

Top/niosII/synthesis/submodules/niosII_cpu_cpu_ociram_default_contents.mif

@@ -7,261 +7,261 @@ DATA_RADIX=HEX;
 
 CONTENT BEGIN
 
-00 : 88997af9;
+00 : 5870e850;
-01 : abaae595;
+01 : c7a32b0d;
-02 : 32fd14d1;
+02 : 6f82d8fd;
-03 : b66193c4;
+03 : 40bb3819;
-04 : c6a6aa09;
+04 : 03c0b473;
-05 : 0b43de5b;
+05 : 8f16cf30;
-06 : d1d93028;
+06 : d708360b;
-07 : bcd08e2a;
+07 : 880f36dc;
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+09 : 5944e053;
-0a : 864ddf62;
+0a : c1313a53;
-0b : 68301486;
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-1a : 4594a3c5;
+1a : b603ed2b;
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+1b : 2a1eb3a0;
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+1c : f4b7b88b;
-1d : 0f552242;
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-20 : 5d590422;
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-2a : e2f4fc64;
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+4f : 6433730b;
-50 : 1edccf12;
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-5a : 3f04e244;
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-5d : c53fe664;
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-5f : aaa406e5;
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-60 : f785e24e;
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-7a : 74ede6d2;
+7a : 5f87a44a;
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+7c : c0524059;
-7d : cc0819fb;
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-80 : 0f267a65;
+80 : e459de2d;
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+89 : d52486ab;
-8a : 0b227946;
+8a : 1e598442;
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+8b : d8d4c72d;
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+8f : 5fa48cd0;
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+9a : 436fcd2b;
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+9b : be8fe3e1;
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+9c : dae80c2f;
-9d : 94e84514;
+9d : e95b81e6;
-9e : 7babc333;
+9e : 767f7b1b;
-9f : afaa8445;
+9f : 23d2190d;
-a0 : b1175e3a;
+a0 : dbd13b92;
-a1 : e08de629;
+a1 : ba04bced;
-a2 : 7f12a52d;
+a2 : c59ab4a9;
-a3 : 0e322909;
+a3 : d18cd97a;
-a4 : 18784dc6;
+a4 : fdc9eef9;
-a5 : b23bcc20;
+a5 : e5d3431b;
-a6 : 266c9e34;
+a6 : 36145dba;
-a7 : c857eaf3;
+a7 : 381901fd;
-a8 : 2ae3b164;
+a8 : 2b84a31d;
-a9 : 038acf2a;
+a9 : 56d3b835;
-aa : c1abc60d;
+aa : 82d83a4f;
-ab : 8af787bd;
+ab : 521d2b9a;
-ac : 043723a9;
+ac : 0224591a;
-ad : c37c952d;
+ad : 80d7ea50;
-ae : 693a361f;
+ae : 49815eac;
-af : da4b8e99;
+af : 9c8177e2;
-b0 : fb8fdb10;
+b0 : d83c171d;
-b1 : 4d6365f2;
+b1 : 82d4e894;
-b2 : 712358e9;
+b2 : 2da7a2cf;
-b3 : 85dae0fa;
+b3 : ae082f05;
-b4 : 7e82a418;
+b4 : ea847ea7;
-b5 : d3493768;
+b5 : c53a36ee;
-b6 : 739c65ec;
+b6 : 9044fe8d;
-b7 : 73b66b19;
+b7 : dadb18f9;
-b8 : 22142816;
+b8 : 3631522b;
-b9 : ff498322;
+b9 : 2bae3746;
-ba : 3266495e;
+ba : 02d78d99;
-bb : e26e8214;
+bb : 8e0e2771;
-bc : c8c47131;
+bc : 2ed189db;
-bd : 660793d8;
+bd : 63aa82eb;
-be : 689f8d69;
+be : 754229af;
-bf : faae340b;
+bf : a11062b5;
-c0 : 37518ba7;
+c0 : e28618e1;
-c1 : f2865fe5;
+c1 : fcaf3400;
-c2 : 1bb44f3d;
+c2 : c8a7faac;
-c3 : 3bce44c5;
+c3 : be56d9b0;
-c4 : aff2d188;
+c4 : 7c3f3063;
-c5 : 985442da;
+c5 : 4d331f3f;
-c6 : 85bb58bd;
+c6 : 8cceb16d;
-c7 : 0c53135d;
+c7 : 2d352b5d;
-c8 : 495f80bc;
+c8 : 0db6cd22;
-c9 : 853c95dc;
+c9 : 745ff58e;
-ca : dde937f1;
+ca : e450c6d2;
-cb : 418f9452;
+cb : 5567ae51;
-cc : 7669641c;
+cc : ec2ac609;
-cd : 0e752434;
+cd : fcced128;
-ce : b0fe17a7;
+ce : 193f8e92;
-cf : d1be9b88;
+cf : 5719a6cc;
-d0 : cfbfeb76;
+d0 : 065cddb6;
-d1 : 80b48a11;
+d1 : 04f4e1f9;
-d2 : 9327c69e;
+d2 : a95d8a1e;
-d3 : beca5a88;
+d3 : d516bf8e;
-d4 : e71d428f;
+d4 : e30d671e;
-d5 : b318d275;
+d5 : ebeeb2fe;
-d6 : 56fea35e;
+d6 : b48fdd0f;
-d7 : 140cd6bd;
+d7 : f4b75c46;
-d8 : b8c937ce;
+d8 : 4d9c9650;
-d9 : 540eea36;
+d9 : f2df58d8;
-da : ee58fc7f;
+da : 67ace373;
-db : 5615c389;
+db : 7ccace3c;
-dc : 46692ad0;
+dc : f4f3f5d5;
-dd : 5c713e51;
+dd : 2be9f598;
-de : 6ba95f60;
+de : f7889908;
-df : 0e166732;
+df : f67c2f07;
-e0 : ac0e49f5;
+e0 : 880a8491;
-e1 : c9a5ea76;
+e1 : 9c3967d0;
-e2 : 05b04d86;
+e2 : d89b44d2;
-e3 : b29ac712;
+e3 : 7c21987c;
-e4 : 4e344493;
+e4 : 495e0377;
-e5 : d45ede48;
+e5 : 1c88706d;
-e6 : 3da7e426;
+e6 : bf0b4325;
-e7 : 4d6a8937;
+e7 : 79fcc944;
-e8 : 99b59bd4;
+e8 : fd8c1d81;
-e9 : 1f8a5751;
+e9 : f4f168ae;
-ea : 8b07e64e;
+ea : cf67e751;
-eb : b4dcd496;
+eb : 75907b16;
-ec : 42f84fe6;
+ec : d859c7c1;
-ed : f1d5952f;
+ed : 05ef2e02;
-ee : a2e5a42d;
+ee : 1f5802c9;
-ef : 15b1af16;
+ef : 8cb4928b;
-f0 : 168012bc;
+f0 : 19e65b5f;
-f1 : 2e276612;
+f1 : 9c3b7bab;
-f2 : 89913eaa;
+f2 : 22bc8d7d;
-f3 : c607a1a2;
+f3 : 03aa0e5f;
-f4 : fd8b544d;
+f4 : 7d35f4ff;
-f5 : aec31a53;
+f5 : e5208a6e;
-f6 : 25f958ad;
+f6 : 44fdd477;
-f7 : 365903ec;
+f7 : 74a81f1c;
-f8 : 14761865;
+f8 : 6936d4f1;
-f9 : 568cc23b;
+f9 : 375fc2a2;
-fa : b0386305;
+fa : 22a07f26;
-fb : fb9ebd8a;
+fb : 701c1a4d;
-fc : a25911d4;
+fc : af4d2557;
-fd : 806e3fbb;
+fd : bac85a82;
-fe : 9df35264;
+fe : 29cff602;
-ff : d62b3814;
+ff : 3e17ccab;
 
 END;

Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v

@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved.  Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved.  Your
 //use of Altera Corporation's design tools, logic functions and other
 //software and tools, and its AMPP partner logic functions, and any
 //output files any of the foregoing (including device programming or

Top/niosII/synthesis/submodules/niosII_jtag_uart.v

@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved.  Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved.  Your
 //use of Altera Corporation's design tools, logic functions and other
 //software and tools, and its AMPP partner logic functions, and any
 //output files any of the foregoing (including device programming or

Top/niosII/synthesis/submodules/niosII_mem.v

@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved.  Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved.  Your
 //use of Altera Corporation's design tools, logic functions and other
 //software and tools, and its AMPP partner logic functions, and any
 //output files any of the foregoing (including device programming or

Top/niosII/synthesis/submodules/niosII_sys_clk_timer.v

@@ -1,4 +1,4 @@
-//Legal Notice: (C)2022 Altera Corporation. All rights reserved.  Your
+//Legal Notice: (C)2023 Altera Corporation. All rights reserved.  Your
 //use of Altera Corporation's design tools, logic functions and other
 //software and tools, and its AMPP partner logic functions, and any
 //output files any of the foregoing (including device programming or

Top/niosII/testbench/mentor/msim_setup.tcl

@@ -1,5 +1,5 @@
 
-# (C) 2001-2022 Altera Corporation. All rights reserved.
+# (C) 2001-2023 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -94,7 +94,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 18.1 625 win32 2022.12.24.02:16:20
+# ACDS 18.1 625 linux 2023.01.17.19:01:36
 
 # ----------------------------------------
 # Initialize variables
@@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] {
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "C:/software/intelfpga_lite/18.1/quartus/"
+  set QUARTUS_INSTALL_DIR "/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
@@ -142,14 +142,14 @@ if ![ string match "*-64 vsim*" [ vsim -version ] ] {
 alias file_copy {
   echo "\[exec\] file_copy"
   file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
-  file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
-  file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
   file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
-  file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
+  file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
-  file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
   file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
   file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
   file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
+  file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
+  file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
+  file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
   file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
 }
 
@@ -280,9 +280,9 @@ alias com {
   eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv"                                 -L altera_common_sv_packages -work cpu_data_master_agent                     
   eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv"                             -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_translator    
   eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv"                            -L altera_common_sv_packages -work cpu_data_master_translator                
-  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v"                                                                           -work cpu                                       
   eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v"                                                        -work cpu                                       
   eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v"                                                           -work cpu                                       
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v"                                                                           -work cpu                                       
   eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v"                                                       -work cpu                                       
   eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v"                                                                -work cpu                                       
   eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v"                                                                  -work rst_controller                            

Top/niosII/testbench/niosII.html

@@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   </table>
   <table class="blueBar">
    <tr>
-    <td class="l">2022.12.24.02:15:37</td>
+    <td class="l">2023.01.17.19:01:29</td>
     <td class="r">Datasheet</td>
    </tr>
   </table>
@@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   </div>
   <table class="blueBar">
    <tr>
-    <td class="l">generation took 0,01 seconds</td>
+    <td class="l">generation took 0.00 seconds</td>
-    <td class="r">rendering took 0,07 seconds</td>
+    <td class="r">rendering took 0.01 seconds</td>
    </tr>
   </table>
  </body>

Top/niosII/testbench/niosII_tb.html

@@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   </table>
   <table class="blueBar">
    <tr>
-    <td class="l">2022.12.24.02:15:47</td>
+    <td class="l">2023.01.17.19:01:31</td>
     <td class="r">Datasheet</td>
    </tr>
   </table>
@@ -211,7 +211,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
       <table>
        <tr>
         <td class="parametername">AUTO_GENERATION_ID</td>
-        <td class="parametervalue">1671833747</td>
+        <td class="parametervalue">1673967691</td>
        </tr>
        <tr>
         <td class="parametername">AUTO_UNIQUE_ID</td>
@@ -2359,8 +2359,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   </div>
   <table class="blueBar">
    <tr>
-    <td class="l">generation took 0,01 seconds</td>
+    <td class="l">generation took 0.00 seconds</td>
-    <td class="r">rendering took 0,06 seconds</td>
+    <td class="r">rendering took 0.02 seconds</td>
    </tr>
   </table>
  </body>

Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v

@@ -1,64 +1,55 @@
+// niosII_tb.v
+
+// Generated using ACDS version 18.1 625
+
 `timescale 1 ps / 1 ps
 module niosII_tb (
-	              );
+                  );
 
-	wire    niosii_inst_clk_bfm_clk_clk;       // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk]
+    wire    niosii_inst_clk_bfm_clk_clk;       // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk]
-	wire    niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n
+    wire    niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n
     reg     train;
     wire    red, yellow, green;
 
-	niosII niosii_inst 
+    niosII niosii_inst (
-      (
+                        .clk_clk           (niosii_inst_clk_bfm_clk_clk),       //        clk.clk
-	   .clk_clk           (niosii_inst_clk_bfm_clk_clk),       //        clk.clk
+                        .reset_reset_n     (niosii_inst_reset_bfm_reset_reset), //      reset.reset_n
-	   .reset_reset_n     (niosii_inst_reset_bfm_reset_reset), //      reset.reset_n
+                        .sem_export_train  (train),                             // sem_export.train
-	   .sem_export_train  (train),                             // sem_export.train
+                        .sem_export_red    (red),                               //           .red
-	   .sem_export_red    (red),                               //           .red
+                        .sem_export_yellow (yellow),                            //           .yellow
-	   .sem_export_yellow (yellow),                            //           .yellow
+                        .sem_export_green  (green)                              //           .green
-	   .sem_export_green  (green)                              //           .green
+                        );
-	   );
 
-	altera_avalon_clock_source 
+    altera_avalon_clock_source #(
-      #(
+                                 .CLOCK_RATE (50000000),
-		.CLOCK_RATE (50000000),
+                                 .CLOCK_UNIT (1)
-		.CLOCK_UNIT (1)
+                                 ) niosii_inst_clk_bfm (
-	    ) 
+                                                        .clk (niosii_inst_clk_bfm_clk_clk)  // clk.clk
-    niosii_inst_clk_bfm 
+                                                        );
-      (
-	   .clk (niosii_inst_clk_bfm_clk_clk)  // clk.clk
-	   );
-
-	altera_avalon_reset_source 
-      #(
-		.ASSERT_HIGH_RESET    (0),
-		.INITIAL_RESET_CYCLES (50)
-	    ) 
-    niosii_inst_reset_bfm 
-      (
-	   .reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
-	   .clk   (niosii_inst_clk_bfm_clk_clk)        //   clk.clk
-	   );
 
+    altera_avalon_reset_source #(
+                                 .ASSERT_HIGH_RESET    (0),
+                                 .INITIAL_RESET_CYCLES (50)
+                                 ) niosii_inst_reset_bfm (
+                                                          .reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
+                                                          .clk   (niosii_inst_clk_bfm_clk_clk)        //   clk.clk
+                                                          );
     initial begin
         train = 0;
         wait (niosii_inst_reset_bfm_reset_reset);
         forever begin
+            wait ({red,yellow,green}==3'b001);
             repeat (29000) @(posedge niosii_inst_clk_bfm_clk_clk);
-            train = 1;
+            repeat(8) begin
-            repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
+                train = 1;
-            train = 0;
+                repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
-            repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk);
+                train = 0;
-            train = 1;
+                wait ({red,yellow,green}==3'b001);
-            repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
+                repeat (200) @(posedge niosii_inst_clk_bfm_clk_clk);
-            train = 0;
+            end
-            repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk);
-            train = 1;
-            repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
-            train = 0;
-            repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk);
-            train = 1;
-            repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
-            train = 0;
         end
     end
 
+
+
 endmodule

Top/niosII/testbench/synopsys/vcs/vcs_setup.sh

@@ -1,5 +1,5 @@
 
-# (C) 2001-2022 Altera Corporation. All rights reserved.
+# (C) 2001-2023 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 18.1 625 win32 2022.12.24.02:16:20
+# ACDS 18.1 625 linux 2023.01.17.19:01:36
 
 # ----------------------------------------
 # vcs - auto-generated simulation script
@@ -94,12 +94,12 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 18.1 625 win32 2022.12.24.02:16:20
+# ACDS 18.1 625 linux 2023.01.17.19:01:36
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="niosII_tb"
 QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="C:/software/intelfpga_lite/18.1/quartus/"
+QUARTUS_INSTALL_DIR="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/"
 SKIP_FILE_COPY=0
 SKIP_SIM=0
 USER_DEFINED_ELAB_OPTIONS=""
@@ -131,14 +131,14 @@ fi
 # copy RAM/ROM files to simulation directory
 if [ $SKIP_FILE_COPY -eq 0 ]; then
   cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
-  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
-  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
   cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
-  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
+  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
-  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
   cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
   cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
   cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
+  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
+  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
+  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
   cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
 fi
 
@@ -171,9 +171,9 @@ vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPT
   $QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv \
   $QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv \
   $QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv \
-  $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v \
   $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v \
   $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v \
+  $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v \
   $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v \
   $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v \
   $QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v \

Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh

@@ -1,5 +1,5 @@
 
-# (C) 2001-2022 Altera Corporation. All rights reserved.
+# (C) 2001-2023 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 18.1 625 win32 2022.12.24.02:16:20
+# ACDS 18.1 625 linux 2023.01.17.19:01:36
 
 # ----------------------------------------
 # vcsmx - auto-generated simulation script
@@ -107,12 +107,12 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 18.1 625 win32 2022.12.24.02:16:20
+# ACDS 18.1 625 linux 2023.01.17.19:01:36
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="niosII_tb"
 QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="C:/software/intelfpga_lite/18.1/quartus/"
+QUARTUS_INSTALL_DIR="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/"
 SKIP_FILE_COPY=0
 SKIP_DEV_COM=0
 SKIP_COM=0
@@ -189,14 +189,14 @@ mkdir -p ./libraries/cycloneive_ver/
 # copy RAM/ROM files to simulation directory
 if [ $SKIP_FILE_COPY -eq 0 ]; then
   cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
-  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
-  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
   cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
-  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
+  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
-  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
   cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
   cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
   cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
+  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
+  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
+  cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
   cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
 fi
 
@@ -239,9 +239,9 @@ if [ $SKIP_COM -eq 0 ]; then
   vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv"                                 -work cpu_data_master_agent                     
   vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv"                             -work jtag_uart_avalon_jtag_slave_translator    
   vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv"                            -work cpu_data_master_translator                
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v"                                              -work cpu                                       
   vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v"                           -work cpu                                       
   vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v"                              -work cpu                                       
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v"                                              -work cpu                                       
   vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v"                          -work cpu                                       
   vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v"                                   -work cpu                                       
   vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v"                                     -work rst_controller                            

Top/niosII_tb.csv

@@ -1,12 +1,12 @@
-# system info niosII_tb on 2022.12.24.02:16:19
+# system info niosII_tb on 2023.01.17.19:01:35
 system_info:
 name,value
 DEVICE,EP4CE115F29C7
 DEVICE_FAMILY,Cyclone IV E
-GENERATION_ID,1671833747
+GENERATION_ID,1673967691
 #
 #
-# Files generated for niosII_tb on 2022.12.24.02:16:19
+# Files generated for niosII_tb on 2023.01.17.19:01:35
 files:
 filepath,kind,attributes,module,is_top
 niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
@@ -27,22 +27,22 @@ niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VER
 niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
 niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
 niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false
+niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false
+niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false
+niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
+niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false
+niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
+niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false
+niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
+niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
+niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false
 niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
 niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
 niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false

Top/niosII_tb.spd

@@ -101,70 +101,70 @@
    path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv"
    type="SYSTEM_VERILOG"
    library="cpu_data_master_translator" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc"
-   type="SDC"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v"
-   type="VERILOG"
-   library="cpu" />
  <file
    path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v"
    type="VERILOG"
    library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v"
-   type="VERILOG"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v"
-   type="VERILOG"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do"
-   type="OTHER"
-   library="cpu" />
  <file
    path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat"
    type="DAT"
    library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex"
-   type="HEX"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif"
-   type="MIF"
-   library="cpu" />
  <file
    path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat"
    type="DAT"
    library="cpu" />
  <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex"
+   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif"
-   type="HEX"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif"
    type="MIF"
    library="cpu" />
  <file
    path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat"
    type="DAT"
    library="cpu" />
+ <file
+   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do"
+   type="OTHER"
+   library="cpu" />
  <file
    path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex"
    type="HEX"
    library="cpu" />
+ <file
+   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v"
+   type="VERILOG"
+   library="cpu" />
+ <file
+   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v"
+   type="VERILOG"
+   library="cpu" />
  <file
    path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif"
    type="MIF"
    library="cpu" />
+ <file
+   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v"
+   type="VERILOG"
+   library="cpu" />
+ <file
+   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc"
+   type="SDC"
+   library="cpu" />
  <file
    path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v"
    type="VERILOG"
    library="cpu" />
+ <file
+   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex"
+   type="HEX"
+   library="cpu" />
+ <file
+   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif"
+   type="MIF"
+   library="cpu" />
+ <file
+   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex"
+   type="HEX"
+   library="cpu" />
  <file
    path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v"
    type="VERILOG"

Top/software/semafor/.settings/language.settings.xml

@@ -2,13 +2,12 @@
 <project>
 	<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" name="Nios II">
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-			<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="1701080960758821589" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="-136685873252219664" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
-			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="altera.tool.Nios2GCCBuildCommandParser" keep-relative-paths="false" name="Nios II GCC Build Output Parser" parameter="(nios2-elf-gcc)|(nios2-elf-g\+\+)" prefer-non-shared="true"/>
-			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
 		</extension>
 	</configuration>

Top/software/semafor/mem_init/hdl_sim/niosII_mem.sym

@@ -7,163 +7,163 @@
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+00007400 A __bss_end
-0000741c A _end
+00007400 A _end
-0000741c A end
+00007400 A end
-0000f290 A _gp
+0000f274 A _gp
 00020000 A __alt_data_end
 00020000 A __alt_heap_limit
 00020000 A __alt_stack_pointer

Top/software/semafor/obj/default/runtime/sim/mentor/wave.do

@@ -20,18 +20,18 @@ add wave -noupdate /niosII_tb/niosii_inst/sem/ctl_addr
 add wave -noupdate /niosII_tb/niosii_inst/sem/ctl_wrdata
 add wave -noupdate /niosII_tb/niosii_inst/sem/ctl_rddata
 add wave -noupdate /niosII_tb/niosii_inst/sem/ram_wr
-add wave -noupdate /niosII_tb/niosii_inst/sem/ram_addr
+add wave -noupdate -radix unsigned /niosII_tb/niosii_inst/sem/ram_addr
-add wave -noupdate /niosII_tb/niosii_inst/sem/ram_wrdata
+add wave -noupdate -radix hexadecimal /niosII_tb/niosii_inst/sem/ram_wrdata
 add wave -noupdate /niosII_tb/niosii_inst/sem/train
 add wave -noupdate /niosII_tb/niosii_inst/sem/red
 add wave -noupdate /niosII_tb/niosii_inst/sem/yellow
 add wave -noupdate /niosII_tb/niosii_inst/sem/green
 add wave -noupdate /niosII_tb/niosii_inst/sem/run
 add wave -noupdate /niosII_tb/niosii_inst/sem/divider
-add wave -noupdate /niosII_tb/niosii_inst/sem/divisor
+add wave -noupdate -radix hexadecimal /niosII_tb/niosii_inst/sem/divisor
 add wave -noupdate /niosII_tb/niosii_inst/sem/contr
 add wave -noupdate /niosII_tb/niosii_inst/sem/colors
-add wave -noupdate /niosII_tb/niosii_inst/sem/cntdiv
+add wave -noupdate -radix hexadecimal /niosII_tb/niosii_inst/sem/cntdiv
 add wave -noupdate /niosII_tb/niosii_inst/sem/enacnt
 add wave -noupdate -divider jtag
 add wave -noupdate /niosII_tb/niosii_inst/jtag_uart/av_irq
@@ -43,7 +43,7 @@ add wave -noupdate /niosII_tb/niosii_inst/jtag_uart/av_read_n
 add wave -noupdate /niosII_tb/niosii_inst/jtag_uart/av_write_n
 add wave -noupdate /niosII_tb/niosii_inst/jtag_uart/av_writedata
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {22 ps} 0}
+WaveRestoreCursors {{Cursor 1} {799999523 ps} 0}
 quietly wave cursor active 1
 configure wave -namecolwidth 275
 configure wave -valuecolwidth 100
@@ -59,6 +59,6 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {0 ps} {662 ps}
 
 run 800us
+wave zoom full

Top/software/semafor/sem.c

@@ -21,16 +21,15 @@ int main()
 	//program divisors
 	p = (alt_u32*) SEM_RAM_SLAVE_BASE;
 	for (i = 0; i < TIME_SETS; i++)	{
-		tmp = 0;
 		for (j = TIME_STATES; j > 0; j--) {
-			tmp = (tmp << 32) | divisors[i][j - 1];
+			*p = divisors[i][j - 1];
+            alt_dcache_flush();
+            ++p;
 		}
-		*p = tmp;
-		p++;
 	}
 	//since we use pointers (cached data access) to write divisor RAM, 
 	//and not direct i/o access with IOWR, we need to flush cache
-	alt_dcache_flush();
+    //    alt_dcache_flush();
 	
 	//select timeset and run semafor
 	IOWR_ALTERA_AVALON_SEM_DIVSET(SEM_CTL_SLAVE_BASE,0x00);

Top/software/semafor_bsp/.settings/language.settings.xml

@@ -2,7 +2,7 @@
 <project>
 	<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" name="Nios II">
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-			<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="1701080960758821589" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="-136685873252219664" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>

Top/software/semafor_bsp/settings.bsp

@@ -2,11 +2,11 @@
 <sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
         <BspType>hal</BspType>
         <BspVersion>default</BspVersion>
-        <BspGeneratedTimeStamp>24.12.2022 2:19:40</BspGeneratedTimeStamp>
+        <BspGeneratedTimeStamp>Jan 17, 2023 7:10:10 PM</BspGeneratedTimeStamp>
-        <BspGeneratedUnixTimeStamp>1671833980256</BspGeneratedUnixTimeStamp>
+        <BspGeneratedUnixTimeStamp>1673968210656</BspGeneratedUnixTimeStamp>
-        <BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation>
+        <BspGeneratedLocation>/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Top/software/semafor_bsp</BspGeneratedLocation>
         <BspSettingsFile>settings.bsp</BspSettingsFile>
-        <SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile>
+        <SopcDesignFile>../../niosII.sopcinfo</SopcDesignFile>
         <JdiFile>default</JdiFile>
         <Cpu>cpu</Cpu>
         <SchemaVersion>1.9</SchemaVersion>

Top/software/semafor_bsp/summary.html

@@ -7,7 +7,7 @@
 <td width="20%" bgcolor="#77BBFF">BSP Type:</td><td>hal</td>
 </tr>
 <tr mode="wrap">
-<td width="20%" bgcolor="#77BBFF">SOPC Design File:</td><td>..\..\niosII.sopcinfo</td>
+<td width="20%" bgcolor="#77BBFF">SOPC Design File:</td><td>../../niosII.sopcinfo</td>
 </tr>
 <tr mode="wrap">
 <td width="20%" bgcolor="#77BBFF">Quartus JDI File:</td><td>default</td>
@@ -22,13 +22,13 @@
 <td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
 </tr>
 <tr mode="wrap">
-<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>24.12.2022 2:19:40</td>
+<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>Jan 17, 2023 7:10:10 PM</td>
 </tr>
 <tr mode="wrap">
-<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671833980256</td>
+<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1673968210656</td>
 </tr>
 <tr mode="wrap">
-<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td>
+<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Top/software/semafor_bsp</td>
 </tr>
 </table>
 <br>